932SQL456 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: mreed
- PDF pages: 24
Technical content
932SQL456 REVISION B 09/29/15 1 Low-Power CK420BQ Derivative for PCIe Separate Clock Architectures 932SQL456 General Description The 932SQL456 is a low power version of the CK420BQ synthesizer for Intel-based server platforms. It has 85 ohm Low-Power (LP) HCSL outputs that save 48 resistors and reduce power consumption by 50% compared to the standard CK420BQ. The 932SQL456 is driven with a 25MHz crystal for maximum performance. It generates CPU outputs of 100MHz. This device meets Separate- Reference-no-Spread (SRnS) PCIe requirements making it ideal for use in systems that need to communicate outside the box. Recommended Application Low-Power CK420BQ for SRnS PCIe Applications Key Specifications
- CPU, SRC, NS_SRC and NS_SAS cycle-cycle jitter <50ps
- Output to output skew <50ps
- Phase jitter: PCIe Gen2 SRnS <2.2ps rms
- Phase jitter: PCIe Gen3 SRnS <0.7ps rms
- Phase jitter: QPI <0.3ps rms
- Phase jitter: NS-SAS <1.3ps rms using long period phase jitter method Features/Benefits
- Integrated 85-ohm differential terminations; saves 48 resistors compared to CK420BQ
- LP-HCSL outputs; up to 50% power savings compared to standard CK420BQ
- 64-pin TSSOP and VFQFPN packages; smallest board footprint
- Available in -40° to +85°C industrial temperature range version; supports demanding operating environments Output Features
- Differential outputs are LP-HCSL with integrated 85 terminations
- 11 non-spreading interchangeable 100MHz differential outputs
- 4 CPU outputs
- 3 SRC outputs
- 1 DOT96 96MHz output
- 1 3.3V 48M output
- 5 3.3V PCI outputs
- 1 3.3V 14.318M output Pin Configurations Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown GNDPCI VDDPCI PCI4_2x PCI3_2x PCI2_2x PCI1_2x PCI0_2x GNDPCI VDDPCI VDD48 48M_2x GND48 GND96 DOT96_Z85T DOT96_Z85C AVDD96 Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 2 REVISION B 09/29/15 932SQL456 DATASHEET 64TSSOP Pin Descriptions
REVISION B 09/29/15 3 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET 64TSSOP Pin Descriptions (cont.)
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 4 REVISION B 09/29/15 932SQL456 DATASHEET 64VFQFPN Pin Descriptions
REVISION B 09/29/15 5 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET 64VFQFPN Pin Descriptions (cont.)
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 6 REVISION B 09/29/15 932SQL456 DATASHEET Block Diagram Logic SRC_Z85(2:0) SMBDAT SMBCLK CKPWRGD#/PD CPU_Z85(3:0) Non-spreading PCIe PLL NS_SAS_Z85(1:0) NS_SRC_Z85(1:0) DOT96_Z85 48M_2x PCI_2x(4:0) 14.31818MHz Non-SS PLL REF14_2x Test_Mode Test_Sel Non-SS PLL IDT 603-25-150JA4C or 603-25-150JA4I 25M X1_25
REVISION B 09/29/15 7 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Power Supply and Test Loads Alternate Terminations The 932SQL456 can also drive other logic levels such as LVPECL, LVDS, and CML. See AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's "Universal" Low-Power HCSL Outputs for details. Low-Power Differential Output (w/Integrated Rs) Test Load 2pF 10 inches Zo = 85 2pF Rs=27 CL=5pF 10 inches Zo = 50 Single-ended Output Test Load Rs=29 and 20 inches for REF Alternate termination for driving 100 transmission lines 2pF Zo = 100 2pF Rs=7.5 Rs=7.5 Rs=16 Zo = 50 CL=5pF Rs=16 Zo = 50 CL=5pF Alternate termination for driving 2 50 loads
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 8 REVISION B 09/29/15 932SQL456 DATASHEET Functionality Tables Clock AC Tolerances Clock Periods–Outputs
REVISION B 09/29/15 9 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 932SQL456. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Electrical Characteristics–Current Consumption Outputs
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 10 REVISION B 09/29/15 932SQL456 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters
REVISION B 09/29/15 11 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Outputs Electrical Characteristics–48MHz V/ns dV/dt % ps ns
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 12 REVISION B 09/29/15 932SQL456 DATASHEET Electrical Characteristics–PCI Electrical Characteristics–Phase Jitter Parameters ns 2.6/3 3.1 0.6 1 0.6 0.7
REVISION B 09/29/15 13 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Test Clarification Table ns
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 14 REVISION B 09/29/15 932SQL456 DATASHEET General SMBus Serial Interface Information for 932SQL456 How to Write
- Controller (host) sends a start bit
- Controller (host) sends the write address
- IDT clock will acknowledge
- Controller (host) sends the beginning byte location = N
- IDT clock will acknowledge
- Controller (host) sends the byte count = X
- IDT clock will acknowledge
- Controller (host) starts sending Byte N through Byte N+X-1
- IDT clock will acknowledge each byte one at a time
- Controller (host) sends a Stop bit How to Read
- Controller (host) will send a start bit
- Controller (host) sends the write address
- IDT clock will acknowledge
- Controller (host) sends the beginning byte location = N
- IDT clock will acknowledge
- Controller (host) will send a separate start bit
- Controller (host) sends the read address
- IDT clock will acknowledge
- IDT clock will send the data byte count = X
- IDT clock sends Byte N+X-1
- IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
- Controller (host) will need to acknowledge each byte
- Controller (host) will send a not acknowledge bit
- Controller (host) will send a stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit Read Address Write Address D3(H) D2(H) Index Block Read Operation Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge P stoP bit
REVISION B 09/29/15 15 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 16 REVISION B 09/29/15 932SQL456 DATASHEET
REVISION B 09/29/15 17 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Recommended Crystal Characteristics (3225 package) Marking Diagrams Notes: 1. L denotes Pb-free, RoHS compliant. 2. LOT denotes the lot number. 3. YYWW denotes the last two digits and week the part was assembled. 4. COO denotes the country of origin. 5. A denotes the device revision designator. 6. Bottom marking (TSSOP only): country of origin. C C 64TSSOP ICS LOT YYWW 932SQL456AGL 64VFQFPN ICS 932SQL456AL LOT COO YYWW 64TSSOP ICS LOT YYWW 932SQL456AIL 64VFQFPN ICS 32SQL456AIL LOT COO YYWW
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 18 REVISION B 09/29/15 932SQL456 DATASHEET Package Outline and Package Dimensions (64-pin TSSOP) INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.20 .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 0.32 0.41 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D 16.90 17.10 .665 .673 E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC aaa 0.10 .004 L 0.45 0.75 .018 .030 a 0 8 0 8
REVISION B 09/29/15 19 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 20 REVISION B 09/29/15 932SQL456 DATASHEET
REVISION B 09/29/15 21 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 22 REVISION B 09/29/15 932SQL456 DATASHEET
Ordering Information
"LF" suffix to the part number denotes Pb-Free configuration, RoHS6.6 compliant. “A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Order Number Shipping Packaging Package Temperature 932SQL456AGLF Tubes 64-pin TSSOP 0 to +70° C 932SQL456AGLFT Tape and Reel 64-pin TSSOP 0 to +70° C 932SQL456AKLF Tray 64-pin VFQFPN 0 to +70° C 932SQL456AKLFT Tape and Reel 64-pin VFQFPN 0 to +70° C 932SQL456AGILF Tubes 64-pin TSSOP -40 to +85° C 932SQL456AGILFT Tape and Reel 64-pin TSSOP -40 to +85° C 932SQL456AKILF Tray 64-pin VFQFPN -40 to +85° C 932SQL456AKILFT Tape and Reel 64-pin VFQFPN -40 to +85° C
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