932SQL450 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: mreed
  • PDF pages: 24

Technical content

932SQL450 REVISION B 03/06/15 1 Low-Power CK420BQ Derivative for PCIe Common Clock Architectures 932SQL450 General Description The 932SQL450 is a low power version of the CK420BQ synthesizer for Intel-based server platforms. It has 85-ohm LP-HCSL outputs allowing for direct connection to 85-ohm transmission lines. The 932SQL450 is driven with a 25MHz crystal for maximum performance. It generates CPU outputs of 100MHz. This device has a “low-drift” non-spread SAS/SRC PLL for use in systems that need to communicate across PCIe domains. Recommended Application Low Power CK420BQ w/Zout=85ohms or PCIe Common Clocked Systems (CC) Key Specifications

  • CPU, SRC, NS_SRC and NS_SAS cycle-cycle jitter <50ps
  • Output to output skew <50ps
  • Phase jitter: PCIe Gen2 <2.5ps rms
  • Phase jitter: PCIe Gen3 <0.6ps rms
  • Phase jitter: QPI <0.3ps rms
  • Phase jitter: NS-SAS <1.3ps rms using long period phase jitter method Features/Benefits
  • Integrated 85 ohm differential terminations; saves 48 resistors and 82mm2 area
  • LP-HCSL output drivers; 40% typical power savings over 932SQ420
  • 0.5% down spread capable on CPU, SRC and PCI outputs; reduce EMI
  • Additional down spread amounts selectable via SMBus; maximal system flexibility
  • 64-pin TSSOP and VFQFPN packages; smallest board footprint Output Features
  • 4 - Low-Power HCSL-compatible (LP-HCSL) CPU outputs
  • 2 - LP-HCSL NS_SAS outputs
  • 2 - LP-HCSL NS_SRC outputs
  • 3 - LP-HCSL SRC outputs
  • 1 - LP-HCSL DOT96 output
  • 1 - 3.3V 48M output
  • 5 - 3.3V PCI outputs
  • 1 - 3.3V 14.318M output Pin Configurations Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown GNDPCI VDDPCI PCI4_2x PCI3_2x PCI2_2x PCI1_2x PCI0_2x GNDPCI VDDPCI VDD48 48M_2x GND48 GND96 DOT96_Z85T DOT96_Z85C AVDD96 Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 2 REVISION B 03/06/15 932SQL450 DATASHEET 64TSSOP Pin Descriptions

REVISION B 03/06/15 3 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET 64TSSOP Pin Descriptions (cont.)

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 4 REVISION B 03/06/15 932SQL450 DATASHEET 64VFQFPN Pin Descriptions

REVISION B 03/06/15 5 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET 64VFQFPN Pin Descriptions (cont.)

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 6 REVISION B 03/06/15 932SQL450 DATASHEET Block Diagram CPU_SRC_PCI PLL (SS) Low Drift non- SS PLL <500ps LTJ Non-SS PLL 14.31818MHz Non-SS PLL Logic SMBCLK SMBDAT CKPWRGD#/PD Test_Mode Test_Sel REF14_2x /2 48M_2x X1_25 X2_25 CPU(3:0)_Z85 SRC(2:0)_Z85 PCI(4:0)_2x NS_SAS(1:0)_Z85 NS_SRC(1:0)_Z85 DOT96_Z85

REVISION B 03/06/15 7 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET Power Supply and Test Loads Alternate Terminations Low-Power Differential Output (w/Integrated Rs) Test Load 2pF 10 inches Zo = 85 2pF Rs=27 CL=5pF 20 inches Zo = 50 Single-ended Output Test Load Alternate termination for driving 100 transmission lines 2pF Zo = 100 2pF Rs=7 Rs=7 Rs=16 Zo = 50 CL=5pF Rs=16 Zo = 50 CL=5pF Alternate termination for driving 2 50 loads

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 8 REVISION B 03/06/15 932SQL450 DATASHEET Functionality and CPU SAS Frequency Tables

REVISION B 03/06/15 9 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET Clock AC Tolerances Clock Periods–Outputs with Spread Spectrum Disabled Clock Periods–Outputs with Spread Spectrum Enabled

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 10 REVISION B 03/06/15 932SQL450 DATASHEET General SMBus Serial Interface Information for 932SQL450 How to Write

  • Controller (host) sends a start bit
  • Controller (host) sends the write address
  • IDT clock will acknowledge
  • Controller (host) sends the beginning byte location = N
  • IDT clock will acknowledge
  • Controller (host) sends the byte count = X
  • IDT clock will acknowledge
  • Controller (host) starts sending Byte N through Byte N+X-1
  • IDT clock will acknowledge each byte one at a time
  • Controller (host) sends a Stop bit How to Read
  • Controller (host) will send a start bit
  • Controller (host) sends the write address
  • IDT clock will acknowledge
  • Controller (host) sends the beginning byte location = N
  • IDT clock will acknowledge
  • Controller (host) will send a separate start bit
  • Controller (host) sends the read address
  • IDT clock will acknowledge
  • IDT clock will send the data byte count = X
  • IDT clock sends Byte N+X-1
  • IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
  • Controller (host) will need to acknowledge each byte
  • Controller (host) will send a not acknowledge bit
  • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK P stoP bit Read Address Write Address D3(H) D2(H) Index Block Read Operation Controller (Host) IDT (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge P stoP bit

REVISION B 03/06/15 11 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 12 REVISION B 03/06/15 932SQL450 DATASHEET

REVISION B 03/06/15 13 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 932SQL450. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Electrical Characteristics–Current Consumption (CPU, SRC, NS_SAS, NS_SRC, DOT96)

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 14 REVISION B 03/06/15 932SQL450 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters

REVISION B 03/06/15 15 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET (CPU, SRC, NS_SAS, NS_SRC, DOT96) Electrical Characteristics–48MHz V/ns dV/dt % ns

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 16 REVISION B 03/06/15 932SQL450 DATASHEET Electrical Characteristics–Phase Jitter Parameters Electrical Characteristics–PCI 3.1 ns

REVISION B 03/06/15 17 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET Test Clarification Table ns

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 18 REVISION B 03/06/15 932SQL450 DATASHEET Recommended Crystal Characteristics (3225 package) Marking Diagrams Notes: 1. “L” denotes Pb-free, RoHS compliant. 2. “LOT” denotes the lot number. 3. “YYWW” denotes the last two digits and week the part was assembled. 4. “COO” denotes the country of origin. 5. “B” denotes the device revision designator. 6. Bottom marking (TSSOP only): country of origin. C C 64TSSOP ICS LOT YYWW 932SQL450BGL 64VFQFPN ICS 932SQL450BL LOT COO YYWW

REVISION B 03/06/15 19 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET Package Outline and Package Dimensions (64-pin TSSOP) INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A – 1.20 – .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 0.32 0.41 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D 16.90 17.10 .665 .673 E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC aaa – 0.10 – .004 L 0.45 0.75 .018 .030 a 0 8 0 8

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 20 REVISION B 03/06/15 932SQL450 DATASHEET Package Outline and Package Dimensions (64-pin VFQFPN)

REVISION B 03/06/15 21 LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 932SQL450 DATASHEET Package Outline and Package Dimensions (64-pin VFQFPN), cont.

LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES 22 REVISION B 03/06/15 932SQL450 DATASHEET

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. “B” is the device revision designator (will not correlate with the datasheet revision).

Revision History

Part / Order Number Shipping Packaging Package Temperature 932SQL450BGLF Tubes 64-pin TSSOP 0 to +70° C 932SQL450BGLFT Tape and Reel 64-pin TSSOP 0 to +70° C 932SQL450BKLF Tray 64-pin VFQFPN 0 to +70° C 932SQL450BKLFT Tape and Reel 64-pin VFQFPN 0 to +70° C

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