932SQ428

932SQ428 RENESAS | Alldatasheet

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• Manufacturer or author: mamiller
• PDF pages: 23

Technical content

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 932SQ428 IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 1 932SQ428 REV E 042312 General Description The 932SQ428 is a main clock synthesizer for Romley-generation Intel based server platforms. The 932SQ428 is driven with a 25 MHz crystal for maximum performance. It generates CPU outputs of 100MHz. Recommended Application CK420BQ Output Features

• 2 - HCSL Non-Spread SAS outputs
• 3 - HCSL SRC outputs - can be used as CPU@100M
• 1 - HCSL DOT96 output
• 1 - 3.3V 48M output
• 5 - 3.3V PCI outputs
• 1 - 3.3V 14.318M output Features/Benefits
• 0.5% down spread capable on SRC/PCI outputs; Lower EMI
• 48-pin MLF package; Space Savings Key Specifications
• Cycle to cycle jitter: SRC/NS_SAS < 50ps
• Phase jitter: PCIe Gen2 <3ps rms
• Phase jitter: PCIe Gen3 <1ps rms
• Phase jitter: QPI 9.6GB/s <0.2ps rms
• Phase jitter: NS-SAS <0.4ps rms using raw phase data
• Phase jitter: NS-SAS <1.3ps rms using Clk Jit Tool 1.6.3 Block Diagram

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 2 932SQ428 REV E 042312 Pin Configuration 932SQ428 Functionality Spread Spectrum Control Power Group Table 932SQ428 Power Down Functionality X2_25 X1_25 GNDXTAL GND14 REF14_3x VDD14 AVDD14 GND14 SMBCLK SMBDATA GND VDD 48 47 46 45 44 43 42 41 40 39 38 37 VDDXTAL 1 36 GNDNS GNDPCI 2 35 AVDDNS PCI4_2x 33 4 NS_SAS1T PCI3_2x 43 3 NS_SAS1C PCI2_2x 53 2 GNDNS PCI1_2x 63 1 VDDNS PCI0_2x 73 0 NS_SAS0T VDDPCI 82 9 NS_SAS0C VDD48 92 8 IREF 48M_2x 10 27 GNDSRC GND48 11 26 AVDDSRC GND96 12 25 VDDSRC 13 14 1 5 16 17 1 8 19 20 21 22 23 24 DOT96T DOT96C VDD96 CKPWRGD#/PD VDDSRC SRC0T SRC0C GNDSRC SRCC1 SRCT1 SRCC2 SRCT2 48-Pin MLF (6x6mm 0.4mm pitch) Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown 932SQ428 SRC PCI REF NS_SAS DOT96 USB Unit SS_Enable (B1b0) SRC & PCI 0O F F 1O N VDD GND 42 41 43 45 14 6 91 1 15 12 17, 25 20 26 27 31 32 35 36 37 38 Core Logic NS-SAS PLL Analog Non-Spreading Differential Outputs & Logic SRC PLL Analog REF14M Output and Logic 14MHz PLL Analog 25MHz XTAL SRC Outputs and Logic 96MHz PLL Analog, Output and Logic 48MHz Output and Logic MLF Descript ion PCI Outputs and Logic CKPWRGD#/PD Differential Outputs Single-ended Outputs Single ended Outputs w/Latch 1H I-Z Low Low 2. These outputs are Hi-Z after VDD is applied and before the first as sertion of CKPWRGD#. Running Hi-Z on the differential outputs will result in both True and Complement being low due to the termination network

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 3 932SQ428 REV E 042312 Pin Descriptions PIN # PIN NAME TYPE DESCRIPTION 1V D D X T A L PWR 3.3V power for the crystal oscillator. 2 GNDPCI PWR Ground pin for PCI outputs and logic. 3 PCI4_2x OUT 3.3V PCI clock output 4 PCI3_2x OUT 3.3V PCI clock out put 5 PCI2_2x OUT 3.3V PCI clock out put 6 PCI1_2x OUT 3.3V PCI clock out put 7 PCI0_2x OUT 3.3V PCI clock output 8 VDDPCI PWR 3.3V power for the PCI outputs and logic 9 VDD48 PWR 3.3V power for the 48MHz output and lo gic 10 48M_2x OUT 3.3V 48MHz out put 11 GND48 PWR Ground pin for 48MHz output and logic. 12 GND96 PWR Ground pin for DOT96 output and logic.

13 DOT96T OUT

True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 14 DOT96C OUT Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 15 VDD9 6 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic

16 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 17 VDDSRC PWR 3.3V power for the SRC outputs and logic

18 SRC0T OUT

True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 19 SRC0C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

20 GNDSRC PWR Ground

pin for SRC outputs and logic. 21 SRCC1 OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

22 SRCT1 OUT

True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 23 SRCC2 OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

24 SRCT2 OUT

True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 25 VDDSRC PWR 3.3V power for the SRC outputs and logic 26 AVDDSRC PWR 3.3V power for the SRC PLL analog circuits 27 GNDSRC PWR Ground pin for SRC outputs and logic.

28 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 29 NS_SAS0C OUT Complementary clock of differential non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

30 NS_SAS0T OUT

True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 31 VDDNS PWR 3.3V power for the Non-Spreading differential outputs outputs and logic 32 GNDNS PWR Ground pin for non-spreadin g differential outputs and logic. 33 NS_SAS1C OUT Complementary clock of differential non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

34 NS_SAS1T OUT

True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 4 932SQ428 REV E 042312 Pin Descriptions (cont.) 35 AVDDNS PWR 3.3V power for the non-spreading SAS PLL analog circuits. 36 GNDNS PWR Gro und pin for non-spreading differential outputs and logic. 37 VDD PWR 3.3V power for core logic 38 GND PWR Ground pin for core logic.

39 SMBDATA I/O Data pin of SMBUS circuitry, 5V tolerant

40 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

41 GND14 PWR Ground pin for 14MHz output and logic.

42 AVDD14 PWR Analo g power pin for 14MHz PLL

43 VDD14 PWR Power pin for 14MHz output and logic, nominal 3.3V 44 REF14_3x OUT 14.318 MHz reference clock. 3X drive stren gth as default 45 GND14 PWR Ground pin for 14MHz output and logic. 46 GNDXTAL PWR Ground pin for Crystal Oscillator. 47 X1_25 IN Cr ystal input, Nominally 25.00MHz. 48 X2_25 OUT Cr ystal output, Nominally 25.00MHz.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 5 932SQ428 REV E 042312 Test Loads and Recommended Terminations Differential Zo Rp Rp HSCL Output Buffer 932SQ420 Differential Test Loads Rs Rs 2pF 2pF Single-ended Output Termination Table Output Loads Zo = 50Ω Zo =6 0Ω PCI/USB 1 36 43 PCI/USB 2 22 33 REF 1 39 47 REF 2 27 36 REF 3 10 20 Rs Value (for each load) 932SQ428 Differential Output Termination Table DIF Zo (Ω)I r e f ( Ω)R s ( Ω)R p ( Ω) 100 475 33 50 85 412 27 42.2 or 43.2

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 6 932SQ428 REV E 042312 Electrical Characteristics - Absolute Maximum Ratings Electrical Characteristics - Current Consumption PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V 1,2 3.3V Logic Supply Voltage VDD 4.6 V 1,2 Input Low Voltage VIL GN D-0 .5 V 1 Input High Voltage V IH Except for SMBus interface VDD+0.5V V 1 Input High Voltage V IHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 Junction Temperature Tj 125 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 Guaranteed by design and characterization, not 100% tested in production. Operation under these conditions is neither im plied nor guaranteed. TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current I DD3.3OP All outputs active @100MHz, C L = Full load; 250 300 mA 1 Powerdown Current IDD 3.3PD Z All differential pairs tri-stated 12 20 mA 1 Guar anteed by design and characterization, not 100% tested in production. TA = TCO M; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate Trf Scope averaging on 1 2.4 4 V/ns 1, 2, 3 Slew rate matching ΔTrf Slew rate matching, Scope averaging on 92 0 % 1, 2, 4 Rise/Fall Time Variation ΔTrf Rise/fall variation, Scope averaging off 18 125 ps 1, 7, 8 Voltage HighV High 660 772 850 1 Voltage Low VLow -150 9 150 1 Max Voltage Vmax 810 1150 1, 7 Min Voltage Vmin -300 -17 1, 7 Vswing Vswing Scope averaging off 300 1446 mV 1, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 351 550 mV 1, 5 Crossing Voltage (var) Δ-Vcross Scope averaging off 24 140 mV 1, 6 Measured from differential waveform Includes over shoot and under shoot. Statistical measurement on single-ended signal using mV Measurement on single ended signal using absolute value. mV Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR R). For R R = 475Ω (1%), IREF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance). Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential risi ng edge (i.e. Clock rising and Clock# falling). The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cros s absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 7 932SQ428 REV E 042312 Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Ambient Operating Temper ature TCOM Commmercial range 0 70 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus, low threshold and tri- level inputs 2 VDD + 0.3 V1 Input Low Voltage VIL Single-ended inputs, except SMBus, low threshold and tri- level inputs GND - 0.3 0.8 V 1 IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1 IINP Single-ended inputs. VIN = 0 V; Inputs with internal pull - up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 Low Threshold Input- High Voltage VIH _FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 Low Threshold Input- Low Voltage VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 Input Frequency Fi 25.00 MHz 2 Pin Inductance Lp in 7n H 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 5 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de- assertion of PD# to 1st clock 1.8 ms 1,2 SS Modulation Frequency fMO DI N Allowable Fr equency (Triangular Modulation ) 30 31.500 33 kHz 1 Tdrive_PD# tDR VPD Differential output enable after PD# de-assertion 200.000 300 us 1,3 Tfall t F Fall time of control inputs 5 ns 1,2 Trise tR Rise time of control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB 0.8 V 1 SMBus Input High Voltage VIHSMB 2.1 VDD SMB V1 SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1 SMBus Sink Current I PULLUP @ VOL 4m A 1 Nominal Bus Voltage VDDSM B 3V to 5V +/- 10% 2.7 5.5 V 1 SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are >200 mV Input Current Capacitance

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 8 932SQ428 REV E 042312 Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle t DC Measured differ entially, PLL Mode 45 50.1 55 % 1 Skew, Output to Output tsk 3SRC Across all SRC outputs, VT = 50% 13.5 50 ps 1 SRC, NS_SAS outputs 35 50 ps 1,3 DOT96 output 75 250 ps 1,3 Guaranteed b y design and characterization, not 100% tested in production. Measured from differential waveform Jitter, Cycle to cycle tjc y c- c yc TA = 0 - 70°C; Supply Voltage V DD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes tjphPCIeG1 PCIe Gen 1 28 86 ps (p-p) 1,2,3,6 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.9 3 ps (rms) 1,2,6 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 1.7 3.1 ps (rms) 1,2,6 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.4 1 ps (rms) 1,2,4,6 QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.15 0.5 ps (rms) 1,5,6 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.13 0.3 ps (rms) 1,5,6 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.11 0.2 ps (rms) 1,5,6 tjphSAS12G SAS12G (Filtered REFCLK Jitter 20KHz to 20MHz.) 0.34 0.4 ps (rms) 1,7,8 tjphSAS12G SAS 12G 0.70 1.3 ps (rms) 1,5,7 1 Guaranteed by design and characterization, not 100% tested in production.

6 Applies to SRC outputs

7 Applies to NS_SAS, NS_SRC outputs, Spread Off

8 Intel calculation from raw phase noise data

4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.6 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. tjphQPI_SMI Phase Jitter 2 See http://www.pcisig.com for complete specs

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 9 932SQ428 REV E 042312 Electrical Characteristics - PCI Electrical Characteristics - 48MHz TA = 0 - 70°C; Supply Voltage V DD /VDD A = 3.3 V +/-5% , PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 O utput Low Voltage V OL IOL = 1 mA 0.55 V 1 MIN @VOH = 1.0 V -33 mA 1 MAX @V OH = 3.135 V -33 mA 1 MIN @VOL = 1.95 V 30 mA 1 MAX @ VOL = 0.4 V 38 mA 1 Clock High Time T HIGH 1.5V 12 ns 1 Clock Low Time TLO W 1.5V 12 ns 1 Edge Rate tsl ewr/f Rising/Falling edge rate 1 1.8 4 V/ns 1,2 Duty Cycle dt1 VT = 1.5 V 45 50.5 55 %1 Group Skew tskew VT = 1.5 V 294 500 ps 1 Jitter, Cycle to cycle tjc yc-cy c VT = 1.5 V 108 500 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. Measured between 0.8V and 2.0V Output High Current IOH Output Low Current IOL TA = 0 - 70°C; Supply Voltage V DD/VDD A = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD*(0.5) 20 60 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 O utput Low Voltage V OL IOL = 1 mA 0.55 V 1 MIN @VOH = 1.0 V -29 mA 1 MAX @V OH = 3.135 V -33 mA 1 MIN @VOL = 1.95 V 29 mA 1 MAX @ VOL = 0.4 V 27 mA 1 Clock High Time T HIGH 1.5V 8.094 10.036 ns 1 Clock Low Time TLO W 1.5V 7.694 9.836 ns 1 Edge Rate tslewr/f_USB Rising/Falling edge rate 1 1.5 2 V/ns 1,2 Duty Cycle dt1 VT = 1 . 5 V 4 55 15 5 % 1 Jitter, Cycle to cycle tjc yc-cy c VT = 1.5 V 109 350 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. Measured between 0.8V and 2.0V Output High Current IOH Output Low Current IOL

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 10 932SQ428 REV E 042312 Electrical Characteristics - REF TA = 0 - 70°C; Supply Voltage V DD/ VDD A = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Output Impedance R DSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 O utput Low Voltage V OL IOL = 1 mA 0.55 V 1 MIN @VOH = 1.0 V -33 mA 1 MAX @V OH = 3.135 V -33 mA 1 MIN @VOL = 1.95 V 30 mA 1 MAX @ VOL = 0.4 V 38 mA 1 Clock High Time T HIGH 1.5V 27.5 ns 1 Clock Low Time T LO W 1.5V 27.5 ns 1 Edge Rate t sl ewr/f Rising/Falling edge rate 1 1.9 4 V/ns 1,2 Duty Cycle dt1 VT = 1.5 V 45 50.5 55 % 1 Jitter, Cycle to cycle tjc yc-cy c VT = 1.5 V 75 1000 ps 1 See "Single-ended Test Loads Page" for termination circuits Guaranteed by design and characterization, not 100% tested in production. Measured between 0.8V and 2.0V Output High Current IOH Output Low Current IOL

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 11 932SQ428 REV E 042312 Clock AC Tolerances Clock Periods – Outputs with Spread Spectrum Disabled Clock Periods – Outputs with Spread Spectrum Enabled SRC, NS_SAS PCI DOT96 48MHz REF 100 100 100 100 100 ppm 50 500 250 350 1000 ps PPM tolerance Cycle to Cycle Jitter 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max SRC, SSC ON Cent er Freq. MHz Measurement Window Units Notes 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - p pm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max Guaranteed b y design and characterization, not 100% tested in pro ductio n. All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz. SSC ON Cent er Freq. MHz Measurement Window Units Notes

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 12 932SQ428 REV E 042312 General SMBus Serial Interface Information How to Write

• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit SMBus write address = D2 hex SMBus read address = D3 hex How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK Ps t o P b i t Index Block Read Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge Ps t o P b i t

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 13 932SQ428 REV E 042312 SMBus Table: Output Enable Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 DOT96 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 6 NS_SAS1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 1 Bit 4 NS_SAS0 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 1 Bit 2 SRC2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 SRC1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 0 SRC0 Enable Output Enable RW Disable-Hi-Z Enable 1 SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 REF14_3x Enable Output Enable RW Disable-Low Enable 1 Bit 6 0 Bit 5 0 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 Spread Spectr um Enable Spread Off/On RW Spread Off Spr ead On 0 SMBus Table: Output Enable Re gister Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 PCI4 Enable Output Enable RW Disable-Low Enable 1 Bit 4 PCI3 Enable Output Enable RW Disable-Low Enable 1 Bit 3 PCI2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 PCI1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 PCI0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 48MHz Enable Output Enable RW Disable-Low Enable 1 Byte 3 ~ Byte 4 Reserved Register SMBus Table: NS_SAS Frequenc y Margining Table Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 FS4 Fre q. Sel 4 R W 0 Bit 3 FS3 Freq. Sel 3 R W 1 Bit 2 FS2 Freq. Sel 2 R W 1 Bit 1 FS1 Freq. Sel 1 R W 1 Bit 0 FS0 Freq. Sel 0 RW 1 SMBus Table: SRC/PCI Frequency Select Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 1 Bit 3 FS3 Freq. Sel 3 RW 1 Bit 2 FS2 Freq. Sel 2 RW 0 Bit 1 FS1 Freq. Sel 1 RW 0 Bit 0 FS0 Freq. Sel 0 RW 0 RESERVED Byte 0 SRC/PCI Byte 2 Byte 1 RESERVED RESERVED Byte 5 RESERVED RESERVED RESERVED RESERVED See NS_SAS Frequency Table Byte 6 See SRC/PCI Frequency Select Table RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 14 932SQ428 REV E 042312 SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Type 0 1 Default Bit 7 RID3 R 0 Bit 6 RID2 R 0 Bit 5 RID1 R 1 Bit 4 RID0 R 1 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 SMBus Table: Byte Count Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 0 Bit 1 BC1 RW 1 Bit 0 BC0 RW 0 SMBus Table: Device ID Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 DID7 R - - 0 Bit 6 DID6 R- - 0 Bit 5 DID5 R - - 0 Bit 4 DID4 R- - 1 Bit 3 DID3 R - - 0 Bit 2 DID2 R - - 1 Bit 1 DID1 R - - 1 Bit 0 DID0 R - - 1 SMBus Table: M/N Programming & Control Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 M/N_EN SRC M/N Programming Enable RW Disable Enable 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 SMBus Table: SRC/PCI Frequency Control Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 SRC N Div8 N Divider Prog bit 8 RW X Bit 6 SRC N Div9 N Divider Prog bit 9 RW X Bit 5 SRC M Div5 RW X Bit 4 SRC M Div4 RW X Bit 3 SRC M Div3 RW X Bit 2 SRC M Div2 RW X Bit 1 SRC M Div1 RW X Bit 0 SRC M Div0 RW X Byte 7 REVISION ID 0011 for A rev- VENDOR ID 0001 for ICS/IDT- Writing to this register will configure how many bytes will be read back, default is A bytes (0 to 9) Byte 8 Byte Count Programming b(7:0) RESERVED Byte 9 Device ID (17 hex) Byte 10 -R E S E R V E D -R E S E R V E D -R E S E R V E D -R E S E R V E D -R E S E R V E D -R E S E R V E D Byte 11 - The decimal representation of M and N Divider in Byte 11 and 12 will configure the SRC VCO frequency. Default at power up = latch-in or Byte 6 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] M Divider Programming bit (5:0)

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 15 932SQ428 REV E 042312 SMBus Table: SRC Frequency Control Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 SRC N Div7 RW X Bit 6 SRC N Div6 RW X Bit 5 SRC N Div5 RW X Bit 4 SRC N Div4 RW X Bit 3 SRC N Div3 RW X Bit 2 SRC N Div2 RW X Bit 1 SRC N Div1 RW X Bit 0 SRC N Div0 RW X SMBus Table: SRC Spread Spectrum Control Re gister Pin # Name Control Function Type 0 1 Defaul t Bit 7 SRC SSP7 RW X Bit 6 SRC SSP6 RW X Bit 5 SRC SSP5 RW X Bit 4 SRC SSP4 RW X Bit 3 SRC SSP3 RW X Bit 2 SRC SSP2 RW X Bit 1 SRC SSP1 RW X Bit 0 SRC SSP0 RW X SMBus Table: SRC Spread Spectrum Control Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 0 Bit 6 SRC SSP14 R W X Bit 5 SRC SSP13 R W X Bit 4 SRC SSP12 R W X Bit 3 SRC SSP11 R W X Bit 2 SRC SSP10 R W X Bit 1 SRC SSP9 R W X Bit 0 SRC SSP8 RW X SMBus Table: NS_SAS Frequency Control Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 NS_SAS N Div8 N Divider Prog bit 8 RW X Bit 6 NS_SAS N Div9 N Divider Prog bit 9 RW X Bit 5 NS_SAS M Div5 RW X Bit 4 NS_SAS M Div4 RW X Bit 3 NS_SAS M Div3 RW X Bit 2 NS_SAS M Div2 RW X Bit 1 NS_SAS M Div1 RW X Bit 0 NS_SAS M Div0 RW X SMBus Table: NS_SAS Frequenc y Control Re gister Pin # Name Control Function Type 0 1 Defaul t Bit 7 NS_SAS N Div7 RW X Bit 6 NS_SAS N Div6 RW X Bit 5 NS_SAS N Div5 RW X Bit 4 NS_SAS N Div4 RW X Bit 3 NS_SAS N Div3 RW X Bit 2 NS_SAS N Div2 RW X Bit 1 NS_SAS N Div1 RW X Bit 0 NS_SAS N Div0 RW X N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) The decimal representation of M and N Divider in Byte 11 and 12 will configure the SRC VCO frequency. Default at power up = latch-in or Byte 6 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] Byte 12 - Reserved Byte 13 Spread Spectrum Pr ogramming bit(7:0) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of SRC Byte 14 Spread Spectrum Programming bit(14:8) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of SRC The decimal representation of M and N Divider in Byte 15 and 16 will configure the NS_SAS VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2] M Divider Programming bits (Fixed at 1 for Rev Byte 15 Byte 16 N Divider Programming b(7:0) The decimal represen tation of M and N Divider in Byte 15 and 16 will configure the NS_SAS VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 25 x [NDiv(9:0)+8] / [MDiv(5:0)+2]

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 16 932SQ428 REV E 042312 Line Byte 1, Bit 0 Spread Enable Byte6 Bit3 FS3 Byte6 Bit2 FS2 Byte6 Bit1 FS1 Byte6 Bit0 FS0 SRC (MHz) PCI (MHz) Spread 0 0 0 0 0 0 89.97 29.99 1 0 0 0 0 1 91.28 30.43 2 0 0 0 1 0 92.58 30.86 3 0 0 0 1 1 93.75 31.25 4 0 0 1 0 0 95.05 31.68 5 0 0 1 0 1 96.22 32.07 6 0 0 1 1 0 97.53 32.51 7 0 0 1 1 1 98.83 32.94 8 0 1 0 0 0 100.00 33.33 9 0 1 0 0 11 0 1 . 3 03 3 . 7 7 10 0 1 0 1 01 0 2 . 4 73 4 . 1 6 11 0 1 0 1 1 103.78 34.59 12 0 1 1 0 01 0 5 . 0 83 5 . 0 3 13 0 1 1 0 11 0 6 . 2 53 5 . 4 2 14 0 1 1 1 01 0 7 . 5 53 5 . 8 5 15 0 1 1 1 11 1 0 . 0 33 6 . 6 8 16 1 0 0 0 0 89.97 29.99 17 1 0 0 0 1 91.28 30.43 18 1 0 0 1 0 92.58 30.86 19 1 0 0 1 1 93.75 31.25 20 1 0 1 0 0 95.05 31.68 21 1 0 1 0 1 96.22 32.07 22 1 0 1 1 0 97.53 32.51 23 1 0 1 1 1 98.83 32.94 24 1 1 0 0 01 0 0 . 0 03 3 . 3 3 25 1 1 0 0 11 0 1 . 3 03 3 . 7 7 26 1 1 0 1 01 0 2 . 4 73 4 . 1 6 27 1 1 0 1 11 0 3 . 7 83 4 . 5 9 28 1 1 1 0 01 0 5 . 0 83 5 . 0 3 29 1 1 1 0 11 0 6 . 2 53 5 . 4 2 30 1 1 1 1 01 0 7 . 5 53 5 . 8 5 31 1 1 1 1 11 1 0 . 0 33 6 . 6 8 SRC/PCI Frequency Selection Table -0.5%

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 17 932SQ428 REV E 042312 Line Byte5 Bit 4 FS4 Byte5 Bit3 FS3 Byte5 Bit2 FS2 Byte5 Bit1 FS 1 Byte5 Bit0 FS0 NS_xxx (MHz) 0 0 0 0 0 0 58.33 1 0 0 0 0 1 61.11 2 0 0 0 1 0 63.89 3 0 0 0 1 1 66.67 4 0 0 1 0 0 69.44 5 0 0 1 0 1 72.22 6 0 0 1 1 0 75.00 7 0 0 1 1 1 77.78 8 0 1 0 0 0 80.56 9 0 1 0 0 1 83.33 10 0 1 0 1 0 86.11 11 0 1 0 1 1 88.89 12 0 1 1 0 0 91.67 13 0 1 1 0 1 94.44 14 0 1 1 1 0 97.22 15 01 1 1 1 100.00 16 1 0 0 0 0 102.78 17 1 0 0 0 1 105.56 18 1 0 0 1 0 108.33 19 1 0 0 1 1 111.11 20 1 0 1 0 0 113.89 21 1 0 1 0 1 116.67 22 1 0 1 1 0 119.44 23 1 0 1 1 1 122.22 24 1 1 0 0 0 125.00 25 1 1 0 0 1 127.78 26 1 1 0 1 0 130.56 27 1 1 0 1 1 133.33 28 1 1 1 0 0 136.11 29 1 1 1 0 1 138.89 30 1 1 1 1 0 141.67 31 1 1 1 1 1 144.44 NOTE: Operation at other than the default entry is not guaranteed. These values are for margining purposes only. NS_SAS Margining Table

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 19 932SQ428 REV E 042312 Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) HCSL Output Buffer L1' R1b L2' R1a L4' R2a R2b Down Device REF_CLK Input Figure 3 L3' R3 R4 Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Cable Connected AC Coupled Application (figure 4) PCIe Device REF_CLK Input Figure 4 R5a L4'

3.3 Volts

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 20 932SQ428 REV E 042312 Package Outline and Package Dimensions (48-pin MLF)

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 21 932SQ428 REV E 042312 Marking Diagram Notes: 1. ‘L ” denotes RoHS compliant package. 2. ‘YYWW ’ is the date code. 3. ‘COO’ is the country of origin. 4. ‘LO T’ is the lot number.

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Revision History

Part / Order Number Shipping Packaging Package Temperature 932SQ428AKLF Tray 48-pin MLF 0 to +70° C 932SQ428AKLFT Tape and Reel 48-pin MLF 0 to +70° C Rev. Issue Date Who Description Page # A 4/15/2011 RDW Updated Idd, phase jitter, minor typo corrections; released to final B 7/26/2011 RDW Updated Power Down Functionality table to clarify functionality of single- ended outputs in power down. C 12/8/2011 RDW 1. U pdated Phase Jitter Table to correct typo in "Conditions" column for SAS. 2. M ark spec added. 8, 21 D 4/13/2012 AT Typo on pin 40 description. Pin type states OUT; should be IN 4 E 4/23/2012 RDW Updated Rp values on Output Terminations Table from 43.2 ohms to 42.2 or 43.2 ohms to be consistent with Intel. 5

© 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, IC S, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp pcclockhelp@idt.com Innovate with IDT and accelerate your future networks. Contact: www.IDT.com 932SQ428 PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS SYNTHESIZERS

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