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CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 932SQ426 IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 1 932SQ426 REV C 022916 General Description The 932SQ426 is a CK420BQ derivative supporting Separate Reference no Spread (SRnS) PCIe clocking architectures. It uses a 25MHz crystal for maximum performance and has 100MHz outputs tuned for non-spreading applications to provide the most open eye diagram on PCIe links. Recommended Application CK420BQ for SRnS applications Output Features
- 11 - HCSL 100MHz outputs for SRnS
- 4 - NS_SAS/SRC outputs
- 4 - CPU outputs
- 3 - SRC outputs
- 1 - HCSL DOT96 output
- 1 - 3.3V 48M output
- 5 - 3.3V PCI outputs
- 1 - 3.3V 14.318M output Features/Benefits
- Non-spread 100MHz outputs/ Supports SRnS PCIe architectures
- 64-pin TSSOP and VFQFPN packages; maximum space savings Key Specifications
- Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS < 50ps
- Phase jitter: PCIe Gen2 <3ps rms
- Phase jitter: PCIe Gen3 <1ps rms
- Phase jitter: QPI 9.6GB/s <0.2ps rms
- Phase jitter: NS-SAS <0.4ps rms using raw phase data
- Phase jitter: NS-SAS <1.3ps rms using Clk Jit Tool 1.6.4 Block Diagram Logic X1_25 X2 SRC(2:0) SMBDAT SMBCLK CKPWRGD#/PD IREF CPU(3:0) Low Drift non-SS PLL <500ps LTJ NS_SAS(1:0) NS_SRC(1:0) DOT96 48M PCI(4:0) 14.31818MHz Non-SS PLL REF14M Test_Mode Test_Sel Non-SS PLL
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 2 932SQ426 REV C 022916 Pin Configuration (TSSOP) 932SQ426 Functionality Power Group Pin Numbers 932SQ426 Power Down Functionality SMBCLK 1 64 SMBDAT GND14 2 63 VDDCPU AVDD14 3 62 CPU3T VDD14 4 61 CPU3C v REF14_3x/TEST_SEL 5 60 CPU2T GND14 6 59 CPU2C GNDXTAL 7 58 GNDCPU X1_25 8 57 VDDCPU X2_25 9 56 CPU1T V D D X T A L1 0 5 5C P U 1 C GNDPCI 11 54 CPU0T VDDPCI 12 53 CPU0C PCI4_2x 13 52 GNDNS PCI3_2x 14 51 AVDD_NS_SAS PCI2_2x 15 50 NS_SAS1T PCI1_2x 16 49 NS_SAS1C PCI0_2x 17 48 NS_SAS0T GNDPCI 18 47 NS_SAS0C VDDPCI 19 46 GNDNS V D D 4 82 0 4 5V D D N S 48M_2x 21 44 NS_SRC1T G N D 4 82 2 4 3N S _ S R C 1 C G N D 9 62 3 4 2N S _ S R C 0 T DOT96 T 24 41 NS_SRC0C DOT96C 25 40 IREF AVDD96 26 39 GNDSRC TEST_MODE 27 38 AVDD_SRC CKPWRGD#/PD 28 37 VDDSRC VDDSRC 29 36 SRC2T SRC0T 30 35 SRC2C SRC0C 31 34 SRC1T GNDSRC 32 33 SRC1C 64-TSSOP Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown 932SQ426 CPU, SRC, NS_SAS, NS_SRC PCI REF DOT96 USB 100 33.33 14.318 96.00 48.00 MHz VDD GND VDD GND 57 56 3 2 14MHz PLL Analog 58 60 4 6 REF14M Output and Logic 64 61 10 7 25MHz XTAL 2,9 1,8 12, 19 11,18 PCI Outputs and Logic 10 12 20 22 48MHz Output and Logic 16 13 26 23 96MHz PLL Analog, Output and Logic 19,27,28 22 29,37,38 32,39 SRC Outputs and Logic 35 36 45 46 Non-Spreading Differential Outputs & Logic 41 42 51 52 NS-SAS/SRC PLL Analog 47,53 48 57,63 58 CPU Outputs and Logic QFN
Description
CKPWRGD#/PD Differential Outputs Single- ended Outputs Single ended Outputs w/La tc h 1H I - Z Low Low
0 Running
- Hi-Z on the differential outputs will result in both True and Complement being low due to the termination 2. These outputs are Hi-Z after VDD is applied and before the first assertion of CKPWRGD#.
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 3 932SQ426 REV C 022916 Pin Descriptions (TSSOP) PIN # PIN NAME TYPE DESCRIPTION
1 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
2 GND14 PWR Ground pin for 14MHz output and logic.
3 AVDD14 PWR Analog power pin for 14MHz PLL
4 VDD14 PWR Power pin for 14MHz output and logic
5 vREF14_3x/TEST_SEL I/O 14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down. 6 GND14 PWR Ground pin for 14MHz output and logic. 7 GNDXTAL PWR Ground pin for Crystal Osc illator. 8 X1_25 IN Crystal input, Nominally 25.00MHz. 9 X2_25 OUT Crystal output, Nominally 25.00MHz. 10 VDDXTAL PWR 3.3V power for the crystal oscillator. 11 GNDPCI PWR Ground pin for PCI outputs and logic. 12 VDDPCI PWR 3.3V power for the PCI outputs and logic 13 PCI4_2x OUT 3.3V PCI clock output 14 PCI3_2x OUT 3.3V PCI clock output 15 PCI2_2x OUT 3.3V PCI clock output 16 PCI1_2x OUT 3.3V PCI clock output 17 PCI0_2x OUT 3.3V PCI clock output 18 GNDPCI PWR Ground pin for PCI outputs and logic. 19 VDDPCI PWR 3.3V power for the PCI outputs and logic 20 VDD48 PWR 3.3V power for the 48MHz output and logic 21 48M_2x OUT 3.3V 48MHz output 22 GND48 PWR Ground pin for 48MHz output and logic. 23 GND96 PWR Ground pin for DOT96 output and logic.
24 DOT96T OUT
True clock of differential 96MHz output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
25 DOT96C OUT
Complementary clock of differential 96MHz output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 26 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic 27 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
28 CKPWRGD#/PD IN
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clo cks and PLLs are stopped. 29 VDDSRC PWR 3.3V power for the SRC outputs and logic
30 SRC0T OUT
True clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
31 SRC0C OUT
Complementary clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 32 GNDSRC PWR Ground pin for SRC outputs and logic.
33 SRC1C OUT
Complementary clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
34 SRC1T OUT
True clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
35 SRC2C OUT
Complementary clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
36 SRC2T OUT
True clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 37 VDDSRC PWR 3.3V power for the SRC outputs and logic 38 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits 39 GNDSRC PWR Ground pin for SRC outputs and logic.
40 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value.
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 4 932SQ426 REV C 022916 Pin Descriptions (TSSOP, cont.) PIN # PIN NAME TYPE DESCRIPTION
41 NS_SRC0C OUT
Complementary clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
42 NS_SRC0T OUT
True clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
43 NS_SRC1C OUT
Complementary clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
44 NS_SRC1T OUT
True clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 45 VDDNS PWR 3.3V power for the Non-Spr eading differential outputs outputs and logic 46 GNDNS PWR Gr ound pin for non-spreading differential outputs and logic.
47 NS_SAS0C OUT
Complementary clock of differentia non-spreading SAS output. These are current m ode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
48 NS_SAS0T OUT
True clock of differential non-spreading SAS output. These are current m ode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
49 NS_SAS1C OUT
Complementary clock of differentia non-spreading SAS output. These are current m ode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
50 NS_SAS1T OUT
True clock of differential non-spreading SAS output. These are current m ode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 51 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits. 52 GNDNS PWR Gr ound pin for non-spreading differential outputs and logic.
53 CPU0C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
54 CPU0T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
55 CPU1C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
56 CPU1T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 57 VDDCPU PWR 3.3V power for the CPU outputs and logic 58 GNDCPU PWR Gr ound pin for CPU outputs and logic. CPU2C OUT Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
60 CPU2T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
61 CPU3C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
62 CPU3T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 63 VDDCPU PWR 3.3V power for the CPU outputs and logic
64 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 5 932SQ426 REV C 022916 Pin Configuration (VFQFPN) VDDXTAL X2_25 X1_25 GNDXTAL GND14 vREF14_3x/TEST_SEL VDD14 AVDD14 GND14 SMBCLK SMBDAT VDDCPU CPU3T CPU3C CPU2T CPU2C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDPCI 1 48 GNDCPU VDDPCI 2 47 VDDCPU PCI4_2x 34 6 C P U 1 T PCI3_2x 44 5 C P U 1 C PCI2_2x 54 4 C P U 0 T PCI1_2x 64 3 C P U 0 C PCI0_2x 7 42 GNDNS GNDPCI 8 41 AVDD_NS_SAS VDDPCI 9 40 NS_SAS1T VDD48 10 39 NS_SAS1C 48M_2x 11 38 NS_SAS0T GND48 12 37 NS_SAS0C GND96 13 36 GNDNS DOT96T 14 35 VDDNS DOT96C 15 34 NS_SRC1T AVDD96 16 33 NS_SRC1C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32TEST_MODE CKPWRGD#/PD VDDSRC SRC0T SRC0C GNDSRC SRC1C SRC1T SRC2C SRC2T VDDSRC AVDD_SRC GNDSRC IREF NS_SRC0C NS_SRC0T Note: Pins with ^ prefix hav e internal 120K pullup Pins with v prefix have internal 120K pulldowm 932SQ426 64-pin VFQFPN
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 6 932SQ426 REV C 022916 Pin Descriptions (VFQFPN) PIN # PIN NAME TYPE DESCRIPTION 1G N D P C I 932S Q426 Ground pin for PCI outputs and logic.
2 VDDPCI PWR
3 PCI4_2x OUT 3.3V PCI clock output 4 PCI3_2x OUT 3.3V PCI clock output 5 PCI2_2x OUT 3.3V PCI clock output 6 PCI1_2x OUT 3.3V PCI clock output 7 PCI0_2x OUT 3.3V PCI clock output 8 GNDPCI PWR Ground pin for PCI outputs and lo gic. 9 VDDPCI PWR 3.3V power for the PCI outputs and lo gic 10 VDD48 PWR 3.3V power for the 48MHz output and logic 11 48M_2x OUT 3.3V 48MHz output
12 GND48 PWR Ground pin for 48MHz output and lo
gic. 13 GND96 PWR Ground pin for DOT96 output and logic.
14 DOT96T OUT
True clock of differential 96MHz output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
15 DOT96C OUT
Complementary clock of differential 96MHz output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 16 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and lo gic 17 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
18 CKPWRGD#/PD IN
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 19 VDDSRC PWR 3.3V power for the SRC outputs and logic
20 SRC0T OUT
True clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
21 SRC0C OUT
Complementary clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 22 GNDSRC PWR Ground pin for SRC outputs and lo gic.
23 SRC1C OUT
Complementary clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
24 SRC1T OUT
True clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
25 SRC2C OUT
Complementary clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
26 SRC2T OUT
True clock of differential SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 27 VDDSRC PWR 3.3V power for the SRC outputs and lo gic 28 AVDD_SRC PWR 3.3V power for the SRC PLL analo g circuits 29 GNDSRC PWR Ground pin for SRC outputs and logic.
30 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value.
31 NS_SRC0C OUT
Complementary clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
32 NS_SRC0T OUT
True clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 7 932SQ426 REV C 022916 Pin Descriptions (VFQFPN, cont.) PIN # PIN NAME TYPE DESCRIPTION
33 NS_SRC1C OUT
Complementary clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
34 NS_SRC1T OUT
True clock of differential non-spreading SRC output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 35 VDDNS PWR 3.3V power for the Non-Spreadin g differential outputs outputs and lo gic 36 GNDNS PWR Ground pin for non-spreading differential outputs and logic.
37 NS_SAS0C OUT
Complementary clock of differentia non-spreading SAS output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
38 NS_SAS0T OUT
True clock of differential non-spreading SAS output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
39 NS_SAS1C OUT
Complementary clock of differentia non-spreading SAS output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
40 NS_SAS1T OUT
True clock of differential non-spreading SAS output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 41 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits. 42 GNDNS PWR Ground pin for non-spreadin g differential outputs and logic.
43 CPU0C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
44 CPU0T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
45 CPU1C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
46 CPU1T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 47 VDDCPU PWR 3.3V power for the CPU outputs and lo gic 48 GNDCPU PWR Ground pin for CPU outputs and logic.
49 CPU2C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
50 CPU2T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
51 CPU3C OUT
Complementary clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values.
52 CPU3T OUT
True clock of differential CPU output. These are current mode outputs and external series resistors and shunt resistors are required for termination. See Test Loads and Recommended Terminations for specific values. 53 VDDCPU PWR 3.3V power for the CPU outputs and logic
54 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
56 GND14 PWR Ground pin for 14MHz output and logic.
57 AVDD14 PWR Analo g power pin for 14MHz PLL
58 VDD14 PWR Power pin for 14MHz output and logic
59 vREF14_3x/TEST_SE L I/O 14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down. 60 GND14 PWR Ground pin for 14MHz output and logic. 61 GNDXTAL PWR Ground pin for Crystal Oscillator. 62 X1_25 IN Crystal input, Nominally 25.00MHz. 63 X2_25 OUT Crystal output, Nominally 25.00MHz. 64 VDDXTAL PWR 3.3V power for the crystal oscillator.
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 8 932SQ426 REV C 022916 Test Loads and Recommended Terminations Differential Zo Rp Rp HSCL Output Buffer 932SQ426 Differential Test Loads Rs Rs 2pF 2pF Zo 5pF Zo 5pF Zo 5pF Zo 5pF Zo 5pF Zo 5pFRs Rs Rs Rs Rs Rs Differential Output Termination Table DIF Zo ( Ω)I r e f ( Ω)R s ( Ω)R p ( Ω) 100 475 33 50 85 412 27 43.2 Single-ended Output Termination Table Output Loads Zo = 50Ω Zo =6 0Ω PCI/USB 1 36 43 PCI/USB 2 22 33 REF 1 39 47 REF 2 27 36 REF 3 10 20 Rs Value (for each load)
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 9 932SQ426 REV C 022916 Electrical Characteristics - Absolute Maximum Ratings Electrical Characteristics - Current Consumption PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES .3V Core Supply Voltag VDDA 932SQ426AKLF 4.6 V 1,2 3V Logic Supply Volta g VDD 4.6 V 1,2 Input Low Voltage V IL GND-0.5 V 1 Input High Voltage V IH Except for SMBus interface V DD+0.5V V 1 Input High Voltage V IHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current IDD3.3OP All outputs active @100MHz, C L = Full load; 370 400 mA Powerdown Current IDD3.3PDZ All differential pairs tri-stated 17 20 mA 1Guaranteed by design and characterization, not 100% tested in production.
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 10 932SQ426 REV C 022916 TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate dV/dt Scope avera ging on 1 2.3 4 V/ns 1, 2, 3 Slew rate matching ∆dV/dt Slew rate matching, Scope averaging on 10 20 % 1, 2, 4 Rise/Fall Time Matching ∆Trf Rise/fall matching, Scope averaging off 17 125 ps 1, 8, 9 Voltage High VHigh 660 716 850 Voltage Low VLow -150 20 150 Max Voltage Vmax 757 1150 1, 7 Min Voltage Vmin -300 -9 1, 7 Vswing Vswing Scope averaging off 300 1393 mV 1, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 338 550 mV 1, 5 Crossing Voltage (var) ∆-Vcross Scope averaging off 32 140 mV 1, 6
2 Measured from differential waveform
7 Includes overshoot and undershoot.
8 Measured from single-ended waveform
9 Measured with scope averaging off, using statistics function. Variation is difference between min and max. 1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR R). For RR =412Ω (1%), IREF = 2.67mA. IOH = 6 x I REF and VOH = 0.7V @ Z O= 85Ω differential impedance. 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# fa lling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cros s absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolut e. Measurement on single ended signal using absolute value. (Scope averaging off) mV Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) mV
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 11 932SQ426 REV C 022916 Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Ambient Operating Temperature TCOM Commmercial range 0 25 70 °C 1 Input High Voltage V IH Single-ended inputs, except SMBus, low threshold and tri-level inputs 2.2 2.4 V DD + 0.3 V Input Low Voltage V IL Single-ended inputs, except SMBus, low threshold and tri-level inputs GND - 0.3 0.4 0.8 V IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA IINP Single-ended inputs. VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA Low Threshold Input- High Voltage VIH_FS 3.3 V +/-5% 0.7 V DD + 0.3 V Low Threshold Input- Low Voltage VIL_FS 3.3 V +/-5% V SS - 0.3 0.35 V Input Frequency F i 25.00 MHz 2 Pin Inductance L pin 7n H 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 5 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization T STAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1.3 1.8 ms 2 Tdrive_PD# t DRVPD Differential output enable after PD# de-assertion 200 300 us 1,3 Tfall t F Fall time of control inputs 5 ns 1,2 Trise t R Rise time of control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB 0.8 V SMBus Input High Voltage VIHSMB 2.1 V DDSMB V1 SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V SMBus Sink Current I PULLUP @ VOL 4m A Nominal Bus Voltage V DDSMB 3V to 5V +/- 10% 2.7 5.5 V SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1Guaranteed by design and characterization, not 100% tested in production. 2Control input must be monotonic from 20% to 80% of input swing. 3Time from deassertion until outputs are >200 mV Input Current Capacitance
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 12 932SQ426 REV C 022916 Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle t DC Measured differentially, PLL Mode 45 52 55 % 1 Skew, Output to Output tsk3SRC Across all SRC, NS-SAS outputs, V T = 50% 12 50 ps 1 Skew, Output to Output tsk3CPU Across all CPU outputs, V T = 50% 35 50 ps 1 CPU, SRC, NS_SAS outputs @100M 34 50 ps 1,3 DOT96 output 75 250 ps 1,3 1Guaranteed by design and characterization, not 100% tested in production.
3 Measured from differential waveform
tjcyc-cycJitter, Cycle to cycle TA = 0 - 70°C; Supply Voltage V DD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes tjphPCIeG1 PCIe Gen 1 16 86 ps (p-p) 1,2,3,6 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.37 3 ps (rms) 1,2,6 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 1.45 3.1 ps (rms) 1,2,6 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.35 1 ps (rms) 1,2,4,6 QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.29 0.5 ps (rms) 1,5,6 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.15 0.3 ps (rms) 1,5,6 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.13 0.2 ps (rms) 1,5,6 tjphSAS12G SAS12G (Filtered REFCLK Jitter 20KHz to 20MHz.) 0.30 0.4 ps (rms) 1,7,8 tjphSAS12G SAS 12G 0.54 1.3 ps (rms) 1,5,8 1 Guaranteed by design and characterization, not 100% tested in production.
6 Applies to CPU, SRC and NS_SAS outputs
7 Intel calculation from raw phase noise data
8 Applies to NS_SAS and NS_SRC outputs only. 4 Subject to final radification by PCI SIG. 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. Phase Jitter tjphPCIeG2 tjphQPI_SMI 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 13 932SQ426 REV C 022916 Electrical Characteristics - PCI Electrical Characteristics - 48MHz TA = 0 - 70°C; Supply Voltage V DD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V Output Low Voltage V OL IOL = 1 mA 0.55 V Clock High Time T HIGH 1.5V 12 ns 1 Clock Low Time T LOW 1.5V 12 ns 1 Edge Rate t slewr/f Rising/Falling edge rate 1 1.7 4 V/ns 1,2 Duty Cycle d t1 VT = 1.5 V 45 51.3 55 % 1 Group Skew t skew VT = 1.5 V 279 500 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 96 500 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V TA = 0 - 70°C; Supply Voltage V DD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD*(0.5) 20 60 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V Output Low Voltage V OL IOL = 1 mA 0.55 V Clock High Time T HIGH 1.5V 8.094 10.036 ns 1 Clock Low Time T LOW 1.5V 7.694 9.836 ns 1 Edge Rate t slewr/f_USB Rising/Falling edge rate 1 1.8 2 V/ns 1,2 Duty Cycle d t1 VT = 1.5 V 45 51 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 122 350 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 14 932SQ426 REV C 022916 Electrical Characteristics - REF Clock AC Tolerances Clock Periods – Outputs without Spread Spectrum TA = 0 - 70°C; Supply Voltage V DD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Output Impedance R DSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V Output Low Voltage V OL IOL = 1 mA 0.55 V Clock High Time T HIGH 1.5V 27.5 ns 1 Clock Low Time T LOW 1.5V 27.5 ns 1 Edge Rate t slewr/f Rising/Falling edge rate 1 1.5 4 V/ns 1,2 Duty Cycle d t1 VT = 1.5 V 45 50.5 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 89 1000 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V CPU SRC, NS_SAS, NS_SRC PCI DOT96 48MHz REF 100 100 100 100 100 100 ppm 50 50 500 250 350 1000 ps PPM tolerance Cycle to Cycle Jitter 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max SRC, NS_SAS, NS_SRC 1,2 1Guaranteed by design and characterization, not 100% tested in production. SSC ON 2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz. Center Freq. MHz Notes Measurement Window Units
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 15 932SQ426 REV C 022916 General SMBus Serial Interface Information How to Write
- Controller (host) sends a start bit
- Controller (host) sends the write address
- IDT clock will acknowledge
- Controller (host) sends the beginning byte location = N
- IDT clock will acknowledge
- Controller (host) sends the byte count = X
- IDT clock will acknowledge
- Controller (host) starts sending Byte N through Byte N+X-1
- IDT clock will acknowledge each byte one at a time
- Controller (host) sends a Stop bit SMBus write address = D2 hex SMBus read address = D3 hex How to Read
- Controller (host) will send a start bit
- Controller (host) sends the write address
- IDT clock will acknowledge
- Controller (host) sends the beginning byte location = N
- IDT clock will acknowledge
- Controller (host) will send a separate start bit
- Controller (host) sends the read address
- IDT clock will acknowledge
- IDT clock will send the data byte count = X
- IDT clock sends Byte N+X-1
- IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
- Controller (host) will need to acknowledge each byte
- Controller (host) will send a not acknowledge bit
- Controller (host) will send a stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK Ps t o P b i t Index Block Read Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge Ps t o P b i t
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 16 932SQ426 REV C 022916 SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 DOT96 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 6 NS_SAS1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 NS_SAS0 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 4 NS_SRC1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 NS_SRC0 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 2 SRC2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 SRC1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 0 SRC0 Enable Output Enable RW Disable-Hi-Z Enable 1 SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 REF14_3x Enable Output Enable RW Disable-Low Enable 1 Bit 6 0 Bit 5 0 Bit 4 CPU3 Output Enable RW Disable-Hi-Z Enable 1 Bit 3 CPU2 Output Enable RW Disable-Hi-Z Enable 1 Bit 2 CPU1 Output Enable RW Disable-Hi-Z Enable 1 Bit 1 CPU0 Output Enable RW Disable-Hi-Z Enable 1 Bit 0 0 SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 PCI4 Enable Output Enable RW Disable-Low Enable 1 Bit 4 PCI3 Enable Output Enable RW Disable-Low Enable 1 Bit 3 PCI2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 PCI1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 PCI0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 48MHz Enable Output Enable RW Disable-Low Enable 1 SMBus Table: Reserved Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 SMBus Table: Reserved Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Byte 2 RESERVED RESERVED RESERVED Byte 0 Byte 1 Byte 3 Byte 4
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 17 932SQ426 REV C 022916 SMBus Table: Reserved Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 SMBus Table: Test Mode Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 Test Mode Test Mode Type RW Hi-Z REF/N 0 Bit 6 Test Select Select Test Mode RW Disable Enable 0 Bit 5 0 Bit 4 1 Bit 3 1 Bit 2 0 Bit 1 0 Bit 0 0 SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Type 0 1 Default Bit 7 RID3 R 0 Bit 6 RID2 R 0 Bit 5 RID1 R 0 Bit 4 RID0 R 0 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 SMBus Table: Byte Count Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 0 Bit 1 BC1 RW 1 Bit 0 BC0 RW 0 SMBus Table: Device ID Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 DID7 R -- 0 Bit 6 DID6 R -- 0 Bit 5 DID5 R -- 0 Bit 4 DID4 R -- 1 Bit 3 DID3 R -- 1 Bit 2 DID2 R -- 0 Bit 1 DID1 R -- 1 Bit 0 DID0 R -- 0 RESERVED 0001 for ICS/IDT RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0000 for A rev RESERVED VENDOR ID REVISION ID Byte 8 Byte 7 Byte 6 Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is A bytes. (0 to 9 Device ID (1A hex) RESERVED RESERVED RESERVED Byte 5 Byte 9
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 19 932SQ426 REV C 022916 Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) HCSL Output Buffer L1' R1b L2' R1a L4' R2a R2b Down Device REF_CLK Input Figure 3 L3' R3 R4 Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Cable Connected AC Coupled Application (figure 4) PCIe Device REF_CLK Input Figure 4 R5a L4'
3.3 Volts
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 20 932SQ426 REV C 022916 Test Clarification Table Marking Diagrams Notes: 1. “LOT” denotes lot number. 2. “YYWW” is the date code. 3. “COO” denotes country of origin. 4. “L” or “LF” denotes RoHS compliant package. Comments TEST_SEL HW PIN 932SQ426A KLF ENTRY BIT B6b6 HI-Z B6b7 OUTPUT 0X0 X N O R M A L 10X 0 H I - Z 10X 1 R E F / N 11X 0 R E F / N 11X 1 R E F / N 0X1 0 H I - Z 0X1 1 R E F / N B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) HW SW Power-up w/ TEST_SEL = 1 (>2.0V) to enter test mode. Cycle power to disable test mode. If TEST_SEL HW pin is 0 during power-up, test mode can be selected through B6b6. If test mode is selected by B6b6, then B6b7 is used to select HI-Z or REF/N. TEST_Mode pin is not used. Cycle power to disable test mode. LOT YYWW 932SQ426AGLF ICS ICS 932SQ426AKL LOT COO YYWW
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 21 932SQ426 REV C 022916
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 22 932SQ426 REV C 022916
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 23 932SQ426 REV C 022916 Package Outline and Package Dimensions (64-pin TSSOP)
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Shipping Pacakging Package Temperature 932SQ426AGLF Tubes 64-pin TSSOP 0 to +70° C 932SQ426AGLFT Tape and Reel 64-pin TSSOP 0 to +70° C 932SQ426AKLF Tray 64-pin VFQFPN 0 to +70° C 932SQ426AKLFT Tape and Reel 64-pin VFQFPN 0 to +70° C
CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING IDT® CK420BQ DERIVATIVE SUPPORTING SRNS PCIE CLOCKING 24 932SQ426 REV C 022916
Revision History
Rev. Issue Date Who Description Page # A 10/14/2011 RDW 1. Updated Electrical Tables with typical values 2. Updated Pin Descriptions on Differential outputs to refer to "Test Loads and Recommended Termiations" table for Rs and Rp values. 3. Updated Byte 5 to Reserved 4. Updated Byte 6 Default value to 18hex from 00hex 5. Removed Non-Spread Output Margining Table on page 15 6. Add Mark Spec 7. Move to Final Various B 7/8/2015 RDW 1.Updated front page text 2. Added 64-QFN power groupings to power grouping table. 3. Added 64-QFN pin out, pin description 4. Updated marking info for 64-QFN 5. Added 64-QFN ordering info 5,17,18 C 2/26/2016 RDW 1.Minor grammatical corrections to electrical tables 9-14
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