932SQ420D

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PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 932SQ420D IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 1 932SQ420D REV J 010715 General Description The 932SQ420D is a main clock synthesizer for Romley-generation Intel based server platforms. The 932SQ420D is driven with a 25 MHz crystal for maximum performance. It generates CPU outputs of 100 or 133.33 MHz. Recommended Application CK420BQ Output Features

• 4 - HCSL CPU outputs
• 4 - HCSL Non-Spread SAS/SRC outputs
• 3 - HCSL SRC outputs
• 1 - HCSL DOT96 output
• 1 - 3.3V 48M output
• 5 - 3.3V PCI outputs
• 1- 3.3V REF output Features/Benefits
• 0.5% down spread capable on CPU/SRC/PCI outputs/Lower EMI
• 64-pin TSSOP and MLF packages/Space Savings Key Specifications
• Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS < 50ps.
• Phase jitter: PCIe Gen2 < 3ps rms, Gen3 < 1ps rms
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
• Phase jitter: NS-SAS < 0.4ps rms using raw phase data
• Phase jitter: NS-SAS < 1.3ps rms using Clk Jit Tool 1.6.3 Block Diagram Logic X1_25 X2 SRC(2:0) SMBDAT SMBCLK CKPWRGD#/PD IREF 100M_133M# CPU_SRC_PCI PLL (SS) CPU(3:0) Low Drift non-SS PLL <500ps LTJ NS_SAS(1:0) NS_SRC(1:0) DOT96 /2 48M PCI(4:0) 14.31818MHz Non-SS PLL REF14M Test_Mode Test_Sel Non-SS PLL

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 2 932SQ420D REV J 010715 Pin Configuration - 64TSSOP Spread Spectrum Control Power Group Pin Numbers 932SQ420 Power Down Functionality SMBCLK 1 64 SMBDAT GND14 2 63 VDDCPU AVDD14 3 62 CPU3T VDD14 4 61 CPU3C v REF14_3x/TEST_SEL 5 60 CPU2T GND14 6 59 CPU2C GNDXTAL 7 58 GNDCPU X1_25 8 57 VDDCPU X2_25 9 56 CPU1T V D D X T A L1 0 5 5C P U 1 C GNDPCI 11 54 CPU0T VDDPCI 12 53 CPU0C PCI4_2x 13 52 GNDNS PCI3_2x 14 51 AVDD_NS_SAS PCI2_2x 15 50 NS_SAS1T PCI1_2x 16 49 NS_SAS1C PCI0_2x 17 48 NS_SAS0T GNDPCI 18 47 NS_SAS0C VDDPCI 19 46 GNDNS V D D 4 82 0 4 5V D D N S 48M_2x/100M_133M# 21 44 NS_SRC1T G N D 4 82 2 4 3N S _ S R C 1 C G N D 9 62 3 4 2N S _ S R C 0 T DOT96T 24 41 NS_SRC0C DOT96C 25 40 IREF AVDD96 26 39 GNDSRC TEST_MODE 27 38 AVDD_SRC CKPWRGD#/PD 28 37 VDDSRC VDDSRC 29 36 SRC2T SRC0T 30 35 SRC2C SRC0C 31 34 SRC1T GNDSRC 32 33 SRC1C 64-TSSOP Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown 932SQ420 SS_Enable (B1b0) CPU, SRC & PCI 0O F F 1O N VDD GND VDD GND 57 56 3 2 14MHz PLL Analog 58 60 4 6 REF14M Output and Logic 64 61 10 7 25MHz XTAL 2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic 10 12 20 22 48MHz Output and Logic 16 13 26 23 96MHz PLL Analog, Output and Logic 19, 27 22 29, 37 32 SRC Outputs and Logic 28 29 38 39 SRC PLL Analog 35 36 45 46 Non-Spreading Differential Outputs & Logic 41 42 51 52 NS-SAS/SRC PLL Analog 47, 53 48 57,63 58 CPU Outputs and Logic MLF DescriptionTSSOP CKPWRGD#/PD Differential Outputs Single-ended Outputs Single ended Outputs w/Latch 1H I - Z Low Low 2. These outputs are Hi-Z after VDD is applied and before the first assertion of CKPWRGD#. Running 1. Hi-Z on the differential outputs will result in both True and Complement being low due to the termination network

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 3 932SQ420D REV J 010715 Pin Descriptions - 64 TSSOP PIN # PIN NAME TYPE DESCRIPTION

1 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

2 GND14 PWR Ground pin for 14MHz output and logic.

3 AVDD14 PWR Analog power pin for 14MHz PLL

4 VDD14 PWR Power pin for 14MHz output and logic

5 vREF14_3x/TEST_SEL I/O 14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down. 6 GND14 PWR Ground pin for 14MHz output and logic. 7 GNDXTAL PWR Ground pin for Crystal Oscillator. 8 X1_25 IN Crystal input, Nominally 25.00MHz. 9 X2_25 OUT Crystal output, Nominally 25.00MHz. 10 VDDXTAL PWR 3.3V power for the crystal oscillator. 11 GNDPCI PWR Ground pin for PCI outputs and logic. 12 VDDPCI PWR 3.3V power for the PCI outputs and logic 13 PCI4_2x OUT 3.3V PCI clock output 14 PCI3_2x OUT 3.3V PCI clock output 15 PCI2_2x OUT 3.3V PCI clock output 16 PCI1_2x OUT 3.3V PCI clock output 17 PCI0_2x OUT 3.3V PCI clock output 18 GNDPCI PWR Ground pin for PCI outputs and logic. 19 VDDPCI PWR 3.3V power for the PCI out puts and logic 20 VDD48 PWR 3.3V power for the 48MHz out put and logic 21 ^48M_2x/100M_133M# I/O 3.3V 48MHz output/ 3.3V tolerant CPU frequency select latched input pin. See VilFS and VihFS values for thresholds. This pin has a weak (~120Kom) internal pull up. 1 = 100MHz, 0 = 133MHz o perating fr equency 22 GND48 PWR Ground pin for 48MHz output and logic. 23 GND96 PWR Ground pin for DOT96 out put and logic. 24 DOT96T OUT True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 25 DOT96C OUT Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 26 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz out put and logic 27 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.

28 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 29 VDDSRC PWR 3.3V power for the SRC outputs and logic 30 SRC0T OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 31 SRC0C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 32 GNDSRC PWR Ground pin for SRC outputs and logic. 33 SRC1C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 34 SRC1T OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 35 SRC2C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 36 SRC2T OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 37 VDDSRC PWR 3.3V power for the SRC outputs and logic 38 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits 39 GNDSRC PWR Ground pin for SRC outputs and logic.

40 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 4 932SQ420D REV J 010715 Pin Descriptions - 64 TSSOP(cont.) 41 NS_SRC0C OUT Complementary clock of differential non-spreading SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 42 NS_SRC0T OUT True clock of differential non-spreading SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 43 NS_SRC1C OUT Complementary clock of differential non-spreading SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 44 NS_SRC1T OUT True clock of differential non-spreading SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 45 VDDNS PWR 3.3V power for the Non-Spreading differential outputs outputs and logic 46 GNDNS PWR Ground pin for non-spreading differential outputs and logic. 47 NS_SAS0C OUT Complementary clock of differentia non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 48 NS_SAS0T OUT True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 49 NS_SAS1C OUT Complementary clock of differential non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 50 NS_SAS1T OUT True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 51 AVDD_NS_SAS PWR 3.3V power for the non-s preading SAS/SRC PLL analo g circuits. 52 GNDNS PWR Ground pin for non-spreading differ ential outputs and logic. 53 CPU0C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 54 CPU0T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 55 CPU1C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 56 CPU1T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 57 VDDCPU PWR 3.3V power for the CPU out puts and logic 58 GNDCPU PWR Ground pin for CPU outputs and logic. 59 CPU2C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 60 CPU2T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 61 CPU3C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 62 CPU3T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 63 VDDCPU PWR 3.3V power for the CPU outputs and logic

64 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 5 932SQ420D REV J 010715 Pin Configuration - 64 MLF VDDXTAL X2_25 X1_25 GN DXTAL GND14 vREF14_3x/TEST_SEL VDD14 AVDD14 GND14 SMBCLK SMBDAT VDDCPU CPU3T CPU3C CPU2T CPU2C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDPCI 1 48 GNDCPU VDDPCI 2 47 VDDCPU PCI4_2x 34 6 CPU1T PCI3_2x 4 45 CPU1C PCI2_2x 54 4 C P U 0 T PCI1_2x 6 43 CPU0C PCI0_2x 74 2 G N D N S GNDPCI 8 41 AVDD_NS_SAS VDDPCI 9 40 NS_SAS1T VDD48 10 39 NS_SAS1C ^48M_2x/100M_133M# 11 38 NS_SAS0T GN D4812 37 NS_SAS0C GN D9613 36 GNDNS DOT96T 14 35 VDDNS DOT96C 15 34 NS_SRC1T AVDD96 16 33 NS_SRC1C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TEST_MODE CKPWRGD#/PD VDDSRC SRC0T SRC0C GNDSRC SRC1C SRC1T SRC2C SRC2T VDDSRC AVDD_SRC GNDSRC IREF NS_SRC0C NS_SRC0T Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm 932SQ420

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 6 932SQ420D REV J 010715 Pin Descriptions - 64 MLF PIN # PIN NAME TYPE DESCRIPTION 1 GNDPCI PWR Ground pin for PCI outputs and logic. 2 VDDPCI PWR 3.3V power for the PCI outputs and logic 3 PCI4_2x OUT 3.3V PCI clock output 4 PCI3_2x OUT 3.3V PCI clock output 5 PCI2_2x OUT 3.3V PCI clock output 6 PCI1_2x OUT 3.3V PCI clock output 7 PCI0_2x OUT 3.3V PCI clock output 8 GNDPCI PWR Ground pin for PCI outputs and logic. 9 VDDPCI PWR 3.3V power for the PCI outputs and logic 10 VDD48 PWR 3.3V power for the 48MHz output and logic 11 ^48M_2x/100M_133M# I/O 3.3V 48MHz output/ 3.3V tolerant CPU frequency select latched input pin. See VilFS and VihFS values for thresholds. This pin has a weak (~120Kom) internal pull up. 1 = 100MHz, 0 = 133MHz operating frequency 12 GND48 PWR Ground pin for 48MHz output and logic. 13 GND96 PWR Ground pin for DOT96 out put and logic. 14 DOT96T OUT True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 15 DOT96C OUT Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 16 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz out put and logic 17 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.

18 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 19 VDDSRC PWR 3.3V power for the SRC outputs and logic 20 SRC0T OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 21 SRC0C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 22 GNDSRC PWR Ground pin for SRC outputs and logic. 23 SRC1C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 24 SRC1T OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 25 SRC2C OUT Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 26 SRC2T OUT True clock of differential SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 27 VDDSRC PWR 3.3V power for the SRC outputs and logic 28 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits 29 GNDSRC PWR Ground pin for SRC outputs and logic.

30 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 31 NS_SRC0C OUT Complementary clock of differential non-spreading SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 32 NS_SRC0T OUT True clock of differential non-spreading SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 33 NS_SRC1C OUT Complementary clock of differential non-spreading SRC output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 34 NS_SRC1T OUT True clock of differential non-spreading SRC output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 7 932SQ420D REV J 010715 Pin Descriptions - 64 MLF (cont). 35 VDDNS PWR 3.3V power for the Non-Spreading differential outputs outputs and logic 36 GNDNS PWR Ground pin for non-spreading differential outputs and logic. 37 NS_SAS0C OUT Complementary clock of differentia non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 38 NS_SAS0T OUT True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 39 NS_SAS1C OUT Complementary clock of differential non-spreading SAS output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 40 NS_SAS1T OUT True clock of differential non-spreading SAS output. These are current mode outputs. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 41 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits. 42 GNDNS PWR Ground pin for non-spreading differential outputs and logic. 43 CPU0C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 44 CPU0T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 45 CPU1C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination. 46 CPU1T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 47 VDDCPU PWR 3.3V power for the CPU out puts and logic 48 GNDCPU PWR Ground pin for CPU outputs and logic. 49 CPU2C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 50 CPU2T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 51 CPU3C OUT Complementary clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 52 CPU3T OUT True clock of differential CPU output. These are current mode outputs and external 33 ohm series resistors and 49.9 ohm shunt resistors are re quired for termination. 53 VDDCPU PWR 3.3V power for the CPU out puts and logic

54 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant

55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

56 GND14 PWR Ground pin for 14MHz output and logic.

57 AVDD14 PWR Analog power pin for 14MHz PLL

58 VDD14 PWR Power pin for 14MHz output and logic

59 vREF14_3x/TEST_SEL I/O 14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm ) internal pull down. 60 GND14 PWR Ground pin for 14MHz output and logic. 61 GNDXTAL PWR Ground pin for Crystal Oscillator. 62 X1_25 IN Crystal input, Nominally 25.00MHz. 63 X2_25 OUT Crystal output, Nominally 25.00MHz. 64 VDDXTAL PWR 3.3V power for the crystal oscillator.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 8 932SQ420D REV J 010715 Test Loads and Recommended Terminations Single-ended Output Termination Table Output Loads Zo = 50Ω Zo =6 0Ω PCI/USB 1 36 43 PCI/USB 2 22 33 REF 1 39 47 REF 2 27 36 REF 3 10 20 Rs Value (for each load) Differential Zo Rp Rp HCSL Output Buffer 932SQ420 Differential Test Loads Rs Rs 2pF 2pF Differential Output Termination Table DIF Zo (Ω)I r e f ( Ω)R s ( Ω)R p ( Ω) 100 475 33 50 85 412 27 42.3 or 43.2

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 9 932SQ420D REV J 010715 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V 1,2 3.3V Logic Supply Voltage VDD 4.6 V 1,2 Input Low Voltage V IL GND-0.5 V 1 Input High Voltage V IH Except for SMBus interface V DD+0.5V V 1 Input High Voltage V IHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Case Temperature Tc 110 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. TA = TCO M; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate dV/dt Scope averaging on 1 2.4 4 V/ns 1, 2, 3 Slew rate matching ∆dV/dt Slew rate matching, Scope averaging on 92 0 % 1, 2, 4 Rise/Fall Time Matching ∆Trf Rise/fall matching, Scope av er aging off 125 ps 1, 8, 9 Voltage High VHigh 660 772 850 1 Voltage Low VLow -150 9 150 1 Max Voltage Vmax 810 1150 1, 7 Min Voltage Vmin -300 -17 1, 7 Vswing Vswing Scope averaging off 300 1446 mV 1, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 351 550 mV 1, 5 Crossing Voltage (var) ∆-Vcross Scope averaging off 24 140 mV 1, 6 Measured from differential waveform Includes overshoot and undershoot. Measured from single-ended waveform Measured with scope averaging off, using statistics function. Variation is difference between min and max. Measurement on single ended signal using absolute value. mV Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) mV Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR R). For R R = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance). Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window arou nd differential 0V. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential risi ng edge (i.e. Clock rising and Clock# falling). The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cros s absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolut e.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 10 932SQ420D REV J 010715 Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Ambient Operating Temper ature TCOM Commmercial range 0 70 °C 1 Input High Voltage VIH Single-ended inputs, except SMBus, low threshold and tri- level inputs 2 VDD + 0.3 V1 Input Low Voltage VIL Single-ended inputs, except SMBus, low threshold and tri- level inputs GND - 0.3 0.8 V 1 IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1 IINP Single-ended inputs. VIN = 0 V; Inputs with internal pull - up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 Low Threshold Input- High Voltage VIH _FS 3.3 V +/-5% 0.7 V DD + 0.3 V 1 Low Threshold Input- Low Voltage VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 Input Frequency Fi 25.00 MHz 2 Pin Inductance L p in 7n H 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 5 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de- assertion of PD# to 1st clock 1.8 ms 1,2 SS Modulation Frequency fMO DI N Allowable Fr equency (Triangular Modulation ) 30 31.500 33 kHz 1 Tdrive_PD# tDR VPD Differential output enable after PD# de-assertion 200.000 300 us 1,3 Tfall t F Fall time of control inputs 5 ns 1,2 Trise tR Rise time of control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB 0.8 V 1 SMBus Input High Voltage VIHSMB 2.1 VDD SMB V1 SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V 1 SMBus Sink Current I PULLUP @ VOL 4m A 1 Nominal Bus Voltage VDDSM B 3V to 5V +/- 10% 2.7 5.5 V 1 SCLK/SDATA Rise Time tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are >200 mV Input Current Capacitance

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 11 932SQ420D REV J 010715 Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle t DC Measured differentially, PLL Mode 45 50.1 55 % 1 Skew, Output to Output tsk 3SRC Across all SRC outputs, VT = 50% 13.5 50 ps 1 Skew, Output to Output tsk 3CPU Across all CPU outputs, VT = 50% 43 50 ps 1 CPU, SRC, NS_SAS out puts 35 50 ps1 , 3 DOT96 output 75 250 ps1 , 3 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform tj cyc -cy cJitter, Cycle to cycle TA = 0 - 70°C; Supply Voltage V DD/VDDA = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes tjphPCIeG1 PCIe Gen 1 28 86 ps (p-p) 1,2,3,6 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.9 3 ps (rms) 1,2,6 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 1.7 3.1 ps (rms) 1,2,6 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.4 1 ps (rms) 1,2,4,6 QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.15 0.5 ps (rms) 1,5,7 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.13 0.3 ps (rms) 1,5,7 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.11 0.2 ps (rms) 1,5,7 tjphSAS12G SAS12G (Filtered REFCLK Jitter 20KHz to 20MHz.) 0.34 0.4 ps (rms) 1,8,9 tjphSAS12G SAS 12G 0.70 1.3 ps (rms) 1,5,8 1 Guaranteed by design and characterization, not 100% tested in production.

6 Applied to SRC outputs

7 Applies to CPU outputs

8 Applies to NS_SAS, NS_SRC outputs, Spr ead Off

9 Intel calculation from raw phase noise data

tjphQPI_SMI 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.6

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 12 932SQ420D REV J 010715 Electrical Characteristics - PCI Electrical Characteristics - 48MHz Electrical Characteristics - Current Consumption TA = 0 - 70°C; Supply Voltage V DD /VDD A = 3.3 V +/-5% , PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 O utput Low Voltage V OL IOL = 1 mA 0.55 V 1 MIN @VOH = 1.0 V -33 mA 1 MAX @V OH = 3.135 V -33 mA 1 MIN @VOL = 1.95 V 30 mA 1 MAX @ VOL = 0.4 V 38 mA 1 Clock High Time T HIGH 1.5V 12 ns 1 Clock Low Time T LO W 1.5V 12 ns 1 Edge Rate tsl ewr/f Rising/Falling edge rate 1 1.8 4 V/ns 1,2 Duty Cycle dt1 VT = 1.5 V 45 50.5 55 %1 Group Skew t skew VT = 1.5 V 294 500 ps 1 Jitter, Cycle to cycle tjc yc-cy c VT = 1.5 V 108 500 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. Measured between 0.8V and 2.0V Output High Current IOH Output Low Current IOL TA = 0 - 70°C; Supply Voltage V DD/VDD A = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD*(0.5) 20 60 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 O utput Low Voltage V OL IOL = 1 mA 0.55 V 1 MIN @VOH = 1.0 V -29 mA 1 MAX @V OH = 3.135 V -33 mA 1 MIN @VOL = 1.95 V 29 mA 1 MAX @ VOL = 0.4 V 27 mA 1 Clock High Time T HIGH 1.5V 8.094 10.036 ns 1 Clock Low Time T LO W 1.5V 7.694 9.836 ns 1 Edge Rate tslewr/f_USB Rising/Falling edge rate 1 1.5 2 V/ns 1,2 Duty Cycle d t1 VT = 1 . 5 V 4 55 15 5 % 1 Jitter, Cycle to cycle tjc yc-cy c VT = 1.5 V 109 350 ps 1 See "Single-ended Test Loads Page" for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. Measured between 0.8V and 2.0V Output High Current IOH Output Low Current IOL TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current IDD3.3OP All outputs active @100MHz, C L = Full load; 380 400 mA 1 Powerdown Current IDD3.3PDZ All differential pairs tri-stated 16 20 mA 1 Guar anteed by design and characterization, not 100% tested in pro ductio n.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 13 932SQ420D REV J 010715 Electrical Characteristics - REF TA = 0 - 70°C; Supply Voltage V DD/ VDD A = 3.3 V +/-5%, PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Output Impedance R DSP VO = VDD*(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 O utput Low Voltage V OL IOL = 1 mA 0.55 V 1 MIN @VOH = 1.0 V -33 mA 1 MAX @V OH = 3.135 V -33 mA 1 MIN @VOL = 1.95 V 30 mA 1 MAX @ VOL = 0.4 V 38 mA 1 Clock High Time T HIGH 1.5V 27.5 ns 1 Clock Low Time T LO W 1.5V 27.5 ns 1 Edge Rate t sl ewr/f Rising/Falling edge rate 1 1.9 4 V/ns 1,2 Duty Cycle dt1 VT = 1.5 V 45 50.5 55 % 1 Jitter, Cycle to cycle tjc yc-cy c VT = 1.5 V 75 1000 ps 1 See "Single-ended Test Loads Page" for termination circuits Guaranteed by design and characterization, not 100% tested in production. Measured between 0.8V and 2.0V Output High Current IOH Output Low Current IOL

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 14 932SQ420D REV J 010715 Clock AC Tolerances Clock Periods – Outputs with Spread Spectrum Disabled Clock Periods – Outputs with Spread Spectrum Enabled CPU SRC, NS_SAS, NS_SRC PCI DOT96 48MHz REF 100 100 100 100 100 100 ppm 50 50 500 250 350 1000 ps PPM tolerance Cycle to Cycle Jitter 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max SRC, NS_SAS, NS_SRC 1,2 REF Measurement Window UnitsSSC ON Cent er Freq. MHz CPU Notes 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max Guaranteed b y design and characterization, not 100% tested in pro ductio n. CPU All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz. Measurement Window UnitsSSC ON Cent er Freq. MHz Notes

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 15 932SQ420D REV J 010715 General SMBus Serial Interface Information How to Write

• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit SMBus write address = D2 hex SMBus read address = D3 hex How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O O O O O O Byte N + X - 1 ACK Ps t o P b i t Index Block Read Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O O O O O O Byte N + X - 1 N Not acknowledge Ps t o P b i t

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 16 932SQ420D REV J 010715 SMBus Table: Output Enable Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 DOT96 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 6 NS_SAS1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 NS_SAS0 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 4 NS_SRC1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 NS_SRC0 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 2 SRC2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 SRC1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 0 SRC0 Enable Output Enable RW Disable-Hi-Z Enable 1 SMBus Table: Output Enable Register Pin # Name Control Function Type 0 1 Defaul t Bit 7 REF14_3x Enable Output Enable RW Disable-Low Enable 1 Bit 6 0 Bit 5 0 Bit 4 CPU3 Output Enable RW Disable-Hi-Z Enable 1 Bit 3 CPU2 Output Enable RW Disable-Hi-Z Enable 1 Bit 2 CPU1 Output Enable RW Disable-Hi-Z Enable 1 Bit 1 CPU0 Output Enable RW Disable-Hi-Z Enable 1 Bit 0 Spread Spectr um Enable Spread Off/On RW Spread Off Spr ead On 0 SMBus Table: Output Enable Re gister Pin # Name Control Function Type 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 PCI4 Enable Output Enable RW Disable-Low Enable 1 Bit 4 PCI3 Enable Output Enable RW Disable-Low Enable 1 Bit 3 PCI2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 PCI1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 PCI0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 48MHz Enable Output Enable RW Disable-Low Enable 1 SMBus Table: Reserved Pin # Name Control Function Type 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 SMBus Table: Reserved Pin # Name Control Function Type 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Byte 3 Byte 4 CPU/SRC/ PCI Byte 2 Byte 1 Byte 0 RESERVED RESERVED

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 17 932SQ420D REV J 010715 SMBus Table: Reserved Pin # Name Control Function Type 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 FS4 Freq. Sel 4 RW 0 Bit 3 FS3 Freq. Sel 3 RW 1 Bit 2 FS2 Freq. Sel 2 RW 1 Bit 1 FS1 Freq. Sel 1 RW 1 Bit 0 FS0 Freq. Sel 0 RW 1 SMBus Table: Test Mode and CPU/SRC/PCI Frequenc y Select Re gister Pin # Name Control Function T ype 0 1 Defaul t Bit 7 Test Mode Test Mode Type RW Hi-Z REF/N 0 Bit 6 Test Select Select Test Mode RW Disable Enable 0 Bit 5 0 Bit 4 100M_133M# (See note) Frequency Select R 133MHz 100MHz Latch Bit 3 FS3 Freq. Sel 3 RW 1 Bit 2 FS2 Freq. Sel 2 RW 0 Bit 1 FS1 Freq. Sel 1 RW 0 Bit 0 FS0 Freq. Sel 0 RW 0 Note: Internal Pull up on 100M_133M# pin will result in default CPU frequency of 100 MHz. SMBus Table: Vendor & Revision ID Re gister Pin # Name Control Function T ype 0 1 Defaul t Bit 7 RID3 R 0 Bit 6 RID2 R 0 Bit 5 RID1 R 1 Bit 4 RID0 R 1 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 SMBus Table: Byte Count Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 0 Bit 1 BC1 RW 1 Bit 0 BC0 RW 0 SMBus Table: Device ID Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 DID7 R -- 0 Bit 6 DID6 R -- 0 Bit 5 DID5 R -- 0 Bit 4 DID4 R -- 1 Bit 3 DID3 R -- 0 Bit 2 DID2 R -- 1 Bit 1 DID1 R -- 1 Bit 0 DID0 R -- 1 0001 for ICS/IDT 0011 for D rev RESERVED VENDOR ID REVISION ID RESERVED RESERVED See NS_SAS/NS_SRC Frequency Table. Device ID (17 hex) Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is A bytes. (0 to 9 Byte 8 Byte 9 RESERVED Byte 6 Byte 5 Byte 7 See CPU/SRC/PCI Frequency Select Table

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 18 932SQ420D REV J 010715 Line Byte 1, Bit 0 Spread Enable Byte6 Bit3 FS3 Byte6 Bit2 FS2 Byte6 Bit1 FS1 Byte6 Bit0 FS0 CPU Speed for 100MHz CPU Speed for 133MHz SRC (MHz) PCI (M Hz) Spread 0 0 0 0 0 0 89.97 119.97 89.97 29.99 1 0 0 0 0 1 91.28 121.70 91.28 30.43 2 0 0 0 1 0 92.58 123.44 92.58 30.86 3 0 0 0 1 1 93.75 125.00 93.75 31.25 4 0 0 1 0 0 95.05 126.73 95.05 31.68 5 0 0 1 0 1 96.22 128.30 96.22 32.07 6 0 0 1 1 0 97.53 130.03 97.53 32.51 7 0 0 1 1 1 98.83 131.77 98.83 32.94 8 0 1 0 0 0 100.00 133.33 100.00 33.33 9 0 1 0 0 1 101.30 135.07 101.30 33.77 10 0 1 0 1 0 102.47 136.63 102.47 34.16 11 0 1 0 1 1 103.78 138.37 103.78 34.59 12 0 1 1 0 0 105.08 140.10 105.08 35.03 13 0 1 1 0 1 106.25 141.67 106.25 35.42 14 0 1 1 1 0 107.55 143.40 107.55 35.85 15 0 1 1 1 1 110.03 146.70 110.03 36.68 16 1 0 0 0 0 89.97 119.97 89.97 29.99 17 1 0 0 0 1 91.28 121.70 91.28 30.43 18 1 0 0 1 0 92.58 123.44 92.58 30.86 19 1 0 0 1 1 93.75 125.00 93.75 31.25 20 1 0 1 0 0 95.05 126.73 95.05 31.68 21 1 0 1 0 1 96.22 128.30 96.22 32.07 22 1 0 1 1 0 97.53 130.03 97.53 32.51 23 1 0 1 1 1 98.83 131.77 98.83 32.94 24 1 1 0 0 0 100.00 133.33 100.00 33.33 25 1 1 0 0 1 101.30 135.07 101.30 33.77 26 1 1 0 1 0 102.47 136.63 102.47 34.16 27 1 1 0 1 1 103.78 138.37 103.78 34.59 28 1 1 1 0 0 105.08 140.10 105.08 35.03 29 1 1 1 0 1 106.25 141.67 106.25 35.42 30 1 1 1 1 0 107.55 143.40 107.55 35.85 31 1 1 1 1 1 110.03 146.70 110.03 36.68 CPU/SRC/PCI Frequency Selection Table -0.5%

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 19 932SQ420D REV J 010715 Line Byte5 Bit 4 FS4 Byte5 Bit3 FS3 Byte5 Bit2 FS2 Byte5 Bit1 FS 1 Byte5 Bit0 FS0 NS_xxx (MHz) 0 0 0 0 0 0 58.33 1 0 0 0 0 1 61.11 2 0 0 0 1 0 63.89 3 0 0 0 1 1 66.67 4 0 0 1 0 0 69.44 5 0 0 1 0 1 72.22 6 0 0 1 1 0 75.00 7 0 0 1 1 1 77.78 8 0 1 0 0 0 80.56 9 0 1 0 0 1 83.33 10 0 1 0 1 0 86.11 11 0 1 0 1 1 88.89 12 0 1 1 0 0 91.67 13 0 1 1 0 1 94.44 14 0 1 1 1 0 97.22 15 01 1 1 1 100.00 16 1 0 0 0 0 102.78 17 1 0 0 0 1 105.56 18 1 0 0 1 0 108.33 19 1 0 0 1 1 111.11 20 1 0 1 0 0 113.89 21 1 0 1 0 1 116.67 22 1 0 1 1 0 119.44 23 1 0 1 1 1 122.22 24 1 1 0 0 0 125.00 25 1 1 0 0 1 127.78 26 1 1 0 1 0 130.56 27 1 1 0 1 1 133.33 28 1 1 1 0 0 136.11 29 1 1 1 0 1 138.89 30 1 1 1 1 0 141.67 31 1 1 1 1 1 144.44 NOTE: Operation at other than the default entry is not guaranteed. These values are for margining purposes only. NS_SAS Margining Table

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 21 932SQ420D REV J 010715 Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) HCSL Output Buffer L1' R1b L2' R1a L4' R2a R2b Down Device REF_CLK Input Figure 3 L3' R3 R4 Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Cable Connected AC Coupled Application (figure 4) PCIe Device REF_CLK Input Figure 4 R5a L4'

3.3 Volts

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 22 932SQ420D REV J 010715 Test Clarification Table Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 68.2 C/W JA 1 m/s air flow 63.3 C/W JA 2 m/s air flow 59.6 C/W Thermal Resistance Junction to Case JC 32.5 C/W Thermal Resistance Junction to Board JB 51.5 C/W Comments TEST_SEL HW P IN TEST_MODE HW PIN TE ST ENTRY BIT B6b6 REF/N or HI-Z B6b7 OUTPUT

0 X 0 X NORMAL

B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) HW SW Power-up w/ TEST_SEL = 1 (>2.0V) to enter test mode. Cycle power to disable test mode. If TEST_SEL HW pin is 0 during power-up, test mode can be selected through B6b6. If test mode is selected by B6b6, then B6b7 is used to select HI-Z or REF/N. TEST_Mode pin is not used. Cycle power to disable test mode.

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 23 932SQ420D REV J 010715 Package Outline and Package Dimensions (64-pin TSSOP)

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 24 932SQ420D REV J 010715 Package Outline and Package Dimensions (64-pin MLF)

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 25 932SQ420D REV J 010715 Package Outline and Package Dimensions, cont. (64-pin MLF)

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 26 932SQ420D REV J 010715 Marking Diagram (TSSOP) Marking Diagram (MLF) Notes: 1. ’LOT’ denotes lot number. 2. ‘YYWW’ is the date code. 3. ‘COO’ denotes country of origin. 4. ‘L ’ or ‘LF’ denotes RoHS compliant package.

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. “D” is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS LOT YYWW 932SQ420DGLF ICS 932SQ420DKL LOT COO YYWW Part / Order Number Shipping Packaging Package Temperature 932SQ420DGLF Tubes 64-pin TSSOP 0 to +70° C 932SQ420DGLFT Tape and Reel 64-pin TSSOP 0 to +70° C 932SQ420DKLF Tray 64-pin MLF 0 to +70° C 932SQ420DKLFT Tape and Reel 64-pin MLF 0 to +70° C

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 27 932SQ420D REV J 010715

Revision History

Rev. Issue Date Who Description Page # A 9/20/2010 RDW Minor typo corrections Various B 3/1/2011 RDW Added rise/fall variation to DC Electrical Characteristics Table 9 C3 / 9 / 2 0 1 1 R D W Corrected Line 0 of NS_SAS Margining Table. 19 D 4/28/2011 RDW Corrected MLF packaging pin description. Pin 37 was missing. 7 E 7/26/2011 RDW Updated Power Down Functionality table to clarify functionality of single- ended outputs in power down. 2 F 9/20/2011 RDW 1. Added "Case Temperature" spec to Abs Max ratings 2. Added Thermal Characteristics Various G 12/8/2011 RDW 1. Updated Phase Jitter Table to correct typo in "Conditions" column for SAS. 2. Mark Spec Added. 11, 23, H 4/18/2012 RDW 1. Updated Rp values on Output Terminations Table from 43.2 ohms to 42.2 or 43.2 ohms to be consistent with Intel. 8 J1 / 7 / 2 0 1 5 D C 1. Updated package drawing and dimensions from PUNCH to SAWN version. Various

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