932S401EFLF

ICS932S401 RENESAS | Alldatasheet

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Systems, Inc. ICS932S401 0921G—08/24/09 Pin Configuration Recommended Application: CK410B clock for Intel-based servers Output Features:  4 - 0.7V current-mode differential CPU pairs  5 - 0.7V current-mode differential SRC pair  4 - PCI (33MHz)  3 - PCICLK_F , (33MHz) free-running  1 - 48MHz  2 - REF , 14.318MHz Programmable Timing Control Hub for Intel-based Servers 932S401 Functionality Key Specifications:  CPU cycle-cycle jitter: < 50ps  SRC cycle-cycle jitter: < 125ps  PCI cycle-cycle jitter: < 500ps  CPU output skew: < 50ps  SRC output skew: < 250ps  ± 300ppm frequency accuracy on all outputs except 48MHz  ± 100ppm frequency accuracy on 48MHz Features/Benefits:  Supports spread spectrum modulation, 0 to -0.5% down spread  Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error  CPU clocks independent of SRC/PCI clocks  D2/D3 SMBus address 56-pin SSOP & TSSOP VDDPCI 1 56 FS_C/TEST_SEL GNDPCI 2 55 REF0 PCICLK0 3 54 REF1 PCICLK1 4 53 VDDREF PCICLK2 5 52 X1 PCICLK3 6 51 X2 GNDPCI 7 50 GNDREF VDDPCI 8 49 FS_B/TEST_MODE PCICLK_F0 9 48 FS_A PCICLK_F1 10 47 VDDCPU PCICLK_F2 11 46 CPUCLKT0 VDD48 12 45 CPUCLKC0 48MHz 13 44 VDDCPU G N D 4 81 4 4 3C P U C L K T 1 VDDSRC 15 42 CPUCLKC1 SRCCLKT0 16 41 GNDCPU SRCCLKC0 17 40 CPUCLKT2 SRCCLKC1 18 39 CPUCLKC2 SRCCLKT1 19 38 VDDCPU GNDSRC 20 37 CPUCLKT3 SRCCLKT2 21 36 CPUCLKC3 SRCCLKC2 22 35 VDDA SRCCLKC3 23 34 GNDA SRCCLKT3 24 33 IREF VDDSRC 25 32 NC SRCCLKT4 26 31 Vtt_PwrGd#/PD SRCCLKC4 27 30 SDATA VDDSRC 28 29 SCLK ICS932S401 FS_C1 FS_B1 FS_A2 CPU MHz SRC MHz PCI MHz REF MHz USB MHz 11 1 1. FS_B and FS_C are three-level inputs. Please see V IL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_A is a low-threshold input. Please see the V IL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Reserved

Systems, Inc. ICS932S401 0921G—08/24/09 Pin Description Pin # PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

2 GNDPCI PWR Ground pin for the PCI outputs

3 PCICLK0 OUT PCI clock output. 4 PCICLK1 OUT PCI clock output. 5 PCICLK2 OUT PCI clock output. 6 PCICLK3 OUT PCI clock output.

7 GNDPCI PWR Ground pin for the PCI outputs

8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 9 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# . 10 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# . 11 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# . 12 VDD48 PWR Power pin for the 48MHz output.3.3V 13 48MHz OUT 48MHz clock output.

14 GND48 PWR Ground pin for the 48MHz outputs

15 VDDSRC PWR Supply for SRC clo cks, 3.3V nominal 16 SRCCLKT0 OUT True clock of differential SRC clock pair. 17 SRCCLKC0 OUT Complement clock of differential SRC clock pair. 18 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 19 SRCCLKT1 OUT True clock of differential SRC clock pair.

20 GNDSRC PWR Ground pin for the SRC outputs

21 SRCCLKT2 OUT True clock of differential SRC clock pair. 22 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 23 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 VDDSRC PWR Supply for SRC clo cks, 3.3V nominal 26 SRCCLKT4 OUT True clock of differential SRC clock pair. 27 SRCCLKC4 OUT Complement clock of differential SRC clock pair. 28 VDDSRC PWR Supply for SRC clo cks, 3.3V nominal

Systems, Inc. ICS932S401 0921G—08/24/09 Pin Description (Continued) Pin # PIN NAME T ype Pin Descri ption 29 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 30 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.

31 Vtt_PwrGd#/PD IN

Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the cr ystal oscillator are stopped. 32 NC N/A No Connection.

33 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value.

34 GNDA PWR Ground

pin for the PLL core. 35 VDDA PWR 3.3V power for the PLL core. 36 CPUCLKC3 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 37 CPUCLKT3 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 38 VDDCPU PWR Su pply for CPU clocks, 3.3V nominal 39 CPUCLKC2 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 40 CPUCLKT2 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias.

41 GNDCPU PWR Ground pin for the CPU outputs

42 CPUCLKC1 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 43 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 44 VDDCPU PWR Su pply for CPU clocks, 3.3V nominal 45 CPUCLKC0 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 46 CPUCLKT0 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 47 VDDCPU PWR Su pply for CPU clocks, 3.3V nominal 48 FS_A IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.

49 FS_B/TEST_MODE IN

3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.

50 GNDREF PWR Ground

pin for the REF outputs. 51 X2 OUT Cr ystal output, Nominally 14.318MHz 52 X1 IN Cr ystal input, Nominally 14.318MHz. 53 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 54 REF1 OUT 14.318 MHz reference clock. 55 REF0 OUT 14.318 MHz reference clock.

56 FS_C/TEST_SEL IN

3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table

Systems, Inc. ICS932S401 0921G—08/24/09 ICS932S401 is a main clock synthesizer for CK410-generation Intel server platforms. ICS932S401 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100 or 200 MHz. The 48 MHz USB clock is an exact 48.000 MHz clock. The ICS932S401 generates all clocks with less the +/- 300 ppm error. General Description Block Diagram Power Groups CPU PLL PCICLK(3:0), PCICLK_F(2:0) CONTROL LOGIC XTAL OSC. CPUCLK(2:0) FIXED PLL 48MHz DIVIDER DIVIDERS REF(1:0) SRCCLK(4:0) SDATA SCLK IREF FS(C:A) VTT_PWRGD#/PD SRC/PCI PLL DIVIDERS TEST_SEL VDD GND 53 50 Xtal, Ref 1,8 2,7 PCICLK outputs 15,25,28 20 SRCCLK outputs 35 34 Master clock, CPU Analog 12 14 48MHz, PLL_48 47,44,38 41 CPUCLK clocks DescriptionPin Number

Systems, Inc. ICS932S401 0921G—08/24/09 Absolute Max Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage VDD + 0.5V V VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient O perating Temp 07 0 ° C Tcase Case Tem perature 115 °C ESD prot Input ESD protection human body model 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage V IH 3.3 V +/-5% 2 V DD + 0.3 V Input Low Voltage V IL 3.3 V +/-5% V SS - 0.3 0.8 V Input High Current I IH VIN = VDD -5 5 uA IIL1 VIN = 0 V; Inputs with no pull- up resistors -5 uA IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA Low Threshold Input High Voltage VIH_FS 3.3 V +/-5% 0.7 V DD + 0.3 V Low Threshold Input Low Voltage VIL_FS 3.3 V +/-5% V SS - 0.3 0.35 V Operating Supply Current I DD3.3OP 3.3 V +/-5%, Full Load 270 350 mA all diff pairs driven 60 90 mA all differential pairs tri-stated 9 15 mA Input Frequency3 Fi VDD = 3.3 V 14.31818 MHz 3 Pin Inductance1 Lpin 7n H 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization1,2 TSTAB From VDD Power-Up or de- assertion of PD# to 1st clock 1.8 ms 1,2 Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_PD# CPU output enable after PD# de-assertion 300 us 1 Tfall_Pd# PD# fall time of 5 ns 1 Trise_Pd# PD# rise time of 5 ns 2 SMBus Voltage V IMAX Max. Voltage on SCLK/SDAT 5.5 V 1 Low-level Output Voltage V OLSMBUS @ IPULLUP 0.4 V 1 Current sinking at VOL = 0.4 V IPULLUP 4m A 1 SCLK/SDATA Clock/Data Rise Time TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1Guaranteed by design and characterization, not 100% tested in production. 2See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL outputs. Input Low Current Powerdown Current I DD3.3PD Input Capacitance1

Systems, Inc. ICS932S401 0921G—08/24/09 Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo VO = Vx 3000 Ω 1 Voltage High VHigh 660 775 850 1 Voltage Low VLow -150 70 150 1 Max VoltageV o v s 1 1 5 0 1 Min Voltage Vuds -300 1 Crossing Voltage (abs) Vcross (abs) 250 355 550 mV 1 Crossing Voltage (var) d-Vcross Variation of crossing over all edges 90 140 mV 1 Long Accuracy ppm see T period min-max values -300 0 300 ppm 1,2 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2 333.33MHz nominal 2.9991 3.0009 ns 2 333.33MHz spread 2.9991 3.016 ns 2 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 7.5400 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.4128 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 240 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 359 700 ps 1 Rise Time Variation d-tr 49 125 ps 1 Fall Time Variation d-tf 59 125 ps 1 Duty Cycle dt3 Measurement from differential wavefrom 45 49 55 % 1 Skew tsk3 CPU (3:0) VT = 50% 33 50 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 38 50 ps 1 1Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz TabsminAbsolute min period Statistical measurement on single ended signal using oscilloscope math function. mV Measurement on single ended signal using absolute value. mV Average period Tperiod

Systems, Inc. ICS932S401 0921G—08/24/09 Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo VO = Vx 3000 Ω 1 Voltage HighV H i gh 660 780 850 1 Voltage Low VLow -150 10 150 1 Max Voltage Vovs 1150 1 Min Voltage Vuds -300 1 Crossing Voltage (abs) Vcross(abs) 250 369 550 mV 1 Crossing Voltage (var) d-Vcross Variation of crossing over all edges 57 140 mV 1 Long Accuracy ppms e e T period min-max values -300 0 300 ppm1 , 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 Absolute min period Tabsmin 100.00MHz nominal/s pread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 283 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 291 700 ps 1 Rise Time Variation d-tr 27 125 ps 1 Fall Time Variation d-tf 30 125 ps 1 Duty Cycle dt3 Measurement from differential wavefrom 45 51 55 % 1 Skew tsk3 SRC(4:0), VT = 50% 15 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 38 125 ps 1 1Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz mV Measurement on single ended signal using absolute value. mV Average period Tperiod Statistical measurement on single ended signal using oscilloscope

Systems, Inc. ICS932S401 0921G—08/24/09 Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see T period min-max values -300 0.00 300 ppm1 , 2 33.33MHz output nominal 29.99100 30.00900 ns 2 33.33MHz output spread 29.99100 30.15980 ns 2 33.33MHz output nominal 29.49100 30.50900 ns 2 33.33MHz output spread 29.49100 30.65980 ns 2 Clk High Time th1 12 N/A ns 1 Clock Low Time tl1 12 N/A ns 1 Output High Voltage VOH IOH = -1 mA 2.4 V Output Low Voltage VOL IOL = 1 mA 0.55 V V OH @MIN = 1.0 V -33 mA VOH@ MAX = 3.135 V -33 mA VOL @ MIN = 1.95 V 30 mA VOL @ MAX = 0.4 V 38 mA Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 0.74 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 0.73 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 50.4 55 % 1 Skew tsk1 VT = 1.5 V 43 500 ps 1 Jitter tjcyc-cyc VT = 1.5 V 98 500 ps 1 1Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz Clock period Tperiod Output High Current IOH Output Low Current IOL Absolute Min/Max Clock period Tabs Electrical Characteristics - 48MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppms e e T period min-max values -100 0 100 ppm1 , 2 Clock period Tperiod 48.0000MHz output nominal 20.83125 20.83542 ns 2 Absolute Min/Max Clock period Tabs Nominal 20.48125 21.18542 ns 2 Clk High Time th1 8.094 ns 1 Clock Low Time tl1 7.694 ns 1 V OH @ MIN = 1.0 V -33 mA VOH@ MAX = 3.135 V -33 mA VOL @MIN = 1.95 V 30 mA VOL @ MAX = 0.4 V 38 mA Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 11 . 12 n s 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 11 . 32 n s 1 Duty Cycle dt1 VT = 1.5 V 45 52.3 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 243 350 ps 1 1Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFout is at 14.31818MHz Output Low Current IOL Output High Current IOH

Systems, Inc. ICS932S401 0921G—08/24/09 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppms e e T period min-max values -300 0 300 ppm1 Clock period Tperiod 14.318MHz output nominal 69.82033 69.86224 ns 1 Absolute Min/Max Clock period Tabs Nominal 68.82033 70.86224 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Output High Current IOH VOH @MIN = 1.0 V, VOH@MAX = 3.135 V -29 -23 mA 1 Output Low Current IOL VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 0.6 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 0.85 2 ns 1 Skew tsk1 VT = 1.5 V 26 500 ps 1 Duty Cycle dt1 VT = 1.5 V 45 52.7 55 % 1 Jitter tjcyc-cyc VT = 1.5 V 917 1000 ps 1 1Guaranteed by design, not 100% tested in production.

Systems, Inc. ICS932S401 0921G—08/24/09 Test Load CL=5pF Rs Zo ICS932S401 SEPP Output Buffer (Single Ended Push Pull) Rs Zo Rs Zo SEPP Output Buffer (Single Ended Push Pull) CL=5pF CL=5pF The singled-ended outputs of the ICS 932S401E default to a drive strength of 2 loads. The REF clocks can be turned down to 1-load strength via the SMBus. Suggested termination resistors are as follows for transmission lines with Zo = 50 ohms: Driving 1 load, Rs = 33 ohms Driving 2 loads, Rs = 7.5 ohms Single-ended outputs at 1-load strength (REF clock only) Driving 1 load, Rs = 22 ohms Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Single-ended Output Terminations

Systems, Inc. ICS932S401 0921G—08/24/09 General SMBus serial interface information for the ICS932S401 How to Write:

• Controller (host) sends a start bit.  Controller (host) sends the write address D2 (H)  ICS clock will acknowledge  Controller (host) sends the begining byte location = N  ICS clock will acknowledge  Controller (host) sends the data byte count = X  ICS clock will acknowledge  Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2)  ICS clock will acknowledge each byte one at a time  Controller (host) sends a Stop bit How to Read:  Controller (host) will send start bit.  Controller (host) sends the write address D2 (H)  ICS clock will acknowledge  Controller (host) sends the begining byte location = N  ICS clock will acknowledge  Controller (host) will send a separate start bit.  Controller (host) sends the read address D3 (H)  ICS clock will acknowledge  ICS clock will send the data byte count = X  ICS clock sends Byte N + X -1  ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8).  Controller (host) will need to acknowledge each byte  Controllor (host) will send a not acknowledge bit  Controller (host) will send a stop bit ICS (Slave/Receiver) T WR ACK ACK ACK ACK ACK P stoP bit X Byte Index Block Write Operation Slave Address D2(H) Beginning Byte = N WRite starT bit Controller (Host) Byte N + X - 1 Data Byte Count = X Beginning Byte N T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge Ps t o P b i t Slave Address D3(H) Index Block Read Operation Slave Address D2(H) Beginning Byte = N ACK ACK Data Byte Count = X ACK ICS (Slave/Receiver)Controller (Host) X Byte ACK ACK

Systems, Inc. ICS932S401 0921G—08/24/09 SMBus Table: SRC Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 SRCCLK7 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 6 SRCCLK6 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 5 SRCCLK5 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 4 SRCCLK4 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 3 SRCCLK3 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 2 SRCCLK2 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 1 SRCCLK1 Enable Output Enable RW Disable-Hi-Z Enable 1 Bit 0 SRCCLK0 Enable Output Enable RW Disable-Hi-Z Enable 1 SMBus Table: CPU, REF and 48 MHz Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 REF1 Enable Output Enable RW Disable-Low Enable 1 Bit 6 REF0 Enable Output Enable RW Disable-Low Enable 1 Bit 5 CPUCLK3 Output Enable RW Disable-Hi-Z Enable 1 Bit 4 CPUCLK2 Output Enable RW Disable-Hi-Z Enable 1 Bit 3 0 Bit 2 CPUCLK1 Output Enable RW Disable-Hi-Z Enable 1 Bit 1 CPUCLK0 Output Enable RW Disable-Hi-Z Enable 1 Bit 0 Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0 SMBus Table: PCI and PCICLK_F Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 PCICLK3 Output Enable RW Disable-Low Enable 1 Bit 6 PCICLK2 Output Enable RW Disable-Low Enable 1 Bit 5 PCICLK1 Output Enable RW Disable-Low Enable 1 Bit 4 PCICLK0 Output Enable RW Disable-Low Enable 1 Bit 3 PCICLK_F2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 PCICLK_F1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 PCICLK_F0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 48MHz Enable Output Enable RW Disable-Low Enable 1 SMBus Table: PCICLK_F and SRC Stop Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 PCICLK_F2 Stop En RW Free-Running Stoppable 1 Bit 6 PCICLK_F1 Stop En RW Free-Running Stoppable 1 Bit 5 PCICLK_F0 Stop En RW Free-Running Stoppable 1 Bit 4 SRCCLK4 Stop En RW Free-Running Stoppable 1 Bit 3 SRCCLK3 Stop En RW Free-Running Stoppable 1 Bit 2 SRCCLK2 Stop En RW Free-Running Stoppable 1 Bit 1 SRCCLK1 Stop En RW Free-Running Stoppable 1 Bit 0 SRCCLK0 Stop En RW Free-Running Stoppable 1 42,43 45,46 23,24 21,22 36,37 16,17 Byte 1 18,19 39,40 Byte 0 NA NA 26,27 NA Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 6, bit 3) 16,17 18,19 21,22 23,24 CPU, SRC, PCI Byte 2 26,27 RESERVED Byte 3

Systems, Inc. ICS932S401 0921G—08/24/09 SMBus Table: CPU and SRC Stop and Power Down Mode Drive Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 CPUCLK3 PD Drive Drive Mode in PD RW Driven Hi-Z 0 Bit 6 CPUCLK2 PD Drive Drive Mode in PD RW Driven Hi-Z 0 Bit 5 CPUCLK1 PD Drive Drive mode in PD RW Driven Hi-Z 0 Bit 4 CPUCLK0 PD Drive Drive mode in PD RW Driven Hi-Z 0 Bit 3 CPUCLK3 Stop En RW Free-Running Stoppable 1 Bit 2 CPUCLK2 Stop En RW Free-Running Stoppable 1 Bit 1 CPUCLK1 Stop En RW Free-Running Stoppable 1 Bit 0 CPUCLK0 Stop En RW Free-Running Stoppable 1 SMBus Table: Output and Spread Spectrum Control Register Byte 5 Pin # Name Control Function Type 0 1 PWD Bit 7 0 Bit 6 SRC Stop Drive Mode Driven in STOP RW Driven Hi-Z 0 Bit 5 SRC PD Drive Mode Driv en in PD RW Driven Hi-Z 0 Bit 4 0 Bit 3 CPUCLK3 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 Bit 2 CPUCLK2 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 Bit 1 CPUCLK1 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 Bit 0 CPUCLK0 Stop Drive Drive Mode in Stop RW Driven Hi-Z 0 SMBus Table: Device ID Register Pin # Name Control Function Type 0 1 PWD Bit 7 Test Mode Selection Test Mode Selection RW Hi-Z REF/N 0 Bit 6 Test Clock Mode Entry Test Mode RW Disable Enable 0 Bit 5 0 Bit 4 REF Drive Strength 1X or 2X RW 1X 2X 1 Bit 3 PCI_STOP Control Stop non-free running PC and SRC clocks. RW Stop Run 1 Bit 2 FS_C FS_C readback RL a t c h Bit 1 FS_B FS_B readback RL a t c h Bit 0 FS_A FS_A readback RL a t c h SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Type 0 1 PWD Bit 7 RID3 R - - X Bit 6 RID2 R - - X Bit 5 RID1 R - - X Bit 4 RID0 R - - X Bit 3 VID3 R - - 0 Bit 2 VID2 R - - 0 Bit 1 VID1 R - - 0 Bit 0 VID0 R - - 1 RESERVED RESERVED See 932S401 Functionality Table Byte 7 Byte 4 SRC SRC 36,37 39,40 42,43 Free-Running Control, Default: not affected by CPU_STOP 45,46 RESERVED 42,43 39,40 PCI, SRC 54,55 36,37 39,40 36,37 Byte 6 45,46 VENDOR ID 42,43 45,46 REVISION ID

Systems, Inc. ICS932S401 0921G—08/24/09 SMBus Table: Byte Count Register Pin # Name Control Function Type 0 1 PWD Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 0 Bit 2 BC2 RW 1 Bit 1 BC1 RW 1 Bit 0 BC0 RW 1 SMBus Table: Device ID Register Pin # Name Control Function Type 0 1 PWD Bit 7 DID7 R - - 0 Bit 6 DID6 R - - 0 Bit 5 DID5 R - - 0 Bit 4 DID4 R - - 0 Bit 3 DID3 R - - 1 Bit 2 DID2 R - - 0 Bit 1 DID1 R - - 1 Bit 0 DID0 R - - 1 SMBus Table: M/N Programming & Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 M/N_EN CPU and SRC M/N Programming Enable RW Disable Enable 0 Bit 6 CPU_STOP Control Stop non-free running PC and SRC clocks. RW Stop Run 1 Bit 5 0 Bit 4 0 Bit 3 SRC Alternate Frequency (96% of Nominal) Set SRC = 96 MHz and PCI = 32 MHz Only active if Byte 10, bit 2 = 1 RW Normal Alternate Frequency 0 Bit 2 CPU Alternate Frequency (96% of Nominal) Only active if latched frequency is 166 MHz or 333 MHz. Set alternate CPU frequency:

166 MHz to 160 MHz

333 MHz to 320 MHz

Bit 1 REF0 Drive Strength 1X or 2X RW 1 Bit 0 REF1 Drive Strength 1X or 2X RW 1 Device ID (0B hex) Byte Count Programming b(7:0) Byte 8 Byte 9 Byte 10 CPU SRC, PCI CPU Writing to this register will configure how many bytes will be read back, default is 8 bytes. (0 to 7) See REF Drive Strength Functionality Table RESERVED RESERVED

Systems, Inc. ICS932S401 0921G—08/24/09 SMBus Table: CPU Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 CPU N Div8 N Divider Prog bit 8 RW X Bit 6 CPU N Div9 N Divider Prog bit 9 RW X Bit 5 CPU M Div5 RW X Bit 4 CPU M Div4 RW X Bit 3 CPU M Div3 RW X Bit 2 CPU M Div2 RW X Bit 1 CPU M Div1 RW X Bit 0 CPU M Div0 RW X SMBus Table: CPU Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 CPU N Div7 RW X Bit 6 CPU N Div6 RW X Bit 5 CPU N Div5 RW X Bit 4 CPU N Div4 RW X Bit 3 CPU N Div3 RW X Bit 2 CPU N Div2 RW X Bit 1 CPU N Div1 RW X Bit 0 CPU N Div0 RW X SMBus Table: CPU Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 0 1 PWD Bit 7 CPU SSP7 RW X Bit 6 CPU SSP6 RW X Bit 5 CPU SSP5 RW X Bit 4 CPU SSP4 RW X Bit 3 CPU SSP3 RW X Bit 2 CPU SSP2 RW X Bit 1 CPU SSP1 RW X Bit 0 CPU SSP0 RW X SMBus Table: CPU Spread Spectrum Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 0 Bit 6 CPU SSP14 RW X Bit 5 CPU SSP13 RW X Bit 4 CPU SSP12 RW X Bit 3 CPU SSP11 RW X Bit 2 CPU SSP10 RW X Bit 1 CPU SSP9 RW X Bit 0 CPU SSP8 RW X Byte 12 Byte 14 The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = [MDiv(5:0)+2] Spread Spectrum Programming bit(7:0) N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) The decimal representation of M and N Divider in Byte 11 and 12 will configure the CPU VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = [MDiv(5:0)+2] M Divider Programming bit (5:0) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of CPU Spread Spectrum Programming bit(14:8) Reserved These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of CPU Byte 11

Systems, Inc. ICS932S401 0921G—08/24/09 SMBus Table: SRC Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 SRC N Div8 N Divider Prog bit 8 RW X Bit 6 SRC N Div9 N Divider Prog bit 9 RW X Bit 5 SRC M Div5 RW X Bit 4 SRC M Div4 RW X Bit 3 SRC M Div3 RW X Bit 2 SRC M Div2 RW X Bit 1 SRC M Div1 RW X Bit 0 SRC M Div0 RW X SMBus Table: SRC Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 SRC N Div7 RW X Bit 6 SRC N Div6 RW X Bit 5 SRC N Div5 RW X Bit 4 SRC N Div4 RW X Bit 3 SRC N Div3 RW X Bit 2 SRC N Div2 RW X Bit 1 SRC N Div1 RW X Bit 0 SRC N Div0 RW X SMBus Table: SRC Spread Spectrum Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 SRC SSP7 RW X Bit 6 SRC SSP6 RW X Bit 5 SRC SSP5 RW X Bit 4 SRC SSP4 RW X Bit 3 SRC SSP3 RW X Bit 2 SRC SSP2 RW X Bit 1 SRC SSP1 RW X Bit 0 SRC SSP0 RW X SMBus Table: SRC Spread Spectrum Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved R - - 0 Bit 6 SRC SSP14 RW X Bit 5 SRC SSP13 RW X Bit 4 SRC SSP12 RW X Bit 3 SRC SSP11 RW X Bit 2 SRC SSP10 RW X Bit 1 SRC SSP9 RW X Bit 0 SRC SSP8 RW X Byte 18 Byte 15 Byte 16 These Spread Spectrum bits in Byte 17 and 18 will program the spread pecentage of SRC Spread Spectrum Programming b(7:0) The decimal representation of M and N Divider in Byte 15 and 16 will configure the SRC VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = [MDiv(5:0)+2] M Divider Programming bits These Spread Spectrum bits in Byte 17 and 18 will program the spread pecentage of SRC Spread Spectrum Programming b(14:8) Byte 17 N Divider Programming b(7:0) The decimal representation of M and N Divider in Byte 15 and 16 will configure the SRC VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = [MDiv(5:0)+2]

Systems, Inc. ICS932S401 0921G—08/24/09 SMBus Table: CPU Programmable Output Divider Register Pin # Name Control Function Type 0 1 PWD Bit 7 CPUDiv3 RW X Bit 6 CPUDiv2 RW X Bit 5 CPUDiv1 RW X Bit 4 CPUDiv0 RW X Bit 3 X Bit 2 X Bit 1 X Bit 0 X SMBus Table: SRC and PCI Programmable Output Divider Register Pin # Name Control Function Type 0 1 PWD Bit 7 PCIDiv3 RW X Bit 6 PCIDiv2 RW X Bit 5 PCIDiv1 RW X Bit 4 PCIDiv0 RW X Bit 3 SRC_Div3 RW X Bit 2 SRC_Div2 RW X Bit 1 SRC_Div1 RW X Bit 0 SRC_Div0 RW X SMBusTable: Test Byte Register Test Type PWD Bit 7 RW 0 Bit 6 RW 0 Bit 5 RW 0 Bit 4 RW 0 Bit 3 RW 0 Bit 2 RW 0 Bit 1 RW 0 Bit 0 RW 0 Note: Do NOT write to Bit 21. Erratic device operation will result! Byte 19 Byte 20 See CPU, SRC and PCI Divider Ratios Table See CPU, SRC and PCI Divider Ratios Table RESERVED RESERVED RESERVED RESERVED CPU Divider Ratio Programming Bits ICS ONLY TEST Reserved ICS ONLY TEST Reserved ICS ONLY TEST Reserved ICS ONLY TEST Reserved ICS ONLY TEST Reserved ICS ONLY TEST Reserved ICS ONLY TEST Reserved Test Function Test Result \` ICS ONLY TEST Reserved Byte 21 SRC_ Divider Ratio Programming Bits PCI Divider Ratio Programming Bits- See CPU, SRC and PCI Divider Ratios Table

Systems, Inc. ICS932S401 0921G—08/24/09 REF Drive Strength Functionality Byte6, bit 4 Byte 10, bit 1 Byte 10, bit 0 REF1 REF0 0X X 1 x 1 x 10 0 1 x 1 x 10 1 1 x 2 x 11 0 2 x 1 x 11 1 2 x 2 x CPU, SRC and PCI Divider Ratios Div(3:0) Divider 00 0 0 0 2 10 0 0 1 3 20 0 1 0 5 30 0 1 1 1 5 40 1 0 0 4 50 1 0 1 6 60 1 1 0 1 0 70 1 1 1 3 0 81 0 0 0 8 91 0 0 1 1 2 10 1010 20 11 1011 60 12 1100 16 13 1101 24 14 1110 40 15 1111 120

Systems, Inc. ICS932S401 0921G—08/24/09 PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down. When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD i s de-asserted. PD, Power Down DPU PC# UPCC RS# CRSI CP/FICPB SUF ERe toN 1l amroNl amroNl amroNl amroNz HM33z HM84z HM813.411 0r o2*ferI taolF taolF2 *ferI taolFro taolFw oLw oLw oL1 Notes: 1. Refer to SMBus Byte 4 for additional information. PD# should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control registe r determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. See SMBus Byte 4 for additional information. PD Assertion PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz USB, 48MHz PCI, 33MHz REF, 14.31818

Systems, Inc. ICS932S401 0921G—08/24/09 The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300 µs of PD deassertion. PD De-assertion PWRDWN# Tstable <1.8mS Tdrive_PwrDwn# <300µS, >200mV CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC# 100MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Test Clarification Table Comments FS_C/TEST _SEL HW PIN FS_B/TEST _MODE HW PIN TEST ENTRY BIT B6b6 REF/N or HI-Z B6b7 OUTPUT

0 X 0 X NORMAL

B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) HW SW Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FS_C./TEST_SEL -->3-level latched input If power-up w/ V>2.0V (-0.3V) then use TEST_SEL If power-up w/ V<2.0V (-0.3V) then use FS_C FS_B/TEST_MODE -->low Vth input TEST_MODE is a If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B6b6. If test mode is invoked by B6b6, only B6b7 is used to select HI-Z or REF/N FS_B/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control

Systems, Inc. ICS932S401 0921G—08/24/09 MIN MAX MIN MAX A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N a 0 °8 °0 °8 ° VARIATIONS MIN MAX MIN MAX 56 18.31 18.55 .720 .730 10-0034 0.635 BASIC 0.025 BASIC COMMON DIMENSIONS In Millimeters In Inches COMMON DIMENSIONS Reference Doc.: JEDEC Publication 95, MO-118 N SEE VARIATIONS SEE VARIATIONS D mm. D (inch) SYMBOL SEE VARIATIONS SEE VARIATIONS INDEX AREA INDEX AREA 121 2 N D h x 45°h x 45° E1 E α SEATING PLANE SEATING PLANE A e -C-- C - b c L

Systems, Inc. ICS932S401 0921G—08/24/09 MIN MAX MIN MAX A -- 1.20 -- .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e L 0.45 0.75 .018 .030 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 13.90 14.10 .547 .555 10-0039 N D mm. D (inch) Reference Doc.: JEDEC Publication 95, MO-153 0.50 BASIC 0.020 BASIC SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS INDEX AREA INDEX AREA 1 21 2 N D E1 E /c97 SEATING PLANE SEATING PLANE AA2A2 e - C -- C - b c L aaa C

Ordering Information

Part / Order Number Shipping Packaging Package Temperature 932S401EFLF Tubes 56-pin SSOP 0 to +70° C 932S401EFLFT Tape and Reel 56-pin SSOP 0 to +70° C 932S401EGLF Tubes 56-pin TSSOP 0 to +70° C 932S401EGLFT Tape and Reel 56-pin TSSOP 0 to +70° C “LF” suffix to the part number denotes Pb-Free configuration, RoHS compliant.

Systems, Inc. ICS932S401 0921G—08/24/09

Revision History

Rev. Issue Date Description Page # A 5/2/2005 1. Updated Electrical Characterisitcs tables with typical data 2. Added Notes on Termination of Single-ended outputs 5-10 B 5/18/2006 1. Changed Max CPU Skew from 100ps to 50ps. 6 C 5/30/2006 Updated Key Specifications: CPU output skew. 1 D 8/22/2006 Updated Single-ended Output Terminations. 10 E 9/11/2006 Updated SMBus. Bytes 0-7 to match CK410B. 12-13 F 6/13/2007 Updated operating supply and power down current values 5 G 8/24/2009 1. Updated Byte 3 table. 2. Added new ordering information table. 13

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