932S208YFLNT | DigiCamel IC Datasheet

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ICS932S208 IDT | Alldatasheet

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IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 Programmable Timing Control HubTM for Next Gen P4TM Processor DATASHEET Pin Configuration Recommended Application: CK409B clock, Intel Y ellow Cover part, Server Applications Output Features:

4 - 0.7V current-mode differential CPU pairs 1 - 0.7V current-mode differential SRC pair 7 - PCI (33MHz) 3 - PCICLK_F , (33MHz) free-running 1 - USB, 48MHz 1 - DOT, 48MHz 2 - REF , 14.318MHz 4 - 3V66, 66.66MHz 1 - VCH/3V66, selectable 48MHz or 66MHz Key Specifications: CPU/SRC outputs cycle-cycle jitter < 125ps 3V66 outputs cycle-cycle jitter < 250ps PCI outputs cycle-cycle jitter < 250ps CPU outputs skew: < 100ps +/- 300ppm frequency accuracy on CPU & SRC clocks Features/Benefits: Supports tight ppm accuracy clocks for Serial-ATA Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread Supports CPU clks up to 400MHz in test mode Uses external 14.318MHz crystal 56-pin SSOP & TSSOP REF0 1 56 FS_B REF1 2 55 VDDA VDDREF 3 54 GNDA X1 4 53 GND X2 5 52 IREF GND 6 51 FS_A PCICLK_F0 7 50 CPUCLKT3 PCICLK_F1 8 49 CPUCLKC3 PCICLK_F2 9 48 VDDCPU VDDPCI 10 47 CPUCLKT2 GND 11 46 CPUCLKC2 PCICLK0 12 45 GND PCICLK1 13 44 CPUCLKT1 PCICLK2 14 43 CPUCLKC1 PCICLK3 15 42 VDDCPU VDDPCI 16 41 CPUCLKT0 GND 17 40 CPUCLKC0 PCICLK4 18 39 GND PCICLK5 19 38 SRCCLKT PCICLK6 20 37 SRCCLKC PD# 21 36 VDD 3V66_0 22 35 Vtt_PWRGD# 3V66_1 23 34 VDD48 VDD3V66 24 33 GND GND 25 32 48MHz_DOT 3V66_2 26 31 48MHz_USB 3V66_3 27 30 SDATA SCLK 28 29 3V66_4/VCH ICS932S208 Functionality B6b5 FS_A FS_B CPU MHz SRC MHz 3V66 MHz PCI MHz REF MHz USB/DOT MHz 0 0 100 100/200 66.66 33.33 14.318 48.00

0 MID Ref/N 0 Ref/N1 Ref/N2 Ref/N3 Ref/N4 Ref/N5

0 1 200 100/200 66.66 33.33 14.318 48.00 1 0 133 100/200 66.66 33.33 14.318 48.00 1 1 166 100/200 66.66 33.33 14.318 48.00

1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

0 0 200 100/200 66.66 33.33 14.318 48.00 0 1 400 100/200 66.66 33.33 14.318 48.00 1 0 266 100/200 66.66 33.33 14.318 48.00 1 1 333 100/200 66.66 33.33 14.318 48.00

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 REF0 OUT 14.318 MHz reference clock. 2 REF1 OUT 14.318 MHz reference clock.

3 VDDREF PWR Ref, XTAL

power supply, nominal 3.3V 4X 1 I N C r ystal input, Nominally 14.318MHz. 5 X2 OUT Cr ystal output, Nominally 14.318MHz 6 GND PWR Ground pin. 7 PCICLK_F0 OUT Free runnin g PCI clock not affected by PCI_STOP# . 8 PCICLK_F1 OUT Free runnin g PCI clock not affected by PCI_STOP# . 9 PCICLK_F2 OUT Free runnin g PCI clock not affected by PCI_STOP# . 10 VDDPCI PWR Power su pply for PCI clocks, nominal 3.3V 11 GND PWR Ground pin. 12 PCICLK0 OUT PCI clock out put. 13 PCICLK1 OUT PCI clock out put. 14 PCICLK2 OUT PCI clock out put. 15 PCICLK3 OUT PCI clock out put. 16 VDDPCI PWR Power su pply for PCI clocks, nominal 3.3V 17 GND PWR Ground pin. 18 PCICLK4 OUT PCI clock out put. 19 PCICLK5 OUT PCI clock out put. 20 PCICLK6 OUT PCI clock out put.

21 PD# IN

Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nominal. 22 3V66_0 OUT 3.3V 66.66MHz clock out put 23 3V66_1 OUT 3.3V 66.66MHz clock out put 24 VDD3V66 PWR Power pin for the 3V66 clocks. 25 GND PWR Ground pin. 26 3V66_2 OUT 3.3V 66.66MHz clock out put 27 3V66_3 OUT 3.3V 66.66MHz clock out put

28 SCLK IN Clock pin of I2C circuitry 5V tolerant

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description (continued) PIN # PIN NAME PIN TYPE DESCRIPTION 29 3V66_4/VCH OUT 66.66MHz clock output for AGP support. AGP-PCI should be aligned with a skew window tolerance of 500ps. VCH is 48MHz clock out put for video controller hub.

30 SDATA I/O Data pin for I2C circuitry 5V tolerant

31 48MHz_USB OUT 48MHz clock out put. 32 48MHz_DOT OUT 48MHz clock out put. 33 GND PWR Ground pin. 34 VDD48 PWR Power pin for the 48MHz output.3.3V

35 Vtt_PWRGD# IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. 36 VDD PWR Power su pply for SRC clocks, nominal 3.3V 37 SRCCLKC OUT Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. 38 SRCCLKT OUT True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. 39 GND PWR Ground pin. 40 CPUCLKC0 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 41 CPUCLKT0 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 42 VDDCPU PWR Su pply for CPU clocks, 3.3V nominal 43 CPUCLKC1 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 44 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 45 GND PWR Ground pin. 46 CPUCLKC2 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 47 CPUCLKT2 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 48 VDDCPU PWR Su pply for CPU clocks, 3.3V nominal 49 CPUCLKC3 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 50 CPUCLKT3 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias.

51 FS_A IN Fre quency select pin, see Frequency table for functionality

52 IREF OUT

This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 53 GND PWR Ground pin. 54 GNDA PWR Ground pin for core. 55 VDDA PWR 3.3V power for the PLL core.

56 FS_B IN Frequency select pin, see Frequency table for functionality

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor General Description Block Diagram Power Groups ICS932S208 follows Intel CK409B Y ellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS932S208 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support. I REF PLL2 Frequency Dividers Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic 48MHz, USB, DOT X2 XTAL SDATA SCLK Vtt_PWRGD# PD# FS_A FS_B Control Logic REF (1:0) CPUCLKT (3:0) CPUCLKC (3:0) SRCCLKT0 SRCCLKC0 3V66(4:0) PCICLK (6:0) PCICLKF (2:0) VDD GND 3 6 Xtal, Ref 24 25 3V66 [0:3] 10,16 11,17 PCICLK outputs 36 39 SRCCLK outputs 55 54 Master clock, CPU Analog 34 33 48MHz, PLL N/A 53 IREF 48, 42 45 CPUCLK clocks DescriptionPin Number

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Absolute Maximum Ratings Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage V DD + 0.5V V VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 V DD + 0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient Operating Temp 0 70 °C Tcase Case Temperature 115 °C ESD prot Input ESD protection human body model 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V Input MID Voltage VMID 3.3 V +/-5% 1 1.8 V Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V Input High Current IIH VIN = VDD -5 5 uA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 uA IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA Operating Supply Current IDD3.3OP Full Active, CL = Full load; 350 mA all diff pairs driven 35 mA all differential pairs tri-stated 12 mA Input Frequency3 Fi VDD = 3.3 V 14.31818 MHz 3 Pin Inductance1 Lpin 7n H 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization1,2 TSTAB From VDD Power-Up or de- assertion of PD# to 1st clock 1.8 ms 1,2 Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_SRC SRC output enable after PCI_Stop# de-assertion 15 ns 1 Tdrive_PD# CPU output enable after PD# de-assertion 300 us 1 Tfall_Pd# PD# fall time of 5 ns 1 Trise_Pd# PD# rise time of 5 ns 2 Tdrive_CPU_Stop# CPU output enable after CPU_Stop# de-assertion 10 us 1 Tfall_CPU_Stop# PD# fall time of 5 ns 1 Trise_CPU_Stop# PD# rise time of 5 ns 2 1Guaranteed by design, not 100% tested in production. 2See timing diagrams for timing requirements. IDD3.3PD 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. Input Capacitance1 Input Low Current Powerdown Current

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo1 VO = Vx 3000 Ω 1 Output High Voltage VOH3 IOH = -1 mA 2.4 V Output Low Voltage VOL3 IOL = 1 mA 0.4 Voltage High VHigh 660 850 1 Voltage Low VLow -150 150 1 Max VoltageV o v s 1 1 5 0 1 Min Voltage Vuds -300 1 Crossing Voltage (abs) Vcross (abs) 250 550 mV 1 Crossing Voltage (var) d-Vcross Variation of crossing over all edges 140 mV 1 Long Accuracy ppms e e T period min-max values -300 300 ppm1 , 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 5.4000 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 200MHz nominal 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr 125 ps 1 Fall Time Variation d-tf 125 ps 1 Duty Cycle dt3 Measurement from differential wavefrom 45 55 % 1 Skew tsk3 VT = 50% 100 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 125 ps 1 1Guaranteed by design, not 100% tested in production. SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair. Statistical measurement on single ended signal using oscilloscope math function. mV Measurement on single ended signal using absolute value. mV 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz TperiodAverage period Absolute min period Tabsmin

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 3V66 Mode: 3V66 [4:0] TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppms e e T period min-max values -300 300 ppm1 , 2 66.66MHz output nominal 14.9955 15.0045 ns 2 66.66MHz output spread 14.9955 15.0799 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V Output Low Voltage VOL IOL = 1 mA 0.55 V V OH @ MIN = 1.0 V -33 mA VOH @ MAX = 3.135 V -33 mA VOL @ MIN = 1.95 V 30 mA VOL @ MAX = 0.4 V 38 mA Edge Rate Risin g edge rate 1 4 V/ns 1 Edge Rate Fallin g edge rate 1 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Skew tsk1 VT = 1.5 V 250 ps 1 Jitter tjcyc-cyc VT = 1.5 V 3V66 250 ps 1 1Guaranteed by design, not 100% tested in production. Clock period Tperiod 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Output High Current IOH Output Low Current IOL Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppms e e T period min-max values -300 300 ppm1 , 2 33.33MHz output nominal 29.9910 30.0090 ns 2 33.33MHz output spread 29.9910 30.1598 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V Output Low Voltage VOL IOL = 1 mA 0.55 V V OH @MIN = 1.0 V -33 mA VOH@ MAX = 3.135 V -33 mA VOL @ MIN = 1.95 V 30 mA VOL @ MAX = 0.4 V 38 mA Edge Rate Rising edge rate 1 4 V/ns 1 Edge Rate Fallin g edge rate 1 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Skew tsk1 VT = 1.5 V 500 ps 1 Jitter tjcyc-cyc VT = 1.5 V 3V66 250 ps 1 1Guaranteed by design, not 100% tested in production. Clock period Tperiod 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Output High Current IOH Output Low Current IOL

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -200 200 ppm 1,2 Clock period Tperiod 66.66MHz output nominal 20.8257 20.8340 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V Output Low Voltage VOL IOL = 1 mA 0.55 V V OH @ MIN = 1.0 V -33 mA VOH @ MAX = 3.135 V -33 mA VOL @ MIN = 1.95 V 30 mA VOL @ MAX = 0.4 V 38 mA Edge Rate Risin g edge rate 2 4 V/ns 1 Edge Rate Falling edge rate 2 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Long Term Jitter 125us period jitter (8kHz frequency modulation amplitude) 2n s 1 1Guaranteed by design, not 100% tested in production. TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified) Electrical Characteristics - 48MHz DOT Clock

2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref

output is at 14.31818MHz Output High Current IOH Output Low Current IOL

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - VCH, 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppms e e T period min-max values -200 200 ppm1 , 2 Clock period Tperiod 66.66MHz output nominal 20.8257 20.8340 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V Output Low Voltage VOL IOL = 1 mA 0.55 V V OH @ MIN = 1.0 V -33 mA VOH@ MAX = 3.135 V -33 mA VOL @MIN = 1.95 V 30 mA VOL @ MAX = 0.4 V 38 mA Edge Rate Risin g edge rate 1 2 V/ns 1 Edge Rate Falling edge rate 1 2 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 12 n s 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 12 n s 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Long Term Jitter 125us period jitter (8kHz frequency modulation amplitude) 6n s 1 1Guaranteed by design, not 100% tested in production. Output Low Current IOL 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Output High Current IOH

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Long Accuracy ppm1 see Tperiod min-max values -300 300 ppm Clock period Tperiod 14.318MHz output nominal 69.8270 69.8550 ns Output High Voltage VOH 1 IOH = -1 mA 2.4 V Output Low Voltage VOL 1 IOL = 1 mA 0.4 V Output High Current IOH 1 V OH @MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA Rise Time tr1 1 VOL = 0.4 V, VOH = 2.4 V 12 n s Fall Time tf1 1 VOH = 2.4 V, VOL = 0.4 V 12 n s Skew tsk1 1 VT = 1.5 V 500 ps Duty Cycle dt1 1 VT = 1.5 V 45 55 % Jitter tjcyc-cyc 1 VT = 1.5 V 1000 ps 1Guaranteed by design, not 100% tested in production. Group to Group Skews at Common Transition Edges GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS 200MHZ CPU to 3V661 SCPU200-3V66 3V66 (4:0) leads 200MHZ 3V66 to PCI S3V66-PCI 3V66 (4:0) leads 33MHz PCI 1.50 3.50 ns DOT-USB SDOT_USB 180 degrees out of phase 0.00 1.00 ns DOT-VCH SDOT_VCH in phase 0.00 1.00 ns 1. 3V66 MHz CL = 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms. Measured at the pins of the 932S208.

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor General I 2C serial interface information for the ICS932S208 How to Write:

Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit ICS (Slave/Receiver) T WR ACK ACK ACK ACK ACK P stoP bit X Byte Index Block Write Operation Slave Address D2(H) Beginning Byte = N WRite starT bit Controller (Host) Byte N + X - 1 Data Byte Count = X Beginning Byte N T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge Ps t o P b i t Slave Address D3(H) Index Block Read Operation Slave Address D2(H) Beginning Byte = N ACK ACK Data Byte Count = X ACK ICS (Slave/Receiver)Controller (Host) X Byte ACK ACK

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor I2C Table: Read-Back Register Pin # Name Control Function T ype0 1 P W D Bit 7 RESERVED RESERVED - X Bit 6 RESERVED RESERVED - X Bit 5 RESERVED RESERVED - X Bit 4 RESERVED RESERVED - X Bit 3 RESERVED RESERVED - X Bit 2 RESERVED RESERVED - X Bit 1 FSB Freq Select 1 Read Back RX Bit 0 FSA Freq Select 0 Read Back RX I2C Table: Spreading and Device Behavior Control Register Pin # Name Control Function T ype0 1 P W D Bit 7 SRC/SRC# SRC Free-Running Control RW FREE-RUN STOPPABLE 0 Bit 6 SRC Output Control RW Disable Enable 1 Bit 5 RESERVED RESERVED - X Bit 4 RESERVED RESERVED - X Bit 3 RESERVED RESERVED - X Bit 2 CPUT2/CPUC2 Output Control RW Disable Enable 1 Bit 1 CPUT1/CPUC1 Output Control RW Disable Enable 1 Bit 0 CPUT0/CPUC0 Output Enable RW Disable Enable 1 I2C Table: Output Control Register Pin # Name Control Function T ype0 1 P W D Bit 7 SRC_PD# Drive Mode 0: Driven in PD# RW Driven Hi-Z 0 Bit 6 SRC_Stop# Drive Mode 0: Driven in PCI_Stop# RW Driven Hi-Z 0 Bit 5 CPUT2_PD# Drive Mode RW Driven Hi-Z 0 Bit 4 CPUT1_PD# Drive Mode RW Driven Hi-Z 0 Bit 3 CPUT0_PD# Drive Mode RW Driven Hi-Z 0 Bit 2 RESERVED RESERVED - X Bit 1 RESERVED RESERVED - X Bit 0 RESERVED RESERVED - X 41, 40 47, 46 47, 46 44, 43 38, 37 38, 37 44, 43 41, 40 Byte 2 38, 37 38, 37 Byte 0 RESERVED RESERVED - RESERVED RESERVED 0:driven in PD# 1: Tri-stated RESERVED READBACK of CPU(3:0) Frequency RESERVED Byte 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor I2C Table: Output Control Register Pin # Name Control Function T ype0 1 P W D Bit 7 PCI_Stop# PCI_Stop# Control 0:all stoppable PCI are stopped RW Enable Disable 1 Bit 6 PCICLK6 Output Control RW Disable Enable 1 Bit 5 PCICLK5 Out put Control RW Disable Enable 1 Bit 4 PCICLK4 Out put Control RW Disable Enable 1 Bit 3 PCICLK3 Out put Control RW Disable Enable 1 Bit 2 PCICLK2 Output Control RW Disable Enable 1 Bit 1 PCICLK1 Output Control RW Disable Enable 1 Bit 0 PCICLK0 Output Control RW Disable Enable 1 I2C Table: Output Control Register Pin # Name Control Function T ype0 1 P W D Bit 7 48MHz_USB 2x output drive 0=2x drive RW 2x drive normal 1 Bit 6 48MHz_USB Output Control RW Disable Enable 1 Bit 5 PCIF2 RW FREE-RUN STOPPABLE 0 Bit 4 PCIF1 RW FREE-RUN STOPPABLE 0 Bit 3 PCIF0 RW FREE-RUN STOPPABLE 0 Bit 2 PCICLK_F2 Output Control RW Disable Enable 1 Bit 1 PCICLK_F1 Output Control RW Disable Enable 1 Bit 0 PCICLK_F0 Output Control RW Disable Enable 1 I2C Table: Output Control Register Pin # Name Control Function T ype0 1 P W D Bit 7 48MHZ_DOT Output Control RW Disable Enable 1 Bit 6 CPUT3/CPUC3 Output Control RW Disable Enable 1 Bit 5 3V66_4/VCH Select Output Select RW 3V66 VCH 0 Bit 4 3V66_4/VCH Output Control RW Disable Enable 1 Bit 3 3V66_3 Output Control RW Disable Enable 1 Bit 2 3V66_2 Output Control RW Disable Enable 1 Bit 1 3V66_1 Output Control RW Disable Enable 1 Bit 0 3V66_0 Output Control RW Disable Enable 1 Byte 5 Byte 3 7,8,9,12,13,14,15, 18,19,20,37,38,

8 PCI FREE-RUN

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor I2C Table: Output Control and Fix Frequency Register Pin # Name Control Function T ype0 1 P W D Bit 7 Test Clock Mode Test Clock Mode RW Disable Enable 0 Bit 6 RESERVED - - - - 0 Bit 5 FS Testmode FS_A and FS_B Operation RW Normal Test Mode 0 Bit 4 SRC100# SRC Frequency Select RW 100MHz 200MHz 0 Bit 3 RESERVED - - - - 0 Bit 2 SSEN Spread Spectrum Enable RW Spread OFF Spread ON 0 Bit 1 REF1 Output Control RW Disable Enable 1 Bit 0 REF0 Output Control RW Disable Enable 1 I2C Table: Vendor & Revision ID Register Pin # Name Control Function T ype0 1 P W D Bit 7 RID3 R - - X Bit 6 RID2 R - - X Bit 5 RID1 R - - X Bit 4 RID0 R - - X Bit 3 VID3 R - - 0 Bit 2 VID2 R - - 0 Bit 1 VID1 R - - 0 Bit 0 VID0 R - - 1 VENDOR ID- Byte 7 REVISION ID- 37,38 41,43,44,46,47 40,41,43,44,46,47 ,40,41,43,44,46,47 B yte 6

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the PCI_STOP register bit. PCI Stop Functionality #POTS_ICPU PC# UPCC RS# CRS6 6V3I CP/FICPT OD/BSUF ERe toN 1l amroNl amroNl amroNl amroNz HM66z HM33z HM84z HM813.41 0l amroNl amroN6 *ferI taolFro woLz HM66w oLz HM84z HM813.41 The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched l ow, the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below. PCI_STOP# Tsu PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz PCI_STOP# Assertion (transition from '1' to '0') The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free manner. PCI_STOP# Tsu Tdrive_SRC PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz PCI_STOP# - De-assertion

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches. PD#, Power Down #NWDRWPU PC# UPCC RS# CRS6 6V3I CP/FICPT OD/BSUF ERe toN 1l amroNl amroNl amroNl amroNz HM66z HM33z HM84z HM813.41 0r o2*ferI taolF taolF2 *ferI taolFro taolFw oLw oLw oLw oL Notes: 1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation. 2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses. PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control registe r determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be trista ted. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 PD# Assertion

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300 µs of PD# deassertion. PWRDWN# Tstable <1.8mS Tdrive_PwrDwn# <300µS, >200mV CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC# 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 PD# De-assertion The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is 3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The outp ut will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising edge of DOT_48 clock. 3V66 3V66_4/VCH DOT_48 7.49nS min 3V66_4/VCH Pin Functionality

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop", "SRC_Stop" and "PwrDwn" register bit settings. langiS# DPniPn iP #potS_UPC potS_UPC tiBetatsirT nwdrwP tiBetatsirT elbappotS-noN stuptuO elbappotS stuptuO }0:2[UPC1 1 X X g ninnuRg ninnuR }0:2[UPC1 0 0 Xg ninnuR6 xferI@nevirD }0:2[UPC1 0 1 X g ninnuRe tatsirT }0:2[UPC0 X X 0 2 xferI@nevirD2 xferI@nevirD }0:2[UPC0 X X 1 e tatsirTe tatsirT Notes: 1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running" 2. Iref x 6 and Iref x 2 is the output current in the corresponding mode 3. See Control Registers section for bit address langiS# DPniPn iP #potS_ICP potS_ICP tiBetatsirT nwdrwP tiBetatsirT elbappotS-noN tuptuO elbappotS tuptuO CRS1 1 X X g ninnuRg ninnuR CRS1 0 0 Xg ninnuR6 xferI@nevirD CRS1 01 X g ninnuRe tatsirT CRS0 XX 0 2 xferI@nevirD2 xferI@nevirD CRS0 XX1 e tatsirTe tatsirT Notes: 1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running" 2. Iref x 6 and Iref x 2 is the output current in the corresponding mode 3. See Control Registers section for bit address Differential Clock Tristate

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor

Ordering Information

A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N a 0 °8 °0 °8 ° VARIATIONS MIN MAX MIN MAX 56 18.31 18.55 .720 .730 10-0034 0.635 BASIC 0.025 BASIC COMMON DIMENSIONS In Millimeters In Inches COMMON DIMENSIONS Reference Doc.: JEDEC Publication 95, MO-118 N SEE VARIATIONS SEE VARIATIONS D mm. D (inch) SYMBOL SEE VARIATIONS SEE VARIATIONS INDEX AREA INDEX AREA 1 2 N D h x 45° E1 E α SEATING PLANE SEATING PLANE A e - C - b c L Example: Designation for tape and reel packaging Annealed Lead Free Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type XXXX y F LN T

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor 0743G—01/26/10 ICS932S208 Programmable Timing Control HubTM for Next Gen P4TM Processor A -- 1.20 -- .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e L 0.45 0.75 .018 .030 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 13.90 14.10 .547 .555 10-0039 N D mm. D (inch) Reference Doc.: JEDEC Publication 95, MO-153 0.50 BASIC 0.020 BASIC SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS INDEX AREA INDEX AREA 121 2 N D E1 E /c97 SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C Example: Designation for tape and reel packaging Annealed Lead Free Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type XXXX y G LN T

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Revision History

Rev. Issue Date Description Page # F 12/2/2008 Removed ICS prefix from ordering information 12-20 G 1/26/2010 Updated document template

Product Information

932S208YFLNT specifications and overview.

Summary

Programmable Timing Control HubTM for Next Gen P4TM Processor

Description

Programmable Timing Control HubTM for Next Gen P4TM Processor

Source title 932S208YFLNT Datasheet(PDF) - Integrated Device Technology

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