932S203YFLXT

ICS932S203 RENESAS | Alldatasheet

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IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 Frequency Generator with 133MHz Differential CPU Clocks DATASHEET Pin ConfigurationRecommended Application: Servers based on Intel CK408 processors Output Features:

• 4 Differential CPU Clock Pairs @ 3.3V  7 PCI (3.3V) @ 33.3MHz  3 PCI_F (3.3V) @ 33.3MHz  1 USB (3.3V) @ 48MHz  1 DOT (3.3V) @ 48MHz  1 REF (3.3V) @ 14.318MHz  1 3V66 (3.3V) @ 66.6MHz  1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz  3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz  1 66MHz_IN/3V66 (3.3V) @ Input/66MHz Features:  Supports spread spectrum modulation, down spread 0 to -0.5%.  Efficient power management scheme through PD# and PCI_STOP#.  Uses external 14.318MHz crystal  Stop clocks and functional control available through SMBus interface. Key Specifications:
• CPU Output Jitter <150ps  3V66 Output Jitter <250ps  CPU Output Skew <150ps 56-Pin 300mil SSOP/TSSOP * These inputs have 150K internal pull-up resistor to VDD. Block Diagram Functionality

1 SF0 S F U P C

) z H M ( 6 6 V 3 ) z H M ( ] 0 : 2 [ f f u B 6 6 ] 2 : 4 [ 6 6 V 3 ) z H M ( F _ I C P I C P ) z H M ( 10 0 016 . 66h t a p n I 6 . 662 / n i 6 . 6 6 11 3 . 3 316 . 66h t a p n I . 662 / n i 6 . 6 6 00 0016 . 666 . 663 . 3 3 01 3 . 3 316 . 666 . 663 . 3 3 d im0 Z - iHZ - iHZ - iHZ - i H d im1 2 / k l cT4 / k l cT4 / k l cT8 / k l c T

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Pin Description R E B M U N N IPE M A N N IPE P YTN O I T P I R C S E D , 6 2 , 9 1 , 4 1 , 8 , 1 0 5 , 6 4 , 7 3 , 2 3D DVR WPy l p p u s r e w o p V 3 . 3 21 Xt u p n I l a t s y r C 2Xt u p n i l a t s y r C z H M 8 1 3 . 4 1

32 X l a t s y r C 1 X

t u p t u O t u p t u ol a t s y r C z H M 8 1 3 . 4 1 5 , 6 ,7) 0 : 2 ( F _ K L C I CPT U O . t n e m e g a n a m r e w o p r o f # P O T S _ I C P y b d e t c e f f a t o n k c o l c I C P g n i n n u r e e r F , 7 2 , 0 2 , 5 1 , 9 , 4 7 4 , 1 4 , 6 3 , 1 3D NGR WPy l p p u s V 3 . 3 r o f s n i p d n u o r G , 3 1 , 6 1 , 7 1 , 8 1 0 1 , 1 1 , 2 1 ) 0 : 6 ( K L C I CPT UOs t u p t u o k c o l c I C P 1 2 , 2 2 , 3 2 )0 : 2 ( T U O _ z H M 66T UO. t u p n i N I _ z H M 6 6 m o r f T U O _ z H M 6 6 d e r e f f u b z H M 6 6 ) 2 : 4 ( 6 6 V3T UOO C V l a n r e t n i m o r f , s k c o l c e c n e r e f e r z H M 6 6 4 2 N I _ z H M 66N Is k c o l c I C P d n a T U O _ z H M 6 6 d e r e f f u b o t t u p n i z H M 6 6 5 _ 6 6 V3T UOO C V l a n r e t n i m o r f , k c o l c e c n e r e f e r z H M 6 6 52# DPN I. w o L e v i t c A . e d o m n w o d - r e w o p s e k o v n I 82# D G R W P _ t t VN I e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i L T T V L V 3 . 3 s i h T e b o t y d a e r e r a d n a d i l a v e r a s t u p n i 0 L E S I T L U M d n a ] 2 : 0 [ S F n e h w d e l p m a s ) w o l e v i t c a ( 92A T A D S O / I t n a r e l o t V 5 y r t i u c r i c s u B M S r o f n i p a t a D 03K L C S N I t n a r e l o t V 5 y r t i u c r i c s u B M S f o n i p k c o l C 330 _ 6 6 V3T UOO C V l a n r e t n i m o r f , s k c o l c e c n e r e f e r z H M 6 6 43# P O T S _ I CPN I t p e c x e w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c K L C I C P s t l a H g n i n n u r e e r f e r a h c i h w F _ K L C I C P 53K L C _ H C V / 1 _ 6 6 V3T U O h g u o r h t e l b a t c e l e s t u p t u o V 3 . 3I2C r o O C V l a n r e t n i m o r f z H M 6 6 e b o t ) C S S - n o n ( z H M 8 4 83T O D _ z H M 84T UOT O D r o f k c o l c t u p t u o z H M 8 4 93B S U _ z H M 84T UOB S U r o f k c o l c t u p t u o z H M 8 4 5 5 , 04) 0 : 1 ( SFN In o i t c e l e s e d o M r o f t u p n i V 3 . 3 l a i c e p S 24F E RIT U O n i p s i h T . s r i a p K L C U P C e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h T e h t h s i l b a t s e o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p d e x i f a s e r i u q e r . t n e r r u c e t a i r p o r p p a 340 L E S T L UMN I o t r o i r p d e h c t a l y l l a n r e t n i n e h t d n a p u - r e w o p n o d e s n e s s i t u p n i 0 L E S T L U M . s k c o l c z H M 8 1 3 . 4 1 V 3 n o t u p t u o r o f d e s u g n i e b n i p e h t 3 5 , 1 5 , 8 4 , 44) 0 : 3 ( C K L C U PCT U O t n e r r u c e r a e s e h T . s t u p t u o U P C r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o C " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o 4 5 , 2 5 , 9 4 , 54) 0 : 3 ( T K L C U PCT U O d n a s t u p t u o t n e r r u c e r a e s eh T . s t u p t u o U P C r i a p l a i t n e r e f f i d f o s k c o l c " e u r T " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e 65F ERT UO. k c o l c e c n er e f e r z H M 8 1 3 . 4 1 Power Groups (Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Frequency Select Table Host Swing Select Functions

0 L E S I T L U M t e g r a T d r a o B

, R e c n e r e f e R = f e r I V D D ) r R * 3 ( / t u p t u O t n e r r u C Z @ h o V 0s m h o 0 5 , % 1 1 2 2 = r R A m 0 0 . 5 = f e r I F E R I * 4 = h oI0 5 @ V 0 . 1 1s m h o 0 5 , % 1 5 7 4 = r R A m 2 3 . 2 = f e r I F E R I * 6 = h oI0 5 @ V 7 . 0 FS1 FS0 CPU 3V66 (1:0) 66Buff (2:0) / 3V66 (4:2)

66 In /

3V66_5 PCI REF USB, DOT note mode 66 mode 66 mid1 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Tri-state outputs mid1 1 Tclk/2 Tclk/4 Tclk/4 Tclk/4 Tclk/8 Tclk Tclk/2 Tclk is at X1 input

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Byte 0: Control Register Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via SMBus Byte 0 Bit 3. In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY , it is not allowed to mix these modes. In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)]. Byte 1: Control Register t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iB- 1 )d e v r e s e R ( 1 t iB5 50 SFX R pu r e w o p n o d e l p m a s n i p 0 S F f o e u l a v e h t s t c e l f e R 2 t iB0 41 SFX R pu r e w o p n o d e l p m a s n i p 1 S F f o e u l a v e h t s t c e l f e R 3 t iB4 3# P O T S _ I C P3 XR # P O T S _ I C P f o e u l a v e h t s t c e l f e R : e d o m e r a w d r a H D W P n o d e l p m a s n i p 4 t iB- 1 )d e v r e s e R ( 5 t iB5 3H C V / 1 _ 6 6 V30 W R z H M 8 4 / z H M 6 6 t c e l e S H C V z H M 8 4 = 1 , z H M 6 6 = 0 6 t iB- 0 )d e v r e s e R ( 7 t iB- d a e r p S d e l b a n E0W Rn O d a e r p S = 1 , f f O d a e r p S = 0 t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iB1 5 , 2 5 0 T K L C U P C

0 C K L C U P C1W Rd e l b a n E = 1 d e l b a s i D = 0

1 t iB8 4 , 9 4 1 T K L C U P C

1 C K L C U P C1W Rd e l b a n E = 1 d e l b a s i D = 0

2 t iB4 4 , 5 4 2 T K L C U P C

2 C K L C U P C1W Rd e l b a n E = 1 d e l b a s i D = 0

3 t iB1 5 , 250 - de v r e s e R 4 t iB8 4 , 940 - de v r e s e R 5 t iB4 4 , 540 - de v r e s e R 6 t iB4 5 , 3 5 3 T K L C U P C

3 C K L C U P C1W Rd e l b a n E = 1 d e l b a s i D = 0

R 0L E S T L U M f o e u l a v t n e r r u c e h t s t c e l f e R

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Byte 2: Control Register Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iB0 10 K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 1 t iB1 11 K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 2 t iB2 12 K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 3 t iB3 13 K L C I CP1 WRd e l b a n E = 1 d e l b a s i D = 0 4 t iB6 14 K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 5 t iB7 15 K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 6 t iB8 16 K L C I CP1 WRd e l b a n E = 1 d e l b a s i D = 0 7 t iB- - 0 - ) d e v r e s e R ( Byte 3: Control Register Byte 4: Control Register t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iB1 22 - 6 6 V 3 / 0 T U O _ z H M 661 WRd e l b a n E = 1 d e l b a s i D = 0 1 t iB2 23 - 6 6 V 3 / 0 T U O _ z H M 661 WRd e l b a n E = 1 d e l b a s i D = 0 2 t iB3 24 - 6 6 V 3 / 0 T U O _ z H M 661 WRd e l b a n E = 1 d e l b a s i D = 0 3 t iB4 25 _ 6 6 V31 W Rd e l b a n E = 1 d e l b a s i D = 0 4 t iB5 3K L C _ H C V / 1 _ 6 6 V31 WRd e l b a n E = 1 d e l b a s i D = 0 5 t iB3 30 _ 6 6 V31 WRd e l b a n E = 1 d e l b a s i D = 0 6 t iB- - 0 R ) d e v r e s e R ( 7 t iB- - 0 R ) d e v r e s e R ( t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iB5 0 F _ K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 1 t iB6 1 F _ K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 2 t iB7 2 F _ K L C I CP1 W Rd e l b a n E = 1 d e l b a s i D = 0 3 t iB5 0F _ K L C I CP0 W R f o n o i t r e s s a h t i w 0 F _ K L C I C P f o l o r t n o c w o l l A g n i n n u r e e r f t o N = 1 , g n i n n u R e e r F = 0 . # P O T S _ I C P 4 t iB6 1F _ K L C I CP0 W R f o n o i t r e s s a h t i w 1 F _ K L C I C P f o l o r t n o c w o l l A g n i n n u r e e r f t o N = 1 , g n i n n u R e e r F = 0 . # P O T S _ I C P 5 t iB7 2 F _ K L C I CP0 WR f o n o i t r e s s a h t i w 2 F _ K L C I C P f o l o r t n o c w o l l A g n i n n u r e e r f t o N = 1 , g n i n n u R e e r F = 0 . # P O T S _ I C P 6 t iB9 3B S U _ z H M 841 W Rd e l b a n E = 1 d e l b a s i D = 0 7 t iB8 3T O D _ z H M 841 WRd e l b a n E = 1 d e l b a s i D = 0

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Byte 6: Vendor ID Register (1 = enable, 0 = disable) t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iBX 0t i B D I r o d n eV1 R ) d e v r e s e R ( 1 t iBX 1t i B D I r o d n eV0 R ) d e v r e s e R ( 2 t iBX 2t i B D I r o d n eV0 R ) d e v r e s e R ( 3 t iBX 3t i B D I r o d n eV0 R ) d e v r e s e R ( 4 t iBX 0t i B D I n o i s i v eRX R n o d e s a b e b l l i w s e u l a v D I n o i s i v e R n o i s i v e r s ' e c i v e d l a u d i v i d n i5 t iBX 1t i B D I n o i s i v eRX R 6 t iBX 2t i B D I n o i s i v eRX R 7 t iBX 3t i B D I n o i s i v eRX R Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default t iB# n iPe m aND WPe p yTn o i t p i r c s e D 0 t iBX B S U _ z H M 840 W Rl o r t n c e t a r e g d e B S U 1 t iBX B S U _ z H M 840 W Rl o r t n c e t a r e g d e B S U 2 t iBX T O D _ z H M 840 W Rl o r t n o c e t a r e g d e T O D 3 t iBX TO D _ z H M 840 W Rl o r t n o c e t a r e g d e T O D 4 t iBX - 0 - ) d e v r e s e R ( 5 t iBX - 0 - ) d e v r e s e R ( 6 t iBX - 0 - ) d e v r e s e R ( 7 t iBX - 0 - ) d e v r e s e R (

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Absolute Maximum Ratings Supply Voltage 5.5 V Logic Inputs GND –0.5 V to VDD +0.5 V Ambient Operating Temperature 0°C to +70°C Case Temperature 115°C Storage Temperature –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2V DD + 0.3 V Input Low Voltage V IL VSS - 0.3 0.8 V Input High Current I IH VIN = VDD -5 5 mA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA IIL2 VIN = 0 V; Inputs with pull-up resistors -200 Operating Supply Current I DD3.3OP CL = Full load; Select @ 100 MHz 229 230 360 mA IDD3.3OP CL =Full load; Select @ 133 MHz 220 233 360 mA Powerdown Current I DD3.3PD 60 mA Input Frequency F i VDD = 3.3 V 14.318 MHz Pin Inductance L pin 7n H CIN Logic Inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 27 45 pF Transition time1 Ttrans To 1st crossing of target frequency 3 ms Settling time1 Ts From 1st crossing to 1% target frequency 3 ms Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target frequency 3 ms tPZH,tPZL Output enable delay (all outputs) 1 10 ns tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns 1Guaranteed by design, not 100% tested in production. Delay1 Input Capacitance1 Input Low Current

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo1 VO = Vx 3000 Ω 1 Voltage High VHigh 660 770 850 1 Voltage Low VLow -150 5 150 1 Max Voltage Vovs 756 1150 1 Min Voltage Vuds -300 -7 1 Crossing Voltage (abs) Vcross (abs) 250 350 550 mV 1 Crossing Voltage (var) d-Vcross Variation of crossing over all edges 12 140 mV 1 Long Accuracy ppm see T period min-max values -300 300 ppm1 , 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 5.4000 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 200MHz nominal 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 332 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 344 700 ps 1 Rise Time Variation d-tr 30 125 ps 1 Fall Time Variation d-tf 30 125 ps 1 Duty Cycle dt3 Measurement from differential wavefrom 45 49 55 % 1 Skew tsk3 VT = 50% 8 100 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 60 150 ps 1 1Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz TperiodAverage period Absolute min period Tabsmin Statistical measurement on single ended signal using oscilloscope math function. mV Measurement on single ended signal using absolute value. mV

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Electrical Characteristics - PCICLK Un-Buffered Mode TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 12 33 55 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.55 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA Rise Time tr1 Fall Time tf1 Duty Cycle dt1 1 VT = 1.5 V 45 52 55 % Skew tsk1 1 VT = 1.5 V 247 500 ps Jitter,cycle to cyc tjcyc-cyc 1 VT = 1.5 V 111 500 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK Buffered Mode TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 12 33 55 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.55 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA Rise Time tr1 Fall Time tf1 Duty Cycle dt1 1 VT = 1.5 V 45 51.9 55 % Skew tsk1 1 VT = 1.5 V 209 500 ps Jitter,cycle to cyc tjcyc-cyc 1 VT = 1.5 V 107 500 ps 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0] TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 66.66 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 12 33 55 W Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.55 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA Rise Time tr1 1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.44 2 ns Fall Time tf1 1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.36 2 ns Duty Cycle dt1 1 VT = 1 . 5 V 4 55 4 . 65 5 % Skew tsk1 1 VT = 1.5 V 3V66 [1:0] 105 250 ps Jitter tjcyc-cyc 1 VT = 1.5 V 3V66 [1:0] 121 300 ps Skew tsk1 1 VT = 1.5 V 66MHz_OUT [2:0] 169 250 ps Jitter tjcyc-cyc 1 VT = 1.5 V 66MHz_OUT [2:0] 89 300 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0] TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 66.66 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 12 33 55 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.55 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30 38 mA Rise Time tr1 1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.38 2 ns Fall Time tf1 1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.45 2 ns Duty Cycle dt1 1 VT = 1.5 V 45 54.4 55 % Skew tsk1 1 VT = 1.5 V 90 250 ps Jitter tjcyc-cyc 1 VT = 1.5 V 3V66 128 250 ps 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 20 48 60 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.4 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA Rise Time tr1 1 VOL = 0.4 V, VOH = 2.4 V 1 1.25 2 ns Fall Time tf1 1 VOH = 2.4 V, VOL = 0.4 V 1 1.15 2 ns Duty Cycle dt1 1 VT = 1.5 V 45 53 55 % Jitter tjcyc-cyc 1 VT = 1.5 V 723 1000 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 48 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 20 48 60 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.4 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA 48DOT Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 0.5 0.6 1 ns 48DOT Fall Time t f1 1 VOH = 2.4 V, VOL = 0.4 V 0.5 0.8 1 ns VCH 48 USB Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 1 1.2 2 ns VCH 48 USB Fall Time t f1 1 VOH = 2.4 V, VOL = 0.4 V 1 1.3 2 ns

48 DOT Duty Cycle dt1

1 VT = 1.5 V 45 52.8 55 % VCH 48 USB Duty Cycle dt1 1 VT = 1.5 V 45 53.5 55 %

48 DOT Jitter t jcyc-cyc

1 VT = 1.5 V 183 350 ps VCH Jitter tjcyc-cyc 1 VT = 1.5 V 223 350 ps 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks General SMBus serial interface information The information in this section assumes familiarity with SMBus programming. For more information, contact ICS for an SMBus software program. How to Write:

• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0) through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit 1. The ICS clock generator is a slave/receiver, SMBus component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator SMBus interface, the protocol is set to use only " Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Notes: Controller (Host) ICS (Slave/Receiver) Start Bit Address D2(H ) ACK Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D3(H ) ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit How to Read:

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship betw een 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation value. 66MHz_IN 66MHz_OUT PCICLK_F 3V66 Tpd Tpci No Relationship Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship Group Skews at Common Transition Edges: (Buffered Mode) GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS 3V66 3V66 3V66 (1:0) pin to pin skew 0 500 ps 66MHz_OUT 66OUT 66MHz_OUT (2:0) pin to pin skew 0 175 ps PCI PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0 500 ps 66MHz_IN 66MHz_OUT Tpd Propogation delay from 66MHz_IN to 66MHz_OUT (2:0) 2.5 4.5 ns 66MHz_OUT to PCI Tpci 66MHz_OUT (2:0) leads 33 MHz PCI 1.5 3.5 ns 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. Un-Buffered Mode 3V66 & PCI Phase Relationship 3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci Group Skews at Common Transition Edges: (Un-Buffered Mode) GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS 3V66 3V66 3V66 (5:0) pin to pin skew 0 500 ps PCI PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0 500 ps 3V66 to PCI S3V66-PCI 3V66 (5:0) leads 33MHz PCI 1.5 3.5 ns 1Guaranteed by design, not 100% tested in production. The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz Assertion of PCI_STOP# Waveforms PCI_STOP# - Assertion (transition from logic "1" to logic "0")

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# - Assertion (transition from logic "1" to logic "0") PD# Functionality # P O T S _ U PCT U PCC U PC6 6 V3T U O _ z H M 6 6F _ K L C I C P K L C I C P K L C I C P T O D / B S U z H M 8 4 1l a m r oNl a m r oNz H M 66N I _ z H M 66N I _ z H M 66N I _ z H M 66z H M 8 4 0t l u M * f e rit a o lFw oLw oLw oLw oLw o L Power Down Assertion of Waveforms - Buffered Mode 0ns PD# CPUT 100MHz CPUC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCI 33MHz USB 48MHz REF 14.318MHz 25ns 50ns

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks MIN MAX MIN MAX A 2.413 2.794 .095 .110 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 D E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC 0.025 BASIC h 0.381 0.635 .015 .025 L 0.508 1.016 .020 .040 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 18.288 18.542 .720 .730 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B N D mm. D (inch) SEE VARIATIONS SYMBOL SEE VARIATIONS SEE VARIATIONS In Millimeters COMMON DIMENSIONS In Inches COMMON DIMENSIONS SEE VARIATIONS 300 mil SSOP

Ordering Information

Example: Designation for tape and reel packaging LF or LN = Lead Free, RoSH Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) XXXX y F Lx T

IDTTM Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10 ICS932S203 Frequency Generator with 133MHz Differential CPU Clocks 6.10 mm. Body, 0.50 mm. pitch TSSOP (240 mil) (0.020 mil) MIN MAX MIN MAX A - 1.20 - .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .30 N α 0° 8° 0° 8° aaa - 0.10 - .004 VARIATIONS MIN MAX MIN MAX 56 13.90 14.10 .547 .555 MO-153 JEDEC Doc.# 10-0039 7/6/00 Rev B SYMBOL SEE VARIATIONS SEE VARIATIONS In Millimeters COMMON DIMENSIONS In Inches COMMON DIMENSIONS SEE VARIATIONS 8.10 BASIC 0.319 N D mm. D (inch) SEE VARIATIONS INDEX AREA INDEX AREA 121 N D E1E1 E SEATING PL ANE SEATIN G PL ANE A1A1 AA2A2 e -C--C- b c L aaaaaa C α Example: Designation for tape and reel packaging LF or LN = Lead Free, RoSH Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) XXXX y G Lx T

Frequency Generator with 133MHz Differential CPU Clocks Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc.

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San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G

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#20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2009 Integrated Device Technology , Inc. All rights reserved. Product specifications subject to change without notice. IDT, IC S, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA TM

Revision History

Rev. Issue Date Description Page # F 9/30/2005 1. C orrected Frequency Select Table Typo. i . A dded Foot Note. 2. U pdated LF Ordering Information. 3, 16-17 G 1/26/2010 Update document template

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