932S200YFT

ICS932S200 RENESAS | Alldatasheet

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General Description Features ICS932S200Integrated Circuit Systems, Inc. 0427D—12/15/08 Block Diagram Frequency Timing Generator for Dual Server/Workstation Systems Pin Configuration 56-pin 300 mil SSOP 56-pin 240 mil TSSOP  Generates the following system clocks: - 6 CPU clocks ( 2.5V, 100/133MHz) - 6 PCI clocks, including 1 free running(3.3V, 33MHz) - 3 IOAPIC clocks (2.5V , 16.67MHz) - 2 Fixed frequency 66MHz clocks(3.3V, 66MHz) - 2 REF clocks(3.3V, 14.318MHz) - 1 USB clock (3.3V, 48MHz)  Efficient power management through PD#, CPU_STOP# and PCI_STOP#.  0.5% typical down spread modulation on CPU, PCI, IOAPIC and 3V66 output clocks.  Uses external 14.318MHz crystal. The ICS932S200 is a dual CPU clock generator for serverworks HE-T, HE-SL-T, LE-T chipsets for P III type processors in a Dual-CPU system. Single ended CPU clocks provide faster than 1.5V/ns transition times by parallel connection of 2 CPU pins to each processor. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS932S200 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Key Specification:  CPU Output Jitter: 150ps  IOAPIC Output Jitter: 250ps  3V66, PCI Output Jitter: 250ps  CPU Output Skew: <175ps  PCI Output Skew: <500ps  3V66 Output Skew <250ps  IOAPIC Output Skew <250ps  CPU to 3V66 Output Offset: 0 - 1.5ns (CPU leads)  CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)  CPU to APIC Output Offset: 1.5 - 4.0ns (CPU leads) PCICLK_F PLL2 PLL1 Spread Spectrum 48MHz CPUCLK (5:0) IOAPIC (2:0) 3V66 (1:0) PCICLK (4:0)5 XTAL OSC CPU DIVDER IOAPIC DIVDER 3V66 DIVDER PCI DIVDER Stop PD# PCI_STOP# CPU_STOP# SPREAD# SEL 133/100# SEL0 SEL1 Control Logic Config. Reg. REF (1:0) GND REF0 REF1 VDD GND GND PCICLK_F VDD PCICLK0 PCICLK1 GND PCICLK2 PCICLK3 VDD VDD PCICLK4 GND GND GND VDD VDD GND 3V66_0 3V66_1 VDD SEL 133/100# VDDL IOAPIC2 IOAPIC1 IOAPIC0 GND VDDL CPUCLK5 CPUCLK4 GND VDDL CPUCLK3 CPUCLK2 GND VDDL CPUCLK1 CPUCLK0 GND VDD GND PCI_STOP# CPU_STOP# PD# SPREAD# SEL1 SEL0 VDD 48MHz GND ICS932S200

0427D—12/15/08 Pin Descriptions Pin number Pin name Type Description 1, 7, 8, 13, 19 20, 21, 24, 29, 38, 40, 44, 48, GND PWR Gnd pins 3, 2 REF(1:0) OUT 14.318MHz reference clock outputs at 3.3V 4,. 10, 16, 17, 22, 23, 27, 31, VDD PWR Power pins 3.3V 5 X1 IN XTAL_IN 14.318MHz crystal input

6 X2 OUT XTAL_OUT Crystal output

9 PCICLK_F OUT Free running PCI clock not affected by PCI_STOP#

18, 15, 14, 12, 11 PCICLK (4:0) OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks. 26, 25 3V66 (1:0) OUT 66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. 28 SEL 133/100# IN This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz, Low=100MHz 30 48MHz OUT Fixed 48MHz clock output. 3.3V 33, 32 SEL (1:0) IN Function select pins. See truth table for details.

34 SPREAD# IN

Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC and 3V66 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread modulation.

35 PD# IN

This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state.

36 CPU_STOP# IN This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0"

when driven active(Low).

37 PCI_STOP# IN This asynchronous input halts the PCICLK at logic"0" when driven

active(Low). PCICLK_F is not affected by this input. 43, 47, 51, 56 VDDL PWR Power pins 2.5V 50, 49, 46, 45, 42, 41 CPUCLK (5:0) OUT Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL 133/100MHz. 55, 54, 53 IOAPIC (2:0) OUT IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz.

0427D—12/15/08 Frequency Select: Note: 1. TCLK is a test clock driven on the x1 input during test mode. ICS932S200 Power Management Features: Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. 4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW. 5. IOAPIC, REF , 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions except PD# = LOW L E S # 0 0 1 / 3 3 11 L ES0 L E S U P C z H M 6 6 V 3 z H M I C P z H M 8 4 z H M F E R z H M C I P A O I z H M s t n e m m o C 00 0 Z - iHZ - iHZ - iHZ - iHZ - iHZ - iHe t a t s - i r T 00 1A /NA /NA /NA /NA /NA /Nd e v r e s e R 00 016 . 663 . 33Z - iH8 1 3 . 417 6 . 6 1 L L P z H M 8 4 d e l b a s i d 10 0 2 / K L CT4 / K L CT8 / K L CT2 / K L CTK L CT6 1 / K L CT) 1 ( e d o m t s e T 1A /NA /NA /NA /NA /NA /Nd e v r e s e R 11 0 3 316 . 663 . 33Z - iH8 1 3 . 417 6 . 6 1 # P O T S _ U PC# DP# P O T S _ I CPK L C U PCC I P A OI6 6 V3I CPF _ I C P . F E R z H M 8 4c sOs O C V X0 XW OLW OLW OLW OLW OLW OLF FOF F O 01 0 W OLN OW OLW OLN ON ON ON O 01 1 W OLN OW OLN ON ON ON ON O 11 0 N ON ON OW OLN ON ON ON O

1 N ON ON ON ON ON ON ON O

0427D—12/15/08 Power Management Requirements: Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. l a g n iSe t a t S l a g n i S y c n e t a L f o s e g d e g n i s i r f o . o N K L C I C P P O T S _ U P C ) d e l b a s i d (01 ) d e l b a n e (11 # P O T S _ I C P ) d e l b a s i d (01 ) d e l ba n e (11 # D P ) n o i t a r e p o l a m r o n (1S m 3 ) n w o d r e w o p (0. x a m 2 CPU_STOP# Timing Diagram CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. Notes: 1. All timing is referenced to the internal CPUCLK. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. 3V66 clocks also stop/start before 4. PD# and PCI_STOP# are shown in a high state. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz CPUCLK (internal) (internal) (externall) (externall) PCICLK PCI_STOP# CPU_STOP# PD# CPUCLK 3V66

0427D—12/15/08 PCI_STOP# Timing Diagram PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled. Notes: 1. All timing is referenced to CPUCLK. 2. Internal means inside the chip. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high state. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. CPUCLK (internal) (internal) (externall) PCICLK PCI_STOP# CPU_STOP# PD# PCICLK

0427D—12/15/08 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS932S200 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may e xist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. CPUCLK 3V66 PCICLK VCO Crystal PD#

0427D—12/15/08 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2V DD+0.3 V Input Low Voltage V IL VSS-0.3 0.8 V Input High Current I IH VIN = VDD 0.1 5 µA Input Low Current I IL1 VIN = 0 V; Inputs with no pull-up resistors -5 2.0 µA Input Low Current I IL2 VIN = 0 V; Inputs with pull-up resistors -200 -100 µA Operating I DD3.3OP100 Select @ 100MHz; Max discrete cap loads 70 160 Supply Current I DD3.3OP133 Select @ 133MHz; Max discrete cap loads 80 Power Down IDD3.3PD CL =30 pF; PWRDWN# = 0 Supply Current Input frequency F i VDD = 3.3 V 12 14.32 16 MHz Input Capacitance 1 CIN Logic Inputs 5 pF CINX X1 & X2 pins 27 36 45 pF Transition Time 1 TTrans To 1st crossing of target Freq. 3 ms Settling Time1 TS From 1st crossing to 1% target Freq. 1 ms Clk Stabilization TStab From VDD = 3.3 V to 1% target Freq. 3m s 1Guaranteed by design, not 100% tested in production. uA200102 mA Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating I DD2.5OP100 Select @ 100MHz; Max discrete cap loads 38 75 Supply Current IDD2.5OP133 Select @ 133MHz; Max discrete cap loads 69 90 Guaranteed by design, not 100% tested in production. mA

0427D—12/15/08 Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH2B IOH = -12.0 mA 2 2.2 V Output Low Voltage V OL2B IOL = 12 mA 0.3 0.4 V Output High Current I OH2B VOH = 1.7 V -35 -19 mA Output Low Current I OL2B VOL = 0.7 V 19 27 mA Rise Time t r2B Fall Time t f2B Duty Cycle d t2B 1 VT = 1.25 V 45 50.7 55 % Skew tsk2B 1 VT = 1.25 V 93 175 ps Jitter, Cycle-to-cycle tjcyc-cyc2B 1 VT = 1.25 V 108 150 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH1 IOH = -11 mA 2.4 3.1 V Output Low Voltage V OL1 IOL = 9.4 mA 0.25 0.4 V Output High Current I OH1 VOH = 2.0 V -60 -22 mA Output Low Current I OL1 VOL = 0.8 V 25 44 mA Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.44 2 ns Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.24 2 ns Duty Cycle dt1 VT = 1.5 V 45 48.2 55 % Skew tsk1 VT = 1.5 V 83 250 ps Jitter, Cycle-to-cycle 1 tjcyc-cyc1 VT = 1.5 V 110 250 ps Guaranteed by design, not 100% tested in production.

0427D—12/15/08 Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH1 IOH = -11 mA 2.4 3.1 V Output Low Voltage V OL1 IOL = 9.4 mA 0.2 0.4 V Output High Current I OH1 VOH = 2.0 V -60 -22 mA Output Low Current I OL1 VOL = 0.8 V 25 45 mA Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 1.2 2 ns Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 1.1 2 ns Duty Cycle dt1 VT = 1.5 V 45 50.8 55 % Skew tsk1 VT = 1.5 V 79 500 ps Jitter, One Sigma tj1σ1 VT = 1.5 V 150 ps Jitter, Absolute tjabs1 VT = 1.5 V -250 250 ps Jitter, Cycle-to-cycle 1 tjcyc-cyc1 VT = 1.5 V 129 250 ps Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH4B IOH = -12 mA 2 2.23 V Output Low Voltage V OL4B IOL = 12 mA 0.3 0.4 V Output High Current I OH4B VOH = 1.7 V -36 -16 mA Output Low Current I OL4B VOL = 0.7 V 19 26 mA Rise Time Fall Time Duty Cycle Dt4B VT = 1.25 V 45 50.3 55 % Skew tsk4B 1 VT = 1.25 V 63 250 ps Jitter, Cycle-to-cycle 1 tjcyc-cyc4B VT = 1.25 V 80 250 ps Guaranteed by design, not 100% tested in production.

0427D—12/15/08 Electrical Characteristics - 48MHz, REF TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH5 IOH = -12 mA 2.6 2.9 V Output Low Voltage V OL5 IOL = 9 mA 0.3 0.4 V Output High Current I OH5 VOH = 2.0 V -35 -22 mA Output Low Current I OL5 VOL = 0.8 V 17 23 mA Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V, 48MHz 1.9 4 ns Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V, 48MHz 2 4 ns Duty Cycle dt5 VT = 1.5 V, 48MHz 45 50.2 55 % Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V, REF 0.7 N/A ns Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V, REF 0.5 N/A ns Duty Cycle dt5 VT = 1.5 V, REF 45 52 N/A % Jitter, Cycle-to-cycle 1 tjcyc-cyc5 VT = 1.5 V, 48MHz 239 500 ps Jitter, Cycle-to-cycle 1 tjcyc-cyc5 VT = 1.5 V, REF 413 1000 ps Guaranteed by design, not 100% tested in production.

0427D—12/15/08

Ordering Information

Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Example: XXXX y F - PPP T MIN MAX MIN MAX A 2.413 2.794 .095 .110 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 D E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC 0.025 BASIC h 0.381 0.635 .015 .025 L 0.508 1.016 .020 .040 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 18.288 18.542 .720 .730 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B N D mm. D (inch) SEE VARIATIONS SYMBOL SEE VARIATIONS SEE VARIATIONS In Millimeters COMMON DIMENSIONS In Inches COMMON DIMENSIONS SEE VARIATIONS 300 mil SSOP

0427D—12/15/08 INDEX AREA INDEX AREA 121 2 N D E1 E /c97 SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C 6.10 mm. Body, 0.50 mm. pitch TSSOP (240 mil) (0.020 mil) MIN MAX MIN MAX A -- 1.20 -- .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e L 0.45 0.75 .018 .030 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 13.90 14.10 .547 .555 10-0039 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 0.50 BASIC 0.020 BASIC SEE VARIATIONS SEE VARIATIONS N D mm. D (inch) Reference Doc.: JEDEC Publication 95, MO-153 Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Example: XXXX y G - PPP T

0427D—12/15/08

Revision History

Rev. Issue Date Description Page # D 12/15/2008 Removed ICS prefix from orderin g information 11-12

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