92CD54IF

TMP92CD54I TOSHIBA | Alldatasheet

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Technical content

CMOS 32-bit Micro-controller TMP92CD54IF 1. Outline and Device Characteristics TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package. Device characteristics are as follows: (1) CPU : 32-bit CPU(900/H1 CPU) Compatible with TLCS-900,900/L,900/L1,900/H,900/H2’s instruction code 16Mbytes of linear address space General-purpose register and register banks Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case) Minimum instruction execution time : 50ns(at 20MHz) Internal data bus : 32-bit (2) Internal memory Internal RAM : 32K-byte Internal ROM : 512K-byte Mask ROM

(3) External memory expansion 16M-byte linear address space (memory mapped I/O) External data bus : 8bit(for external I/O expansion) * Can’t use upper address bus when built-in I/Os are selected (4) Memory controller (MEMC) Chip select output : 1 channel (5) 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (PPG) output mode (4 channels) 8-bit pulse width modulation (PWM) output mode (4 channels) (6) 16-bit timer : 2 channels 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) output mode Frequency measurement mode Pulse width measurement mode Time differential measurement mode (7) Serial interface (SIO) : 2 channels I/O interface mode Universal asynchronous receiver transmitter (UART) mode (8) Serial expansion interface (SEI) : 1 channel Baud rate 4/2/0.5Mbps at fc=20MHz. (9) Serial bus interface (SBI) : 3 channels Clocked-synchronous 8-bit serial interface mode I 2C bus mode (10) CAN controller : 1channel Supports CAN version 2.0B. 16 mailboxes (11) 10-bit A/D converter (ADC) : 12 channels A/D conversion time 8µsec @fc=20MHz. Total tolerance +/- 3LSB (excluding quantization error) Scan mode for all 12channels (12) Watch dog timer (WDT) (13) Timer for real-time clock (RTC) Can operate with only low frequency oscillator. (14) Interrupt controller (INTC) : 60 interrupt sources 9 interrupts from CPU 42 internal interrupt vectors 9 external interrupt vectors (15) I/O Port : 68pins (16) Standby mode Four modes : IDLE3,IDLE2,IDLE1 and STOP STOP mode can be released by 9 external inputs. (17) Internal voltage detection flag (RAMSTB)

(18) Power supply voltage VCC5 = 4.5V to 5.25V VCC3 = 3.3V (VCC3 Connect to REGOUT; built-in voltage regulator.) (19) Operating temperature : -40 to 85 degree C (20) Package : P-LQFP100-1414-0.50F

Figure 1 TMP92CD54I block diagram PORT0 PORT4 INTERRUPT CONTROLLER SERIAL BUS I/F Channel 0 SERIAL BUS I/F Channel 1 SERIAL EXP.I/F PM0( SS /A8) PM1(MOSI/A9) PM2(MISO/A10) PM3(SECLK/A11) PN0(SCK0) PN1(SO0/SDA0) PN2(SI0/SCL0) PN3(SCK1/A12) PN4(SO1/SDA1/A13) PN5(SI1/SCL1/A14) P00toP07 (D0toD7) P40toP47 (A0toA7) INT0 NMI RESET AM0 AM1 TEST0 TEST1 PORT7 P70( RD ) P71( WR ) P73( CS ) P74 P75( WAIT ) CLK IX IY IZ SP L H E D C B A W XSP XIZ XIY XIX XHL XDE XBC XWA 900/H1 CPU F SR 32 bits P C 32KB RAM 512KB Mask ROM SERIAL I/O Channel 0 SERIAL I/O Channel 1 10-BIT 12CH A/D CONVERTER 8BIT TIMER (TIMER0) 8BIT TIMER (TIMER1) 8BIT TIMER (TIMER2) 8BIT TIMER (TIMER3) 8BIT TIMER (TIMER4) 8BIT TIMER (TIMER5) 8BIT TIMER (TIMER6) 8BIT TIMER (TIMER7) CAN CONTROLLER WATCH-DOG TIMER 16BIT TIMER (TIMER8) 16BIT TIMER (TIMERA) REAL TIME CLOCK (RTC) OSC RTC Regulator (TO7/INT4)PC5 (TI4/INT3)PC3 (TO3/INT2)PC2 (TO5)PC4 (TI0/INT1)PC0 (TO1)PC1 (TX)PF6 (RX)PF7 VREFL VREFH ADVSS ADVCC PG0toPG7 (AN0toAN7) PL0toPL3 (AN8toAN11) (RXD0)PF1 (TXD0)PF0 (RXD1)PF4 (TXD1)PF3 (SCLK0/ CTS0 )PF2 (SCLK1/ CTS1 )PF5 (TI8/WUINT0/INT5/A16)PD0 (TI9/WUINT1/INT6/A17)PD1 (TO8/WUINT2/A18)PD2 (TO9/WUINT3/A19)PD3 (TIA/WUINT4/INT7/A20)PD4 (TIB/WUINT5/A21)PD5 (TOA/WUINT6/A22)PD6 (TOB/WUINT7/A23)PD7 REGOUT XT1 XT2 DVSS[6] DVCC5[5] REGEN DVCC3[3] CONNECT SERIAL BUS I/F Channel 2 PM4(SCK2) PN6(SO2/SDA2/A15) P72(SI2/SCL2)

1. Pin Assignment and Functions

2.1 Pin Assignment

Figure 2.1 TMP92CD54I Pin Assignment PL3/AN11 PL2/AN10 PL1/AN9 PL0/AN8 PG7/AN7 PG6/AN6 PG5/AN5 PG4/AN4 PG3/AN3 PG2/AN2 PG1/AN1 PG0/AN0 DVSS P75/WAIT DVCC3 P74 P73/CS P72/SI2/SCL2 P71/WR P70/RD AM0 RESET AM1 CLK TEST0 TMP92CD54IF (P-LQFP100-1414-0.50F) 14 x 14 x 1.4 TOP VIEW DVCC5 DVSS TEST1 XT1 XT2 DVCC3 PN6/SO2/SDA2/A15 PN5/SI1/SCL1/A14 PN4/SO1/SDA1/A13 PN3/SCK1/A12 DVSS PN2/SI0/SCL0 DVCC5 PN1/SO0/SDA0 PN0/SCK0 PC0/TI0/INT1 PC1/TO1 PC2/TO3/INT2 PC3/TI4/INT3 PC4/TO5 PC5/TO7/INT4 REGEN DVSS D6/P06 D7/P07 A0/P40 A1/P41 A2/P42 A3/P43 A4/P44 A5/P45 A6/P46 A7/P47 DVCC3 INT0 DVSS NMI DVCC5 A16/WUINT0/INT5/TI8/PD0 A17/WUINT1/INT6/TI9/PD1 A18/WUINT2/TO8/PD2 A19/WUINT3/TO9/PD3 A20/WUINT4/INT7/TIA/PD4 A21/WUINT5/TIB/PD5 A22/WUINT6/TOA/PD6 A23/WUINT7/TOB/PD7 REGOUT DVCC5 ADVSS ADVCC VREFL VREFH RX/PF7 TX/PF6 CTS1/SCLK1/PF5 RXD1/PF4 TXD1/PF3 CTS0/SCLK0/PF2 RXD0/PF1 TXD0/PF0 DVSS PM4/SCK2 DVCC5 A8/SS/PM0 A9/MOSI/PM1 A10/MISO/PM2 A11/SECLK/PM3 D0/P00 D1/P01 D2/P02 D3/P03 D4/P04 D5/P05 51 50 076 080 085 090 095 100

2.2 Pin names and functions

The following table shows the names and functions of the input/output pins. Pin name Pin number Number of pins In/Out Function (CMOS) P00..P07 D0..D7 20th…27 th 8 (TTL) in/out in/out Port 0: I/O port. Input or output specifiable in units of bits. Data: Data bus 0 to 7. P40..P47 A0..A7 28th…35 th 8 in/out out Port4: I/O port. Input or output specifiable in units of bits. Address: Address bus 0 to 7. P70 RD 81st 1 in/out out Port70: I/O port. Read: Outputs strobe signal to read external memory. P71 WR 82nd 1 in/out out Port 71: I/O port. Write: Output strobe signal to write external memory. P72 SI2 SCL2 83rd 1 in/out Port 72: I/O port. SBI channel 2: Input data at SIO mode SBI channel 2: Clock input/output at I²C mode P73 CS 84 th 1 in/out out Port 73: I/O port. Chip select: Outputs “low” if address is within specified address area. P74 85 th 1 in/out Port 74: I/O port. P75 WAIT 87th 1 in/out in Port 75: I/O port. Wait: Signal used to request CPU bus wait. PC0 TI0 INT1 th 1 in/out in in Port C0: I/O port. Timer input 0: Input pin for timer 0. Interrupt request pin 1: Rising-edge interrupt request pin. PC1 TO1 57th 1 in/out out Port C1: I/O port. Timer output 1: Output pin for timer 1. PC2 TO3 INT2 th 1 in/out out in Port C2: I/O port. Timer output 3: Output pin for timer 3. Interrupt request pin 2: Rising-edge interrupt request pin. PC3 TI4 INT3 th 1 in/out in in Port C3: I/O port. Timer input 4: Input pin for timer 4. Interrupt request pin 3: Rising-edge interrupt request pin. PC4 TO5 54 th 1 in/out out Port C4: I/O port. Timer output 5: Output pin for timer 5. PC5 TO7 INT4 rd 1 in/out out in Port C5: I/O port. Timer output 7: Output pin for timer 7. Interrupt request pin 4: Rising-edge interrupt request pin. PD0 TI8 INT5 A16 WUINT0 st 1 in/out in in out in Port D0: I/O port. Timer input 8: Input pin for timer 8. Interrupt request pin 5: Interrupt request pin with programmable rising/falling edge. Address: Address bus 16. Wake up input 0: Wake up request pin with programmable rising, falling or both falling and rising edge. PD1 TI9 INT6 A17 WUINT1 nd 1 in/out in in out in Port D1: I/O port. Timer input 9: Input pin for timer 9. Interrupt request pin 6: Rising-edge interrupt request pin. Address: Address bus 17. Wake up input 1: Wake up request pin with programmable rising, falling or both falling and rising edge. PD2 TO8 A18 WUINT2 rd 1 in/out out out in Port D2: I/O port. Timer output 8: Output pin for timer 8 Address: Address bus 18. Wake up input 2: Wake up request pin with programmable rising, falling or both falling and rising edge. PD3 TO9 A19 WUINT3 th 1 in/out out out in Port D3: I/O port. Timer output 9: Output pin for timer 9 Address: Address bus 19. Wake up input 3: Wake up request pin with programmable rising, falling or both falling and rising edge. INT5 WUINT0 INT4 INT3 INT2 INT1 INT6 WUINT1 WUINT2 WUINT3

Port D4: I/O port. Timer input A: Input pin for timer A Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge. Address: Address bus 20. Wake up input 4: Wake up request pin with programmable rising, falling or both falling and rising edge. PD5 TIB A21 WUINT5 46th 1 in/out in out in Port D5: I/O port. Timer input B: Input pin for timer B. Address: Address bus 21. Wake up input 5: Wake up request pin with programmable rising, falling or both falling and rising edge. PD6 TOA A22 WUINT6 th 1 in/out out out in Port D6: I/O port. Timer output A: Output pin for timer A. Address: Address bus 22. Wake up input 6: Wake up request pin with programmable rising, falling or both falling and rising edge. PD7 TOB A23 WUINT7 48th 1 in/out out out in Port D7: I/O port. Timer output B: Output pin for timer B. Address: Address bus 23. Wake up input 7: Wake up request pin with programmable rising, falling or both falling and rising edge. PF0 TXD0 12th 1 in/out out Port F0: I/O port. Serial interface channel 0: Transmission data. PF1 RXD0 11th 1 in/out in Port F1: I/O port. Serial interface channel 0: Receive data. PF2 SCLK0 CTS0 10th 1 in/out in/out in Port F2: I/O port. Serial interface channel 0: Clock input/output. Serial interface channel 0: Data ready to send. (Clear-to-send) PF3 TXD1 9 th 1 in/out out Port F3: I/O port. Serial interface channel 1: Transmission data. PF4 RXD1 8 th 1 in/out in Port F4: I/O port. Serial interface channel 1: Receive data. PF5 SCLK1 CTS1 7th 1 in/out in/out in Port F5: I/O port. Serial interface channel 1: Clock input/output. Serial interface channel 1: Data ready to send. (Clear-to-send) PF6 TX 6th 1 in/out out Port F6: I/O port. CAN: Transmission data. PF7 RX 5 th 1 in/out in Port F7: I/O port. CAN: Receive data. PG0..PG7 AN0..AN7 89th…96 th 8 in in Port G: Input-only port. Analog input 0 to 7: AD converter input pins. PL0..PL3 AN8..AN1 th...100th 4 in in Port L0 to L3: Input-only port. Analog input 8 to 11: AD converter input pins. PM0 SS 16th 1 in/out in out Port M0: I/O port. SEI: Slave select input. Address: Address bus 8. PM1 MOSI th 1 in/out in/out out Port M1: I/O port. SEI: Master output, slave input. Address: Address bus 9. PM2 MISO A10 th 1 in/out in/out out Port M2: I/O port. SEI: Master input, slave output. Address: Address bus 10. PM3 SECLK A11 th 1 in/out in/out out Port M3: I/O port. SEI: Clock input/output. Address: Address bus 11. PM4 SCK2 14 th 1 in/out in/out Port M4: I/O port. SBI channel 2: Clock input/output at SIO mode. PN0 SCK0 59 th 1 in/out in/out Port N0: I/O port. SBI channel 0: Clock input/output at SIO mode. INT7 WUINT4 WUINT5 WUINT6 WUINT7

Port N1: I/O port. SBI channel 0: Output data input/output at SIO mode SBI channel 0: Data input/output at I²C mode PN2 SI0 SCL0 nd 1 in/out in in/out Port N2: I/O port. SBI channel 0: Input data at SIO mode SBI channel 0: Clock input/output at I²C mode PN3 SCK1 A12 th 1 in/out in/out out Port N3: I/O port. SBI channel 1: Clock input/output at SIO mode Address: Address bus 12. PN4 SO1 SDA1 A13 th 1 in/out out in/out out Port N4: I/O port. SBI channel 1: Output data at SIO mode SBI channel 1: Data input/output at I²C mode Address: Address bus 13. PN5 SI1 SCL1 A14 66th 1 in/out in in/out out Port N5: I/O port. SBI channel 1: Input data at SIO mode SBI channel 1: Clock input/output at I²C mode Address: Address bus 14 PN6 SO2 SDA2 A15 th 1 in/out out Port N6: I/O port. SBI channel 2: Output data at SIO mode SBI channel 2: data input output at I2C mode Address: Address bus 15. NMI 39th 1 in Non-maskable interrupt: Interrupt request pin with programmable falling or both falling and rising edge. INT0 37 th 1 in Interrupt request pin 0: Interrupt request pin with programmable level or rising-edge. AM0,1 80 th, 78th 2 in Address Mode selection: Connect AM0 pin to L, AM1 pins to H. TEST0,1 76 th, 71st 2 in Test mode pins: Should be set to L. CLK 77 th 1 out Programmable clock output (with pull-up register) X1/X2 74 th, 72nd 2 in/out Oscillator connecting pins XT1/XT2 70 th, 69th 2 in/out Low frequency oscillator connecting pins. Crystal or ceramic resonator is connected. RC oscillation is also possible RESET 79th 1 in Reset: Initializes LSI (with pull-up register). VREFH 4 th 1 in AD reference voltage high VREFL 3 rd 1 in AD reference voltage low ADVCC 2 nd 1 - Power supply pin for AD converter (+5V): Connect ADVCC pin to 5V power supply. ADVSS 1 st 1 - GND pin for AD converter: Connect ADVSS pin to GND (0V). DVCC5 15th, 40th, 50th,61st,75th 5 - Power supply pins (+5V): Connect all DVCC5 pins to 5V power supply. DVCC3 36 th,68th,86th 3 - Power supply pins (+3.3V): Connect all DVCC3 pins to REGOUT pin. DVSS 13th,38th,51st, 63rd,73rd,88th 6 - GND: Connect all DVSS pins to GND (0V). REGOUT 49 th 1 out Regulator output 3.3V: Connect capacitor to stabilize the regulator output. REGEN 52 nd 1 in Regulator enable pin: Should be set to H or OPEN (with pull-up register). INT0 NMI

1. OPERATION This section describes the basic components, functions and operation of TMP92CD54I.

3.1 CPU

TMP92CD54I contains an advanced high-speed 32-bit CPU (900/H1 CPU)

3.1.1 CPU Outline

900/H1 CPU is high-speed and high-performance CPU based on 900/H CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly. Outline of 900/H1 CPU are as follows: 900/H1 CPU Width of CPU Address Bus 24-bit Width of CPU Data Bus 32-bit Internal Operating Frequency 16 to 20MHz (@f OSC=8 to 10MHz) Minimum Bus Cycle (Internal RAM) 1-clock access (50ns@fOSC=10MHz) Internal RAM 32-bit 1-clock access Internal ROM 32-bit interleave 2-1-1-1-clock access 8/16-bit 2-clock access PORT, INTC, MEMC Internal I/O 8/16-bit 5 to 6-clock access SEI, SIO, WDT, 8-bit Timer, 16-bit Timer, RTC, 10-bit ADC, SBI, CAN External Device 8-bit 2-clock access (can insert some waits) Minimum Instruction Execution Cycle 1-clock(50ns@fOSC=10MHz) Conditional Jump 2-clock(100ns@f OSC=10MHz) Instruction Queue Buffer 12-byte Instruction Set Compatible with TLCS-900, 900/H, 900/L, 900/L1 and 900/H2 (NORMAL, MIN, MAX and LDX instruction is deleted) Micro DMA 8-channels

3.1.2 Reset Operation

When resetting TMP92CD54I microcontroller, ensu re that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (4us). At reset the clock doubler is bypassed and system clock operates at 5MHz (fOSC=10MHz). When the Reset has been accepted, the CPU performs the following:

• Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored at address FFFF00H to FFFF02H: PC<0 to 7> ← data in location FFFF00H PC<8 to 15> ← data in location FFFF01H PC<16 to 23> ← data in location FFFF02H
• Sets the Stack Pointer (XSP) to 00000000H.
• Sets bits <IFF0 to IFF2> of the Status Register (SR) to 111 (thereby setting the Interrupt Level Mask Register to level 7).
• Clears bits <RFP0 to RFP1> of the Status Register to 00 (thereby selecting Register Bank 0). When the Reset is released, the CPU starts executing instructions according to the Program Counter settings. CPU internal registers not mentioned above do not change when the Reset is released. When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
• Initializes the internal I/O registers as table of “Special Function Register” in Section 5.
• Sets the port pins, including the pins that also act as internal I/O, to General-Purpose Input or Output Port Mode. When external reset is released, built-in clock doubler begins operation and after the stable time (1.6384ms @ fOSC=10MHz) elapse of the circuit, internal reset is released. The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on TMP92CD54I may be spoiled because the control signals are unstable until power supply becomes stable after power on reset. TMP92CD54I can initialize all general-purpose ports and CLKOUT setting by reset, even if the device is not fed DVCC3 voltage to. When RESET = L level, CLKOUT will be initialized to High-z, but CLKOUT is pulled-up in internal logic. If the device is not fed DVCC3 voltage to, RESET = L level, CLKOUT will be High-z or pulled-up (H level output).

3.1.3 Setting of TEST0, TEST1, AM0 and AM1

Connect TEST0, TEST1 pin to “GND” to use at NORMAL mode. Set AM0 pin to “0” and set AM1 pin to “1” to use. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin Operation Mode RESET AM1 AM0 TEST1 TEST0 Single-chip Mode 1 0 0 0

3.2 Memory Map

Figure 3.2 is a memory map of TMP92CD54I. 000000H 000400H 16Mbyte area (R) ( −R) (R +) (R + R8/16) (R + d8/16) (nnn) Direct area (n) 64Kbyte area (nn)

512 KByte

(1 KByte) Internal RAM (32 KByte) 008400H 010000H F80000H ( = Internal area) FFFF00H FFFFFFH Vector table (256 Byte) External memory 000100H Emulator Control Area (64K Byte) Figure 3.2 Memory Map Note1: The emulator control area is for emulator, it is mapped F00000H to F10000H address after reset. Note2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Note3: On emulator WR signal and RD signal are asserted, when emulator control area is accessed. Be careful to use external memory. Note4: Since there is a possibility of abnormal writing/reading of the data if Bus width put the different memories in consecutive address, do not execute an access which is placed on both memories with one command. (Note1) (Note2)

3.3 The Clock Function and Standby Function

3.3.1 Block diagram of system clock

*1) Clock-doubler outputs averaging 40MHz clock because it is corrected in clock unit of High Frequency OSC output (10MHz) though it has the possibility that the tolerance of 1.46ns at 40MHz (reference data) is included. Figure 3.3.1 Block Diagram of System clock 10MHz 2/5 SEI 16MHz System Clock ‘fc’ For RTC 14-stage binary counter Clock doubler*1 (PLL)×4 (40MHz) 10MHz (10MHz) To generate the external memory interface timing High Frequency OSC XT1 XT2 (32.768 kHz) Low frequency OSC (32.768 kHz) fs 20MHz ･CPU ･MEMC ･INTC ･ROMC ･PORT ･CAN ･SIO ･TIMER ･WDT ･SBI ･A/D ･RTC

3.3.2 Standby controller

(1) Halt Modes When the HALT instruction is executed, the operating mode switches to Idle2, Idle1, Idle3 or Stop Mode, depending on the contents of the CLKMOD<HALTM1,HALTM0> register. Clock Mode Register 7 6 5 4 3 2 1 0 bit Symbol HALTM1 HALTM0 - - - CLKOE CLKM1 CLKM0 Read/Write R/W R/W R/W After reset 1 1 - 0 - 0 0 0 Function Standby mode 00: IDLE3 01: STOP 10: IDLE1 11: IDLE2 Fix to “0” CLKoutput enable 0: not output 1: output CLK output select 00: fc 01: Reserved 10: 2/5 fc 11: Reserved CLK output clock select 00 fc

01 Reserved

11 Reserved

0 Not output (Pull up)

1 Output

Selects standby mode by HALT instruction

00 IDLE3

01 STOP

10 IDLE1

11 IDLE2

Figure 3.3.2 Clock Mode Register CLKMOD (010AH)

The subsequent actions performed in each mode are as follows: ① Idle2: The CPU only is halted. In Idle2 Mode internal I/O operations can be performed by setting the following registers. Table 3.3.1 Shows the registers of setting operation during Idle2 Mode. Table 3.3.1 Shows the registers of setting operation during Idle2 Mode Internal I/O SFR TIMER0,TIMER1 TRUN01<I2T01> TIMER2,TIMER3 TRUN23<I2T23> TIMER4,TIMER5 TRUN45<I2T45> TIMER6,TIMER7 TRUN67<I2T67> TIMER8 TRUN8<I2T8> TIMERA TRUNA<I2TA> SIO0 SC0MOD1<I2S0> SIO1 SC1MOD1<I2S1> SBI0 SBI0BR0<I2SBI0> SBI1 SBI1BR0<I2SBI1> SBI2 SBI2BR0<I2SBI2> A/D converter ADMOD1<I2AD> WDT WDMOD<I2WDT> ② Idle1: Only the oscillator of low and high frequency continue to operate. ③ Idle3: Only the oscillator of low frequency and RTC are operated. ④ Stop: All internal circuits stop operating. The operation of each of the different Halt Modes is described in Table 3.3.2. Table 3.3.2 I/O operation during Halt Modes Halt Mode Idle2 Idle1 Idle3 Stop CLKMOD <HALT1:0> 11 10 00 01 CPU Halt I/O ports Maintain same state as when HALTinstruction was executed. See table 3.3.5 8-bit TMR, 16-bit TMR SIO, SBI A/D converter WDT Selectable See table 3.3.1 Stopped RTC, XT1 CAN, SEI Block Interrupt controller Operational

(2) How to clear a Halt mode The Halt state can be cleared by a Reset or by an interrupt request. The combination of the value in <IFF0:IFF2> of the Interrupt Mask Register and the current Halt mode determine in which ways the Halt mode may be cleared. The details associated with each type of Halt state clearance are shown in Table 3.3.5.

• Clearance by interrupt request Whether or not the Halt mode is cleared and subsequent operation depends on the status of the generated interrupt. If the interrupt request level set before execution of the HALT instruction is greater than or equal to the value in the Interrupt Mask Register, the following sequence takes place: the Halt mode is cleared, the interrupt is then processed, and the CPU then resumes execution starting from the instruction following the HALT instruction. If the interrupt request level set before execution of the HALT instruction is less than the value in the Interrupt Mask Register, the Halt mode is not cleared. (If a non-maskable interrupt is generated, the Halt mode is cleared and the interrupt processed, regardless of the value in the Interrupt Mask Register.) However, for INT0 only, even if the interrupt request level set before execution of the HALT instruction is less than the value in the Interrupt Mask Register, the Halt mode is cleared. In this case, the interrupt is not processed and the CPU resumes execution starting from the instruction following the HALT instruction. The interrupt request flag remains set to 1.
• Clearance by Reset Any Halt state can be cleared by Reset. When Stop Mode is cleared by RESET signal, sufficient time (at least10ms@f OSCMHz) must be allowed after the Reset for the operation of the oscillator and clock doubler to stabilize. When a Halt mode is cleared by resetting, the contents of the internal RAM remain the same as they were before execution of the HALT instruction. However, all other settings are re-initialized. (Clearance by an interrupt affects neither the RAM contents nor any other settings – the state which existed before the HALT instruction was executed is retained.)

Table 3.3.3 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt Interrupt Enabled (interrupt level) ≥ (interrupt mask) Interrupt Disabled (interrupt level) < (interrupt mask) Halt mode Idle2 Idle1 Idle3 Stop Idle2 Idle1 Idle3 Stop NMI INTWDT *1 *1 INT1 to 7 INTT0 to 7 INTTR8 to B INTTO8, INTTOA INTRX0 to 1, TX0 to 1 INTCR0, INTCT0, INTCG0 INTSEM0, E0, R0, T0 INTSBE0, S0, E1, S1, E2, S2 INTAD All the above-mentioned interrupts [MASK] × × × × × × × × Interrupt Source of Halt state clearance : After clearing the Halt mode, CPU starts interrupt processing. (RESET initializes the microcont .) {: After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction. ×: Cannot be used to clear the Halt mode. −: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The Halt mode is cleared when the warm-up time has elapsed. *2: Any WUINT interrupt (WUINT0 to WUINT7) generate an INT0 interrupt. Note 1: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level H, interrupt processing is not correctly started. Note 2: When the external interrupts INT5 to INT7 are used during Idle2 Mode, set to 1 for TRUN8<I2T8> and TRUNA<I2TA>. (Example - clearing Idle1 Mode) An INT0 interrupt clears the Halt state when the device is in Idle1 Mode. Address 8203H LD (IIMC), 00H ; Selects INT0 interrupt rising edge. 8206H LD (INTE0AD), 06H ; Sets INT0 interrupt level to 6. 8209H EI 5 ; Sets interrupt level to 5 for CPU. 820BH LD (CLKMOD), 80H ; Sets Halt mode to Idle1 Mode. 820EH HALT ; Halts CPU. INT0 INT0 interrupt routine RETI 820FH LD XX, XX

③ Idle3 Mode When Idle3 Mode is selected, internal circuits stop including the internal oscillator, except the oscillator of low frequency and RTC. Pin status in Stop Mode depends on the settings in the WDMOD<DRVE> register. Table 3.3.5 summariz es the state of these pins in Stop Mode and Idle3 mode. After Idle3 Mode has been cleared system cloc k output starts when the warm-up time and clock doubler stable time have elapsed, in order to allow oscillation and clock doubler to stabilize. Figure 3.3.5 illustrates the timing for clearance of the Idle3 Mode Halt state by an interrupt. Idle3 mode can only be released by an NMI pin, INT0 pin or WUINT0 to WUINT7 pins (generate a INT0 interrupt) interrupt, or by reset. When Idle3 mode is released by other than reset, the system clock starts its output after the time set by the warm-up counter for the internal oscillation to stabilize. When using reset to release stop mode, input reset signals long enough for stable oscillation and clock doubler stable time. In systems with an external oscillator, the warm-up counter also operates when Idle3 mode is released. Therefore, such systems also re quire a warm-up time between input of release signals and system clock output. fc ( N o t e ) N e x t N e x t + 4 A0 to 23 RD WR D0 to 31 Data Data HALT instruction execution sequence Clearing interrupt Interrupt response sequence fs(32kHz) RTC Operated Operated Programmable Programmable Figure 3.3.5 Timing chart for Idle3 Mode Halt state cleared by interrupt Internal signals (Note); The interrupt processing starts after it completes for Startup time (T sta) of Oscillator, Warm-up time and clock doubler stable time period, after releasing HALT (Tsta + 1.6 ms + 1.6 ms). Please inquire about Startup time (Tsta) to each oscillator manufacturer.

④ Stop Mode When Stop Mode is selected, all internal circuits stop, including the internal oscillator. Pin status in Stop Mode depends on the settings in the WDMOD<DRVE> register. Table 3.3.5 summarizes the state of these pins in Stop Mode and Idle3 mode. After Stop Mode has been cleared system cloc k output starts when the warm-up time and clock doubler stable time have elapsed, in order to allow oscillation and clock doubler to stabilize. Figure 3.3.6 illustrates the timing for clearance of the Stop Mode Halt state by an interrupt. S T O P m o d e c a n o n l y b e r e l e a s e d b y a n N M I p i n , I N T 0 p i n o r W U I N T 0 t o W U I N T 7 pins(generate a INT0 interrupt) interrupt , or by reset. When STOP mode is released by other than reset, the system clock starts its output after the time set by the warm-up counter for the internal oscillation to stabilize. When using reset to release stop mode, input reset signals long enough for stable oscillation and clock doubler stable time. In systems with an external oscillator, the warm-up counter also operates when STOP mode is released. Therefore, such systems also re quire a warm-up time between input of release signals and system clock output. And if it released from STOP mode, RTCFC register will be initialized without a RESET input. Therefore, it is necessary to set up RTCFC register again after releasing from STOP mode. N e x t N e x t + 4 fc A0 to 23 RD WR D0 to 31 Data Data HALT instruction execution sequence Clearing interrupt Interrupt response sequence ( N o t e ) Figure 3.3.6 Timing chart for Stop Mode Halt state cleared by interrupt Table 3.3.4 Warming-up time and clock doubler stable time after clearance of Stop Mode and Idle3 Mode (@ fc=20MHz) Warm-up time 1.6 ms (2 14/fOSC) Clock doubler stable time 1.6 ms (2 14/fOSC) fc = 2×fOSC Internal signals (Note); The interrupt processing starts after it completes for Startup time (T sta) of Oscillator, Warm-up time and clock doubler stable time period, after releasing HALT (Tsta + 1.6 ms + 1.6 ms). Please inquire about Startup time (Tsta) to each oscillator manufacturer.

Table 3.3.5 Pin states in Idle3 and Stop Mode Pin Names I/O <DRVE> = 0 <DRVE> = 1 P00 to 07 Input Mode Invalid Output Mode Output D0 to D7 High-z Input Mode Invalid P40 to 47/A0 to 7 Output Mode High-z Output Input Mode Invalid P70,P71,P73 to 75/ RD , WR , CS to WAIT Output Mode High-z Output Input Mode Input P72/SI2/SCL2 Output Mode Input Output Input Mode Invalid PC0 to PC5/TI0 to TO7 Output Mode High-z Output Input Mode Input Output Mode High-z Output PD0 to PD7/TI8 to TOB WUINT0 to 7 Input Input Mode Invalid PF0 to PF7/TXD0 to RX Output Mode High-z Output PG0 to PG7/AN0 to AN7 Input Mode Invalid PL0 to PL3/AN8 to AN11 Input Mode Invalid Input Mode Invalid PM0 to PM4 / SS to SCK2 Output Mode High-z Output Input Mode Invalid PN0 to PN6 /SCK0 to SO2&SDA2 Output Mode High-z Output NMI Input Input INT0 Input Input RESET Input Input AM0, AM1 Input Input TEST0, TEST1 Input Input X1 Input Invalid X2 Output H Level Output XT1 Input Invalid (STOP) Operate (IDLE3, RTCFC<XTEN>=1) XT2 Output H Level Output (STOP) Operate (IDLE3, RTCFC<XTEN>=1) CLK Output H level output (CLKMOD<CLKOE>=0) L level output (CLKMOD<CLKM1:0>=00) H or L level Output (CLKMOD<CLKM1:0>=10) Input: Input gate in operation. Input voltage should be fixed to “L” or “H” so that input pin stays constant. Output: Output state Invalid: Input pin invalid. High-z: Output pin High-Impedance. Note) At RTCFC<XTEN>=1.

3.4 Interrupts

Interrupts are controlled by the CPU Interrupt Mask Register <IFF2:0> (bits 12 to 14 of the Status Register) and by the built-in interrupt controller. TMP92CD54I has a total of 60 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources

• Software interrupts: 8 sources
• Illegal Instruction interrupt: 1 source Internal interrupts: 42 sources
• Internal I/O interrupts: 34 sources
• Micro DMA Transfer End interrupts: 8 sources External interrupts: 9 sources
• Interrupts on external pins ( NMI, INT0 to INT7) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six levels of priority can also be as signed to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt are generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU Interrupt Mask Register <IFF2:0>. If the priority level of the interrupt is greater than or equal to the value in the Interrupt Mask Register, the CPU accepts the interrupt. However, software interrupts and Illegal Instruction interrupts generated by the CPU are processed irrespective of the value in <IFF2:0>. The value in the Interrupt Mask Register <IFF2:0> can be changed using the EI instruction (EI num sets <IFF2:0> to num). For example, the command EI 3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent to the command EI 1). The DI instruction (sets <IFF2:0> to 7) is exactly equivalent to the EI 7 instruction. The DI instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 0 to 6). The EI instruction takes effect as soon as it is executed. In addition to the general-purpose Interrupt Processing Mode described above, there is also a Micro DMA Processing Mode. In Micro DMA Mode the CPU automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, TMP92CD54I also has a software start function in which micro DMA processing is requested in software rather than by an interrupt. Figure 3.4.1 is a flowchart showing overall interrupt processing.

start vector? Yes Interrupt processing PUSH PC PUSH SR SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 End PC ← (FFFF00H + V) Interrupt processing program Count ← Count－1 Count = 0 No Yes Data transfer by micro DMA No Micro DMA processing RETI instruction POP SR POP PC INTNEST←INTNEST − 1 Clear vector register generating micro DMA transfer end interrupt (INTTC0 to 7) Clear interrupt request flag Interrupt vector calue “V” read Interrupt request F/F clear Micro DMA soft start request * Figure 3.4.1 Interrupt and micro DMA processing sequence * Micro DMA is initiated by a write cycle which writes to the register DMAR.

3.4.1 General-purpose interrupt processing

When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and Illegal Instruction interrupts generated by the CPU, the CPU skips steps (a) and (c) and executes only steps (b), (d) and (e). (a) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level have been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: the smaller the vector value, the higher the priority.) (b) The CPU pushes the Program Counter (PC) and Status Register (SR) onto the top of the stack (pointed to by XSP). (c) The CPU sets the value of the CPU’s Interrupt Mask Register <IFF2:0> to the priority level for the accepted interrupt plus 1. Howe ver, if the priority level for the accepted interrupt is 7, the register’s value is set to 7. (d) The CPU increments the interrupt nesting counter INTNEST by 1. (e) The CPU jumps to the address given by adding the contents of address FFFF00H + the interrupt vector, then starts the interrupt processing routine. On completion of interrupt processing, the RETI instruction is used to return control to the main routine. RETI restores the contents of the Program Counter and the Status Register from the stack and decrements the Interrupt Nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU Interrupt Mask Register <IFF2:0>, the CPU will accept the interrupt. The CPU Interrupt Mask Register <IFF2:0> is then set to the value of the priority level for the accepted interrupt plus 1. If during interrupt processing, an interrupt is generated with a higher priority than the interrupt currently being processed, or if, during the processing of a non-maskable interrupt processing, a non-maskable interrupt request is generated from another source, the CPU will suspend the routine which it is currently executing and accept the new interrupt. When processing of the new interrupt has been completed, the CPU will resume processing of the suspended interrupt. If the CPU receives another interrupt request while performing processing steps (a) to (e), the new interrupt will be sampled immediately after execution of the first instruction of its interrupt processing routine. Specifying DI as the start instruction disables nesting of maskable interrupts. After a reset, initializes the Interrupt Mask Register <IFF2:0> to 111, disabling all maskable interrupts. Table 3.4.1 shows TMP92CD54I interrupt vectors and micro DMA start vectors. FFFF00H to FFFFEFH (240 bytes) is designated as the interrupt vector area.

Table 3.4.1 TMP92CD54I interrupt vectors and micro DMA start vectors (1/2) Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Address refer to Vector Micro DMA Start Vector

1 Reset or [SWI0] instruction 0000H FFFF00H

2 [SWI1] instruction 0004H FFFF04H

3 Illegal instruction or [SWI2] instruction 0008H FFFF08H

4 [SWI3] instruction 000CH FFFF0CH 5 [SWI4] instruction 0010H FFFF10H 6 [SWI5] instruction 0014H FFFF14H 7 [SWI6] instruction 0018H FFFF18H 8 [SWI7] instruction 001CH FFFF1CH

9 NMI: pin input 0020H FFFF20H

INTWD: Watchdog Timer 0024H FFFF24H - Micro DMA - - -

11 INT0: INT0 pin input (Note2) 0028H FFFF28H 0AH

12 INT1: INT1 pin input 002CH FFFF2CH 0BH

13 INT2: INT2 pin input 0030H FFFF30H 0CH

14 INT3: INT3 pin input 0034H FFFF34H 0DH

15 INT4: INT4 pin input 0038H FFFF38H 0EH

16 INT5: INT5 pin input 003CH FFFF3CH 0FH

17 INT6: INT6 pin input 0040H FFFF40H 10H

18 INT7: INT7 pin input 0044H FFFF44H 11H

19 INTT0: 8-bit timer 0 0048H FFFF48H 12H

20 INTT1: 8-bit timer 1 004CH FFFF4CH 13H

21 INTT2: 8-bit timer 2 0050H FFFF50H 14H

22 INTT3: 8-bit timer 3 0054H FFFF54H 15H

23 INTT4: 8-bit timer 4 0058H FFFF58H 16H

24 INTT5: 8-bit timer 5 005CH FFFF5CH 17H

25 INTT6: 8-bit timer 6 0060H FFFF60H 18H

26 INTT7: 8-bit timer 7 0064H FFFF64H 19H

27 INTTR8: 16-bit timer 8 0068H FFFF68H 1AH

28 INTTR9: 16-bit timer 8 006CH FFFF6CH 1BH

29 INTTRA: 16-bit timer A 0070H FFFF70H 1CH

30 INTTRB: 16-bit timer A 0074H FFFF74H 1DH

31 INTTO8: 16-bit timer 8 (overflow) 0078H FFFF78H 1EH

32 INTTOA: 16-bit timer A (overflow) 007CH FFFF7CH 1FH

33 INTRX0: Serial receive (Channel 0) 0080H FFFF80H 20H (Note3)

34 INTTX0: Serial transmission (Channel 0) 0084H FFFF84H 21H

35 INTRX1: Serial receive (Channel 1) 0088H FFFF88H 22H (Note3)

36 INTTX1: Serial transmission (Channel 1) 008CH FFFF8CH 23H

37 INTCR: CAN receive 0090H FFFF90H 24H (Note3)

38 INTCT: CAN transmission 0094H FFFF94H 25H (Note3)

39 INTCG: CAN global 0098H FFFF98H 26H (Note3)

40 INTSEM: SEI mode fault error 009CH FFFF9CH 27H (Note3)

41 INTSEE: SEI transfer end / slave error 00A0H FFFFA0H 28H (Note3)

42 INTSER: SEI receive 00A4H FFFFA4H 29H

43 INTSET: SEI transmission 00A8H FFFFA8H 2AH

44 INTRTC: Read Time Counter 00ACH FFFFACH 2BH

45 (reserved) 00B0H FFFFB0H -

46 INTSBE2: SBI I2CBUS transfer end (Channel 2) 00B4H FFFFB4H 2DH

47 INTSBS2: SBI I2CBUS stop condition (Channel 2) 00B8H FFFFB8H 2EH

48 INTSBE0: SBI I2CBUS transfer end (Channel 0) 00BCH FFFFBCH 2FH

49 INTSBS0: SBI I2CBUS stop condition (Channel 0) 00C0H FFFFC0H 30H

INTSBE1: SBI I2CBUS transfer end (Channel 1) 00C4H FFFFC4H 31H

Table 3.4.2 TMP92CD54I interrupt vectors and micro DMA start vectors (2/2) Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Address refer to Vector Micro DMA Start Vector

51 INTSBS1: SBI I2CBUS stop condition (Channel 1) 00C8H FFFFC8H 32H

52 INTAD: AD conversion end 00CCH FFFFCCH 33H

53 INTTC0: Micro DMA end (Channel 0) 00D0H FFFFD0H 34H

54 INTTC1: Micro DMA end (Channel 1) 00D4H FFFFD4H 35H

55 INTTC2: Micro DMA end (Channel 2) 00D8H FFFFD8H 36H

56 INTTC3: Micro DMA end (Channel 3) 00DCH FFFFDCH 37H

57 INTTC4: Micro DMA end (Channel 4) 00E0H FFFFE0H 38H

58 INTTC5: Micro DMA end (Channel 5) 00E4H FFFFE4H 39H

59 INTTC6: Micro DMA end (Channel 6) 00E8H FFFFE8H 3AH

60 INTTC7: Micro DMA end (Channel 7) 00ECH FFFFECH 3BH

(reserved) 00F0H 00FCH FFFFF0H FFFFFCH to Note1: Micro DMA default priority If an interrupt request is generated by micro DMA, the interrupt has a higher priority than any other maskable interrupt (irrespective of default channel priority). Note2: When standing-up micro DMA, set at edge detect mode. Note3: Micro DMA processing cannot be applied. Note4: This table mentions only the start address. Then each vector has 4 bytes.

3.4.2 Micro DMA processing

In addition to general-purpose interrupt processing, TMP92CD54I also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function has been implem ented with the cooperative operation of CPU, when CPU is a state of stand-by by HALT instruction, the requirement of micro DMA will be ignored (pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function in the following. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the Micro DMA Start Vector Register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte or two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a Micro DMA Transfer End interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (Channel 0 thus has the highest priority and Channel 7 the lowest). If an interrupt request is triggered on the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e. interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16M-bytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer mode s are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be increment ed or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, from I/O to I/O, and memory to memory. For details of the various transfer modes, see Section 3.4.2 (4), Detailed description of the Transfer Mode Register.

(3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr,r can be used to set these registers. Channel 0 DMAS0 DMA Source address register 0 DMAD0 DMA Destination address register 0 DMAC0 DMA Counter register 0 DMAM0 DMA Mode register 0 Channel 7 DMAS7 DMA Source address register 7 DMAD7 DMA Destination address register 7 DMAC7 DMA Counter register 7 DMAM7 DMA Mode register 7 8 bits 16 bits 32 bits

(4) Detailed description of the Transfer Mode Register 0 0 0 Mode DMAM0 to 7 DMAM[4:0] Mode Description Execution time 0 0 0 z z Destination INC mode (DMADn +) ← (DMASn) DMACn ← DMACn - 1 if DMACn = 0 then INTTCn 5states 0 0 1 z z Destination DEC mode (DMADn -) ← (DMASn) DMACn ← DMACn - 1 if DMACn = 0 then INTTCn 5states 0 1 0 z z Source INC mode (DMADn) ← (DMASn +) DMACn ← DMACn - 1 if DMACn = 0 then INTTCn 5states 0 1 1 z z Source DEC mode (DMADn) ← (DMASn -) DMACn ← DMACn – 1 if DMACn = 0 then INTTCn 5states 1 0 0 z z Source and Destination INC mode (DMADn +) ← (DMASn +) DMACn ← DMACn – 1 If DMACn = 0 then INTTCn 6states 1 0 1 z z Source and Destination DEC mode (DMADn -) ← (DMASn -) DMACn ← DMACn – 1 If DMACn = 0 then INTTCn 6states 1 1 0 z z Destination and Fixed mode (DMADn) ← (DMASn) DMACn ← DMACn – 1 If DMACn = 0 then INTTCn 5states Counter mode 1 1 1 z z DMASn ← DMASn + 1 DMACn ← DMACn – 1 If DMACn = 0 then INTTCn 5states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (reserved) Note1: The execution time is measured at 1states = 50ns (operation @internal 20 MHz) Note2: n stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn−/DMASn−: Post-decrement (register value is decremented after transfer)

3.4.3 Interrupt controller operation

The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 51 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a Reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writting a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently fo r each interrupt source by writing the priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). Six interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and Watchdog Timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt’s vector address to the CPU. The CPU compares the mask value set in <IFF2:0> of the Status Register (SR) with the priority level of the requested interrupt; if the latter is higher, the interrupt is accepted. Then the CPU sets SR <IFF2:0> to the priority level of the acce pted interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in SR <IFF2:0> (i.e. interrupts with a priority higher than the interrupt being processed) will be accepted. When interrupt processing has been completed (i.e. after execution of a RETI instruction), the CPU restores to SR<IFF2:0> the priority value which was saved on the stack before the interrupt was generated. The interrupt controller also includes eight registers which are used to store the micro DMA start vector. Writing the start vector of the interrup t source for the micro DMA processing (see Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter regist ers (e.g. DMAS and DMAD) prior to micro DMA processing.

if 1≦IFF2:0≦6 then 1. Micro DMA start vector setting register INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH Soft start Micro DMA Counter Zero Interrupt INTTC0 During IDLE1 1 7 3 3 8 input OR INT0 Micro DMA channel priority encoder Priority encoder DMA0V DMA1V DMA7V RESET Interrupt request F/F RESET Decoder Reset Priority setting register V = 20H V = 24H Interrupt controller CPU S Q R V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH D Q CLR A B C Dn Dn + 1 Dn + 2 Interrupt request F/F Interrupt vector read Micro DMA acknowledge Interrupt request F/F Dn + 3 A B C interrupt vector read Match Detect S Q R A B C Interrupt vector V read Interrupt mask F/F Micro DMA request HALT release NMI if INTRQ2:0≧IFF2:0 then 1. INTRQ2 to 0 IFF2:0 Interrupt level detect RESET EI 1 to 7 DI Interrupt request signal During STOP Micro DMA channel specification RESET NMI INTWD INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INTT0 INTT1 Interrupt vector generator Highest Priority interrupt level select D Q CLR Figure 3.4.3 Block Diagram of Interrupt Controller

(1) Interrupt priority setting registers Symbol NAME Address 7 6 5 4 3 2 1 0 INTAD INT0 (Note) IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0AD INT0 & INTAD Enable F0h 0 0 0 0 0 0 0 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W INTE12 INT1 & INT2 Enable D0h 0 0 0 0 0 0 0 0 INT4 INT3 I4C I4M2 I4M1 I4M0 I3C I3M2 I3M1 I3M0 R R/W R R/W INTE34 INT3 & INT4 Enable D1h 0 0 0 0 0 0 0 0 INT6 INT5 I6C I6M2 I6M1 I6M0 I5C I5M2 I5M1 I5M0 R R/W R R/W INTE56 INT5 & INT6 Enable D2h 0 0 0 0 0 0 0 0 INT7 - - - - I7C I7M2 I7M1 I7M0 R R/W INTE7 INT7 Enable D7h - - - - 0 0 0 0 INTT1(Timer1) INTT0(Timer0) IT1C IT1M2 IT1M1 IT1M0 IT0C IT0M2 IT0M1 IT0M0 R R/W R R/W INTET01 INTT0 & INTT1 Enable D4h 0 0 0 0 0 0 0 0 INTT3(Timer3) INTT2(Timer2) IT3C IT3M2 IT3M1 IT3M0 IT2C IT2M2 IT2M1 IT2M0 R R/W R R/W INTET23 INTT2 & INTT3 Enable D5h 0 0 0 0 0 0 0 0 INTT5(Timer5) INTT4(Timer4) IT5C IT5M2 IT5M1 IT5M0 IT4C IT4M2 IT4M1 IT4M0 R R/W R R/W INTET45 INTT4 & INTT5 Enable D6h 0 0 0 0 0 0 0 0 INTT7(Timer7) INTT6(Timer6) IT7C IT7M2 IT7M1 IT7M0 IT6C IT6M2 IT6M1 IT6M0 R R/W R R/W INTET67 INTT6 & INTT7 Enable D7h 0 0 0 0 0 0 0 0 INTTR9(Timer8) INTTR8(Timer8) IT9C IT9M2 IT9M1 IT9M0 IT8C IT8M2 IT8M1 IT8M0 R R/W R R/W INTET89 INTTR8 & INTTR9 Enable D8h 0 0 0 0 0 0 0 0 INTTRB(TimerA) INTTRA(TimerA) ITBC ITBM2 ITBM1 ITBM0 ITAC ITAM2 ITAM1 ITAM0 R R/W R R/W INTETAB INTTRA & INTTRB Enable D9h 0 0 0 0 0 0 0 0 INTTOA INTTO8 ITOAC ITOAM2 ITOAM1 ITOAM0 ITO8C ITO8M2 ITO8M1 ITO8M0 R R/W R R/W INTETO8A INTTO8 & INTTOA (Overflow) Enable DAh 0 0 0 0 0 0 0 0 Note: When any bit of WUPMASK<WMK7:0> is set to 1, INT0 will be disabled. Using INT0, set WUPMASK<WMK7:0> to “00H”.

Symbol NAME Address 7 6 5 4 3 2 1 0 INTTX0 INTRX0 ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 R R/W R R/W INTES0 INTRX0 & INTTX0 Enable DBh 0 0 0 0 0 0 0 0 INTTX1 INTRX1 ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0 R R/W R R/W INTES1 INTRX1 & INTTX1 Enable DCh 0 0 0 0 0 0 0 0 INTCT INTCR ICTC ICTM2 ICTM1 ICTM0 ICRC ICRM2 ICRM1 ICRM0 R R/W R R/W INTECRT INTCR & INTCT Enable DDh 0 0 0 0 0 0 0 0 INTCG - - - - ICGC ICGM2 ICGM1 ICGM0 R R/W INTECG INTCG Enable DEh - - - - 0 0 0 0* INTSEE0 INTSEM0 ISEE0C ISEE0M2 ISEE0M1 ISEE0M0 ISEM0C ISEM0M2 ISEM0M1 ISEM0M0 R R/W R R/W INTESEE0 INTSEM0 & INTSEE0 Enable DFh 0 0 0 0 0 0 0 0 INTSET0 INTSER0 ISET0C ISET0M2 ISET0M1 ISET0M0 ISER0C ISER0M2 ISER0M1 ISER0M0 R R/W R R/W INTESED0 INTSER0 & INTSET0 Enable E0h 0 0 0 0 0 0 0 0 INTRTC - - - - IRTCC IRTCM2 IRTCM1 IRTCM0 R R/W INTERTC INTRTC Enable E1h - - - - 0 0 0 0 INTSBS2 INTSBE2 ISBS2C ISBS2M2 ISBS2M1 ISBS2M0 ISBE2C ISBE2M2 ISBE2M1 ISBE2M0 R R/W R R/W INTESB2 INTSBE2 & INTSBS2 Enable E2h 0 0 0 0 0 0 0 0 INTSBS0 INTSBE0 ISBS0C ISBS0M2 ISBS0M1 ISBS0M0 ISBE0C ISBE0M2 ISBE0M1 ISBE0M0 R R/W R R/W INTESB0 INTSBE0 & INTSBS0 Enable E3h 0 0 0 0 0 0 0 0 INTSBS1 INTSBE1 ISBS1C ISBS1M2 ISBS1M1 ISBS1M0 ISBE1C ISBE1M2 ISBE1M1 ISBE1M0 R R/W R R/W INTESB1 INTSBE1 & INTSBS1 Enable E4h 0 0 0 0 0 0 0 0 INTTC1(DMA1) INTTC0(DMA0) ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R/W R R/W INTETC01 INTTC0 & INTTC1 Enable F1h 0 0 0 0 0 0 0 0 INTTC3(DMA3) INTTC2(DMA2) ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R/W R R/W INTETC23 INTTC2 & INTTC3 Enable F2h 0 0 0 0 0 0 0 0 INTTC5(DMA5) INTTC4(DMA4) ITC5C ITC5M2 ITC5M1 ITC5M0 ITC4C ITC4M2 ITC4M1 ITC4M0 R R/W R R/W INTETC45 INTTC4 & INTTC5 Enable F3h 0 0 0 0 0 0 0 0 INTTC7(DMA7) INTTC6(DMA6) ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R/W R R/W INTETC67 INTTC6 & INTTC7 Enable F4h 0 0 0 0 0 0 0 0

Symbol NAME Address 7 6 5 4 3 2 1 0 NMI INTWD INMIC - - - IWDC - - - R R INTNMWDT NMI & INTWD Enable F7h 0 - - - 0 - - - lxxM2 LxxM1 lxxM0 Function ( write ) 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests Note: After executing DI command previously, the setting value of “Interrupt priority setting register” should change. (2) External interrupt control Symbol NAME Address 7 6 5 4 3 2 1 0 - - - - - - I0LE NMIREE R/W - - - - - - 0 0 IIMC Interrupt Input Mode Control F6H (no RMW) I N T 0 m o d e 0:edge mode 1:level mode NMI mode 0:Falling edge 1:Falling & rising edges INT0 Level Enable

0 Rising edge detect INT

1 “H”level INT NMI rising edge Enable

0 INT request generation at falling edge

1 INT request generation at rising and falling edge

Note 1 : Disable INT0 request before changing INT0 pin mode from level-sense to edge-sense. Then, execute EI instruction after waiting 3-cycles (3 times NOP instruction). Setting example: DI ; Disable interrupts LD (IIMC), XXXXXX0-B ; Switches from level to edge. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP ; Wait 3-cycles NOP NOP EI ; Enable interrupts Note: X = Don’t care; “-“ = No change Note 2 : See electrical characteristics in section 4 for external interrupt input pulse width. Interrupt request flag

Table 3.4.2 Settings of External interrupt Pin Function Interrupt Pin name Mode Setting method Falling Edge IIMC<NMIREE> = 0 NMI NMI Falling and Rising Edges IIMC<NMIREE> = 1 Rising Edge IIMC<I0LE> = 0 INT0 INT0 High Level IIMC<I0LE> = 1 INT1 PC0 Rising Edge - INT2 PC2 Rising Edge - INT3 PC3 Rising Edge - INT4 PC5 Rising Edge - Rising Edge TMOD8<CAP89M1:0> = 0,0 or 0,1 or 1,1 INT5 PD0 Falling Edge TMOD8<CAP89M1:0> = 1,0 INT6 PD1 Rising Edge - Rising Edge TMODA<CAPABM1:0> = 0,0 or 0,1 or 1,1 INT7 PD4 Falling Edge TMODA<CAPABM1:0> = 1,0 Falling and Rising Edges WUPMOD<WMD0> = 0 Falling Edge WUPMOD<WMD0> = 1 and WUPEDGE<WED0> = 0 WUINT0 PD0 Rising Edge WUPMOD<WMD0> = 1 and WUPEDGE<WED0> = 1 Falling and Rising Edges WUPMOD<WMD1> = 0 Falling Edge WUPMOD<WMD1> = 1 and WUPEDGE<WED1> = 0 WUINT1 PD1 Rising Edge WUPMOD<WMD1> = 1 and WUPEDGE<WED1> = 1 Falling and Rising Edges WUPMOD<WMD2> = 0 Falling Edge WUPMOD<WMD2> = 1 and WUPEDGE<WED2> = 0 WUINT2 PD2 Rising Edge WUPMOD<WMD2> = 1 and WUPEDGE<WED2> = 1 Falling and Rising Edges WUPMOD<WMD3> = 0 Falling Edge WUPMOD<WMD3> = 1 and WUPEDGE<WED3> = 0 WUINT3 PD3 Rising Edge WUPMOD<WMD3> = 1 and WUPEDGE<WED3> = 1 Falling and Rising Edges WUPMOD<WMD4> = 0 Falling Edge WUPMOD<WMD4> = 1 and WUPEDGE<WED4> = 0 WUINT4 PD4 Rising Edge WUPMOD<WMD4> = 1 and WUPEDGE<WED4> = 1 Falling and Rising Edges WUPMOD<WMD5> = 0 Falling Edge WUPMOD<WMD5> = 1 and WUPEDGE<WED5> = 0 WUINT5 PD5 Rising Edge WUPMOD<WMD5> = 1 and WUPEDGE<WED5> = 1 Falling and Rising Edges WUPMOD<WMD6> = 0 Falling Edge WUPMOD<WMD6> = 1 and WUPEDGE<WED6> = 0 WUINT6 PD6 Rising Edge WUPMOD<WMD6> = 1 and WUPEDGE<WED6> = 1 Falling and Rising Edges WUPMOD<WMD7> = 0 Falling Edge WUPMOD<WMD7> = 1 and WUPEDGE<WED7> = 0 WUINT7 PD7 Rising Edge WUPMOD<WMD7> = 1 and WUPEDGE<WED7> = 1

(3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH ; Clears interrupt request flag INT0. Symbol NAME Address 7 6 5 4 3 2 1 0 - - - - - - - - W 0 0 0 0 0 0 0 0 INTCLR Interrupt Clear control F8H (no RMW) Interrupt Vector (4) Micro DMA start vector registers These registers assign an interrupt source wh ich makes a micro DMA processing start. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel’s micro DMA start vector register agai n, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.)

Symbol NAME Address 7 6 5 4 3 2 1 0 DMA0 Start Vector - - DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W DMA0V DMA0 Start Vector 100h (no RMW) - - 0 0 0 0 0 0 DMA1 Start Vector - - DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W DMA1V DMA1 Start Vector 101h (no RMW) - - 0 0 0 0 0 0 DMA2 Start Vector - - DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 R/W DMA2V DMA2 Start Vector 102h (no RMW) - - 0 0 0 0 0 0 DMA3 Start Vector - - DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R/W DMA3V DMA3 Start Vector 103h (no RMW) - - 0 0 0 0 0 0 DMA4 Start Vector - - DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0 R/W DMA4V DMA4 Start Vector 104h (no RMW) - - 0 0 0 0 0 0 DMA5 Start Vector - - DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R/W DMA5V DMA5 Start Vector 105h (no RMW) - - 0 0 0 0 0 0 DMA6 Start Vector - - DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R/W DMA6V DMA6 Start Vector 106h (no RMW) - - 0 0 0 0 0 0 DMA7 Start Vector - - DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R/W DMA7V DMA7 Start Vector 107h (no RMW) - - 0 0 0 0 0 0 (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the Transfer Counter Register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol NAME Address 7 6 5 4 3 2 1 0 DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0 R/W DMAB DMA Burst 108h (no RMW) 0 0 0 0 0 0 0 0

(6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be preceded by a DI instruction. In addition, please note that the following two circuits are exceptional and demand special attention. In Level Mode INT0 is not an edge-triggered interrupt. Hence, in Level Mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from Edge Mode to Level Mode, the interrupt request flag is cleared automatically. INT0 Level Mode If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to Level Mode so as to release a Halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the Halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the Halt state has been released.) When the mode changes from Level Mode to Edge Mode, interrupt request flags which were set in Level Mode will not be cleared. Interrupt request flags must be cleared using the following sequence. Also EI instruction should be execuse after waiting 3-cycle. DI LD (IIMC), 00H ; Switches from level to edge. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP ; Wait 3-cycle NOP NOP EI INTRX The interrupt request flip-flop can only be cleared by a Reset or by reading the Serial Channel Receive Buffer. It cannot be cleared by an instruction. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0: Instructions which switch to Level Mode after an interrupt request has been generated in Edge Mode. The pin input changes from High to Low after an interrupt request has been generated in INTRX: Instructions which read the Receive Buffer

3.4.4 Interrupt Mask register

TMP92CD54I has Interrupt Mask registers. Unlike Interrupt priority register, Interrupt mask register only disables or enables interrupts. An interrupt will not be generated, if the interrupt is disabled by Interrupt mask register, even if th e interrupt has been enabled by setting Interrupt priority register. One, two or more interrupt fact ors can be prohibited synchronous by setting of Interrupt Mask register. After reset, all bits in Interrupt mask register are initialize 1 (enabled interrupts). It is necessary to write 0 in the corresponding bit in case of making interrupt Mask register to prohibit interrupt. Figure 3.4.4 Block Diagram of Interrupt Mask Control Symbol NAME Address 7 6 5 4 3 2 1 0 MKI7 MKI6 MKI5 MKI4 MKI3 MKI2 MKI1 MKI0 R/W 1 1 1 1 1 1 1 1 INTMK0 Interrupt Mask Control 0 E5H INT7 0: Mask 1: Enable INT6 0: Mask 1: Enable INT5 0: Mask 1: Enable INT4 0: Mask 1: Enable INT3 0: Mask 1: Enable INT2 0: Mask 1: Enable INT1 0: Mask 1: Enable INT0 0: Mask 1: Enable MKIT7 MKIT6 MKIT5 MKIT4 MKIT3 MKIT2 MKIT1 MKIT0 R/W 1 1 1 1 1 1 1 1 INTMK1 Interrupt Mask Control 1 E6H INTT7 0: Mask 1: Enable INTT6 0: Mask 1: Enable INTT5 0: Mask 1: Enable INTT4 0: Mask 1: Enable INTT3 0: Mask 1: Enable INTT2 0: Mask 1: Enable INTT1 0: Mask 1: Enable INTT0 0: Mask 1: Enable - MKIRTC MKITOA MKITO8 MKITRB MKITRA MKITR9 MKITR8 R/W - 1 1 1 1 1 1 1 INTMK2 Interrupt Mask Control 2 E7H INTRTC 0: Mask 1: Enable INTTOA 0: Mask 1: Enable INTTO8 0: Mask 1: Enable INTTRB 0: Mask 1: Enable INTTRA 0: Mask 1: Enable INTTR9 0: Mask 1: Enable INTTR8 0: Mask 1: Enable TMR SIO I2C CAN Interrupt Mask registers MASK INTC Interrupt Signals Internal I/O & external interrupts (except NMI, INTWD, INTTC0 to 7) Data Bus Address Bus

Symbol NAME Address 7 6 5 4 3 2 1 0 - MKICG MKICT MKICR MKITX1 MKIRX1 MKITX0 MKIRX0 R/W - 1 1 1 1 1 1 1 INTMK3 Interrupt Mask Control 3 E8H INTCG 0: Mask 1: Enable INTCT 0: Mask 1: Enable INTCR 0: Mask 1: Enable INTTX1 0: Mask 1: Enable INTRX1 0: Mask 1: Enable INTTX0 0: Mask 1: Enable INTRX0 0: Mask 1: Enable - - - - MKISET0 MKISER0 MKISEE0 MKISEM0 R/W - - - - 1 1 1 1 INTMK4 Interrupt Mask Control 4 E9H I N T S E T 0: Mask 1: Enable INTSER 0: Mask 1: Enable INTSEE 0: Mask 1: Enable INTSEM 0: Mask 1: Enable - MKISBS2 MKISBE2 MKIAD MKISBS1 MKISBE1 MKISBS0 MKISBE0 R/W - 1 1 1 1 1 1 1 INTMK5 Interrupt Mask Control 5 EAH INTSBS2 0: Mask 1: Enable INTSBE2 0: Mask 1: Enable INTAD 0: Mask 1: Enable INTSBS1 0: Mask 1: Enable INTSBE1 0: Mask 1: Enable INTSBS0 0: Mask 1: Enable INTSBE0 0: Mask 1: Enable Maskable bit for INTAD request

0 INTAD is disabled

1I N T A D i s e n a b l e d Note: Port D0, D1 and D4 have 2 kinds of interrupt source (PD0:INT5/WUINT0, PD1:INT6/WUINT1, PD4:INT7/WUINT4). If both interrupt requests are generated in both interrupt enabled status, both interrupt processing will be executed. When any of these interrupts is used, set Interrupt Mask register or Wake UP Mask register to enable/disable. Example of register setting: In the case of setting INT0 interrupt priority level to 7 from 3. LD (INTE0AD), 03H ; Set INT0 level to 3 LD (INTMK0), 01H ; Enable INT0 EI ; Enable interrupt operation : ; running program DI ; Disable interrupt operation LD (INTMK0), 00H ; Disable INT0 LD (INTE0AD), 07H ; Set INT0 level to 7 LD (INTCLR), 0AH ; Clear INT0 request NOP ; Wait 3 cycles NOP NOP LD (INTMK0), 01H ; Enable INT0 EI ; Enable interrupt operation

3.4.5. ON/OFF LOGIC TMP92CD54I has 8 pins (WUINT0 to WUINT7) for wake up from standby mode. These pins are multiplexed with Port D (PD0 to PD7). All wake up events can release standby mode and triggering edge can be independently programmable as both rising and falling edge, rising edge or falling edge. It is possible to mask all wake up events independently. Figure 3.4.5 Block diagram of ON/OFF logic Using ON/OFF logic, all interrupt signals of WUINT0 to 7 are sent to INT0 in internal logic. When any WUINTn requests are generated, INT0 interrupt request will be generated. Like external INT0, also INT0 from WUINTn is set di sable/enable by Interrupt priority register or Interrupt mask register. Writing 1 to any bit in WUPMASK register, INT0 switches ON/OFF logic mode. In this case, WUINTn written 1 in WUPMASK register are enabled, external INT0 cannot use. When external INT0 is used, write 00 to WUPMASK register. Selection edge of WUINTn signal uses WUPMOD and WUPEDGE register, rising edge, falling edge or both falling and rising edge are selectable. Reading WUPFLAG register, request/no-request of WUINTn will be confirmed. Edge select & Interrupt Mask Mask Register Edge select register Flag status register WUINT0 WUINT7 Interrupt Controller Clock Control etc. A B Selector S INT0 8OR WUINT1 WUINT2 WUINT3 WUINT4 WUINT5 WUINT6 External Interrupts INT0 8OR INTMK0<MKI0> Mode control register Internal bus

Wake UP FLAG status Register 7 6 5 4 3 2 1 0 Symbol WFLG7 WFLG6 WFLG5 WFLG4 WFLG3 WFLG2 WFLG1 WFLG0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 function WUINT7 0:NO request 1: request WUINT6 0:NO request 1: request WUINT5 0:NO request 1: request WUINT4 0:NO request 1: request WUINT3 0:NO request 1: request WUINT2 0:NO request 1: request WUINT1 0:NO request 1: request WUINT0 0:NO request 1: request Wake UP Mode Control Register 7 6 5 4 3 2 1 0 Symbol WMD7 WMD6 WMD 5 WMD4 WMD3 WMD2 WMD1 WMD0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 function WUINT7 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT6 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT5 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT4 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT3 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT2 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT1 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT0 0:Falling & Rising Edge 1:Falling or Rising Edge Wake UP Edge Select Register 7 6 5 4 3 2 1 0 Symbol WED7 WED6 WED 5 WED4 WED3 WED2 WED1 WED0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 function WUINT7 0:Falling Edge 1:Rising Edge WUINT6 0:Falling Edge 1:Rising Edge WUINT5 0:Falling Edge 1:Rising Edge WUINT4 0:Falling Edge 1:Rising Edge WUINT3 0:Falling Edge 1:Rising Edge WUINT2 0:Falling Edge 1:Rising Edge WUINT1 0:Falling Edge 1:Rising Edge WUINT0 0:Falling Edge 1:Rising Edge Note: WUPEDGE register is used with setting each WUPMOD<WMD7:0> to 1. If each WUPMOD<WMD7:0> is clear to 0, WUPEDGE<WED7:0> is disabled. Wake UP Mask Register 7 6 5 4 3 2 1 0 Symbol WMK7 WMK6 WMK5 WMK4 WMK3 WMK2 WMK1 WMK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 function WUINT7 0: Disable 1: Enable WUINT6 0: Disable 1: Enable WUINT5 0: Disable 1: Enable WUINT4 0: Disable 1: Enable WUINT3 0: Disable 1: Enable WUINT2 0: Disable 1: Enable WUINT1 0: Disable 1: Enable WUINT0 0: Disable 1: Enable Wake up interrupt mask control

0 WUINTn Disabled (MASK)

1 WUINTn Enabled

Note1: Port D0, D1 and D4 have 2 kinds of interrupt source (PD0: INT5/WUINT0, PD1: INT6/WUINT1, PD4:INT7/WUINT4). If both interrupt requests are generated in both interrupt enabled status, both interrupt processing will be executed. When each interrupts is used, set Interrupt Mask register or Wake UP Mask register to enable/disable. Even if port D is any of Input/Output port, INTn, and WUINTn, the level of port D is inputted into these interrupts. For details, refer to the block diagram of the port. Note2: When any WUPMASK<WMK7:0> is set to 1, external INT0 will be disabled. Using INT0, set WUPMASK<WMK7:0> to “00H”. WUPFLAG (00ECH) WUPEDGE (00EEH) WUPMASK (00EFH) WUPMOD (00EDH)

Example of register setting: To set WUINT0 with rising edge and set interrupt level 3, set the registers as follows: DI ; Disable interrupt operation LD (INTMK0), 00H ; Disable INT0 LD (PDFC), 00H ; Set PD0 as port mode LD (PDCR), 00H ; Set PD0 as input mode LD (WUPMOD), 01H ; Set WUINT0 as “Falling or rising edge” LD (WUPEDGE), 01H ; Set WUINT0 to “Rising edge” LD (WUPFLAG), 00H ; Clear WUINT0 flag LD (INTE0AD), 03H ; Set INT0 (function as WUINT0) interrupt level to 3 LD (INTCLR), 0AH ; Clear INT0 request flag NOP ; Wait 3 cycles NOP NOP LD (INTMK0), 01H ; Enable WUINT0 EI ; Enable interrupt operation

3.5 Function of Ports

TMP92CD54I has I/O port pins that are shown in table 3.5.1. In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.5.1 Port Functions (1/2) Port Name Pin Name Number of Pins I/O I/O Setting Pin Name for built-in function Port 0 P00 to P07 8 I/O Bit D0 to D7 Port 4 P40 to P47 8 I/O Bit A0 to A7 P70 1 I/O Bit RD P71 1 I/O Bit WR P72 1 I/O Bit SI2/SCL2 P73 1 I/O Bit CS P74 1 I/O Bit Port 7 P75 1 I/O Bit WAIT PC0 1 I/O Bit TI0 / INT1 PC1 1 I/O Bit TO1 PC2 1 I/O Bit TO3 / INT2 PC3 1 I/O Bit TI4 / INT3 PC4 1 I/O Bit TO5 Port C PC5 1 I/O Bit TO7 / INT4 PD0 1 I/O Bit TI8 / INT5 / A16 / WUINT0 PD1 1 I/O Bit TI9 / INT6 / A17 / WUINT1 PD2 1 I/O Bit TO8 / A18 / WUINT2 PD3 1 I/O Bit TO9 / A19 / WUINT3 PD4 1 I/O Bit TIA / INT7 / A20 / WUINT4 PD5 1 I/O Bit TIB / A21 / WUINT5 PD6 1 I/O Bit TOA / A22 / WUINT6 Port D PD7 1 I/O Bit TOB / A23 / WUINT7 PF0 1 I/O Bit TXD0 PF1 1 I/O Bit RXD0 PF2 1 I/O Bit SCLK0 / CTS0 PF3 1 I/O Bit TXD1 PF4 1 I/O Bit RXD1 PF5 1 I/O Bit SCLK1 / CTS1 PF6 1 I/O Bit TX Port F PF7 1 I/O Bit RX Port G PG0 to PG7 8 Input (Fixed) AN0 to AN7 Port L PL0 to PL3 4 Input (Fixed) AN8 to AN11 PM0 1 I/O Bit SS / A8 PM1 1 I/O Bit MOSI / A9 PM2 1 I/O Bit MISO / A10 PM3 1 I/O Bit SECLK / A11 Port M PM4 1 I/O Bit SCK2 PN0 1 I/O Bit SCK0 PN1 1 I/O Bit SO0 / SDA0 PN2 1 I/O Bit SI0 / SCL0 PN3 1 I/O Bit SCK1 / A12 PN4 1 I/O Bit SO1 / SDA1 / A13 PN5 1 I/O Bit SI1 / SCL1 / A14 Port N PN6 1 I/O Bit SO2 / SDA2 / A15

3.5.1 Port 0 (P00 to P07)

Port0 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P0CR and function register P0FC. In addition to functioning as a general-purpose I/O port, port0 can also function as a data bus (D0 to D7). SYMBOL NAME Address 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 R/W 0 0 0 0 0 0 0 0 P0 PORT0 00H Input/Output P07C P06C P05C P04C P03C P02C P01C P00C W 0 0 0 0 0 0 0 0 P0CR PORT0 Control Register 02H (no RMW) 0:Input 1:Output - - - - - - - P0F W

0 P0FC

(no RMW) 0:PORT 1:Data Bus(D7 to D0) P 0 F C < P 0 F > P0CR<P0xC> 0 1

0 Input port Data bus

(D0 to D7)

1 Output port Data bus

(D0 to D7) Table 3.5.2 Port0 Registers Figure 3.5.1 Port0 P0CR register P0FC register P0 register S Selector S 1 Selector External write strobe External write data Port read data External read data Port 0 P00 to P07 (D0 to D7) External read strobe

3.5.2 Port 4 (P40 to P47)

Port4 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC. In addition to functioning as a general-purpose I/O port, port4 can also function as an address bus (A0 to A7). SYMBOL NAME Address 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 R/W 0 0 0 0 0 0 0 0 P4 PORT4 10H Input/Output P47C P46C P45C P44C P43C P42C P41C P40C W 0 0 0 0 0 0 0 0 P4CR PORT4 Control Register 12H (no RMW) 0:Input 1:Output P47F P46F P45F P44F P43F P42F P41F P40F W 0 0 0 0 0 0 0 0 P4FC PORT4 Function Register 13H (no RMW) 0:PORT 1:Address Bus(A0 to A7) P 4 F C < P 4 x F > P4CR<P4xC> 0 1

0 Input port Address bus

(A0 to A7)

1 Output port Don’t use this

setting. Table 3.5.3 Port4 Registers Figure 3.5.2 Port4 P4CR register P4FC register P4 register S Selector S 1 Selector (reserved) Port read data Port4 P40 to P47 (A0 to A7) S Selector (reserved) Address bus (reserved) (reserved)

3.5.3 Port 7 (P70 to P75)

Port7 is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70, P71 and P73 pins can also function as read/write strobe signals and chip selection to connect with an external memory. P72 pin can also function as I/O functions of serial bus interface which employs clocked-synchronous 8-bit SIO and I 2C. P75 pin can also function as wait input. The pin is always enabled for the following input signals: SBI data input (SIO) SI2#1, SBI clock I/O (I2C) SCL2#1,. #1 : In IDLE3/STOP mode, input signal is valid (Input gate opened) A reset initializes P70, P71, P73 and P74 pins to output port mode, and P72, P75 pin to input port mode. Figure 3.5.3 Port7 (P70 to P72) P7 register S Selector S 1 Selector Port read data P71 ( WR ) Write strobe P7CR register P7FC register P72 (SI2/SCL2) P7CR register P7FC register P7 register S Selector S 1 Selector Port read data S Selector (reserved) SI/SCL input When PNODE register is “1”, P72 signal is open drain output. SCL output P7 register S0 Selector S 1 Selector Port read data P70 (RD ) Read strobe P7CR register P7FC register

Figure 3.5.4 Port7 (P73 to P75) P7 register S Selector S 1 Selector Port read data P73 (CS ) Chip selection P7CR register P7FC register P7 register S Selector S 1 Selector Port read data P74 (reserved) P7CR register P7FC register Port read data P7 register S 1 SelectorWait request P75 ( WAIT ) P7CR register P7FC register

Table 3.5.4 Port7 Registers SYMBOL NAME Address 7 6 5 4 3 2 1 0 - - P75 P74 P73 P72 P71 P70 R/W - - 0 1 1 1 1 1 P7 PORT7 1CH Input/Output - - P75C P74C P73C P72C P71C P70C W - - 0 1 1 0 1 1 P7CR PORT7 Control Register 1EH (no RMW) 0:Input 1:Output - - P75F P74F P73F P72F P71F P70F W - - 0 0 0 0 0 0 P7FC PORT7 Function Register 1FH (no RMW) 0:PORT WAIT 0:PORT 0:PORT 1:CS 0:PORT 1:SI2 SCL2 Note1 0:PORT 1:WR 0:PORT 1:RD P7CR P7FC - - P75 P74 P73 P72 P71 P70 0 0 Input Port Input Port, SI2 Input Port 1 0 Output Port 1 1 WAIT Don’t use this setting. CS Don’t use this setting. WR RD 0 1 WAIT Don’t use this setting. CS SI2, SCL2 WR RD Note1: P72 SCL2, clock input/output at I2C mode, can be open-drain output by setting 1 to PNODE<ODE72>.

3.5.4 Port C (PC0 to PC5)

PortC is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PCCR and function register PCFC. In addition to functioning as a general-purpose I/O port, PortC can also function as 8-bit timer I/O and interrupt input. The pin is always enabled for the following input signals: timer inputs TI0#1, TI4#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortC to input port mode. PC4 (TO5) PC5 (TO7/INT4) Figure 3.5.5 PortC (PC0 to PC5) PC register Port read data Timer input PC0 (TI0/INT1) PC3 (TI4/INT3) (Reserved) S 1 PCCR register PCFC register S Interrupt request PC1 (TO1) PC2 (TO3/INT2) PC register PCCR register PCFC register S (Reserved) Port read data Timer output S 1 Interrupt request S PC register PCCR register PCFC register S 1Timer output Port read data S 1 Interrupt request

Table 3.5.5 PortC Registers SYMBOL NAME Address 7 6 5 4 3 2 1 0 - - PC5 PC4 PC3 PC2 PC1 PC0 R/W - - 0 0 0 0 0 0 PC PORTC 30H Input/Output - - PC5C PC4C PC3C PC2C PC1C PC0C W - - 0 0 0 0 0 0 PCCR PORTC Control Register 32H (no RMW) 0:Input 1:Output - - PC5F PC4F PC3F PC2F PC1F PC0F W - - 0 0 0 0 0 0 PCFC PORTC Function Register 33H (no RMW) 0:PORT I N T 4 1:TO7 0:PORT 1:TO5 0:PORT INT3 TI4 0:PORT INT2 1:TO3 0:PORT 1:TO1 0:PORT INT1 TI0 PCCR PCFC - - PC5 PC4 PC3 PC2 PC1 PC0 0 0 Input Port, INT4 Input Port Input Port, INT3, TI4 Input Port, INT2 Input Port Input Port, INT1, TI0 1 0 Output Port 1 1 TO7 TO5 Output Port TO3 TO1 Output Por t 0 1 TO7 TO5 Do not use this setting

3.5.5 Port D (PD0 to PD7)

PortD is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PDCR and function register PDFC. In addition to functioning as a general-purpose I/O port, PortD can also function as 16-bit timer I/O, interrupt input and wake up interrupt input. The pin is always enabled (excluding address bus setting) for the following input signals: 16-bit timer input TI8#1, TI9#1, TIA#1, TIB#1, external interrupt INT5#2 to INT7#2, wake up interrupt WUINT0#2 to WUINT7#2. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) #2 : In IDLE3/STOP mode, input signal is valid (Input gate opened) A reset initializes Port D to input port mode. Figure 3.5.6 PortD Interrupt request Timer input PD0 (TI8/INT5/A16/WUINT0) PD1 (TI9/INT6/A17/WUINT1) PD4 (TIA/INT7/A20/WUINT4) PD5 (TIB/A21/WUINT5) PDCR register PDFC register PD register S Selector S 1 Selector Address bus Port read data Wake up request PD2 (TO8/A18/WUINT2) PD3 (TO9/A19/WUINT3) PD6 (TOA/A22/WUINT6) PD7 (TOB/A23/WUINT7) S Selector S 1 Selector Port read data S Selector Timer output Address bus Wake up request PDCR register PDFC register PD register

Table 3.5.6 PortD Registers SYMBOL NAME Address 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 R/W 0 0 0 0 0 0 0 0 PD PORTD 34H Input/Output PD7C PD6C PD5C PD4C PD3C PD2C PD1C PD0C W 0 0 0 0 0 0 0 0 PDCR PORTD Control Register 36H (no RMW) 0:Input 1:Output PD7F PD6F PD5F PD4F PD3F PD2F PD1F PD0F W 0 0 0 0 0 0 0 0 PDFC PORTD Function Register 37H (no RMW) 0:PORT WUINT7 1:TOB A23 0:PORT WUINT6 1:TOA A22 0:PORT TIB WUINT5 1:A21 0:PORT TIA INT7 WUINT4 1:A20 0:PORT WUINT3 1:TO9 A19 0:PORT WUINT2 1:TO8 A 1 8 0:PORT TI9 INT6 WUINT1 1:A17 0:PORT TI8 INT5 WUINT0 1: A16 PDCR PDFC PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 Input Port, WUINT7 Input Port, WUINT6 Input Port, TIB, WUINT5 Input Port, INT7, TIA, WUINT4 Input Port, WUINT3 Input Port, WUINT2 Input Port, INT6, TI9, WUINT1 Input Port, INT5, TI8, WUINT0 1 0 Output Port 1 1 TOB TOA, TIB, WUINT5 TIA, INT7, WUINT4 TO9 TO8 TI9, INT6, WUINT1 TI8, INT5, WUINT0 0 1 A23 A22 A21 A20 A19 A18 A17 A16 Note: Port D0, D1 and D4 have 2 kinds of interrupt source (PD0: INT5/WUINT0, PD1: INT6/WUINT1, PD4: INT7/WUINT4). If both interrupt requests are generated in both interrupt enabled status, both interrupt processing are executed. When each interrupts is used, set Interrupt Mask register or Wake UP Mask register to enable/disable. If these ports are used as output/input ports, first, disable interrupt request, then set PDFC and PDCR (cf Timers).

3.5.6 Port F (PF0 to PF7)

PortF is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or o outputs by control register PFCR and function register PFFC. In addition to functioning as a general-purpose I/O port, PortF can also function as serial channels I/O function and controller area network (CAN). The pin is always enabled for the following input signals: serial receive data RXD0#1, RXD1#1, CAN receive data RX#1, Clear-to-send CTS0#1, CTS1#1, and serial clock SCLK0#1, SCLK1#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortF to input port mode. Figure 3.5.7 PortF (PF0, PF3, PF6) When PFCR register is “0” and PFFC register is “1”, TXD is open drain output. PFCR register PFFC register PF register S Selector S 1 Selector TXD output Port read data PF0 (TXD0) PF3 (TXD1) PFCR register PFFC register PF register S Selector S 1 Selector TX output Port read data PF6 (TX)

(SCLK0/CTS0) PF5 (SCLK1/CTS1) Figure 3.5.8 PortF (PF1, PF2, PF4, PF5, PF7) PFCR register PFFC register PF register S Selector S 1 Selector Port read data S Selector SCLK output (reserved) SCLK input CTS input PF register S 1 Selector Port read data RXD input PF1 (RXD0) PF4 (RXD1) PF7 (RX) PFCR register PFFC register

Table 3.5.9 PortF Registers SYMBOL NAME Address 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 R/W 0 0 0 0 0 0 0 0 PF PORTF 3CH Input/Output PF7C PF6C PF5C PF4C PF3C PF2C PF1C PF0C W 0 0 0 0 0 0 0 0 PFCR PORTF Control Register 3EH (no RMW) 0:Input 1:Output PF7F PF6F PF5F PF4F PF3F PF2F PF1F PF0F W 0 0 0 0 0 0 0 0 PFFC PORTF Function Register 3FH (no RMW) 0:PORT 1:RX 0:PORT 1:TX 0:PORT CTS1 1:SCLK1 0:PORT 1:RXD1 0:PORT 1:TXD1 0:PORT CTS0 1:SCLK0 0:PORT 1:RXD0 0:PORT 1:TXD0 PFCR PFFC PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 0 0 Input Port, RX Input Port Input Port, SCLK1 (Input), CTS1 Input Port, RXD1 Input Port Input Port, SCLK0 (Input), CTS0 Input Port, RXD0 Input Port 1 0 Output Port 1 1 RX TX SCLK1 (Output) RXD1 TXD1 SCLK0 (Output) RXD0 TXD0 0 1 RX TX Don’t use this Setting. RXD1 TXD1 (Open Drain) Don’t use this Setting. RXD0 TXD0 (Open Drain)

3.5.7 Port G (PG0 to PG7)

PortG is an 8-bit general-purpose input-only port. In addition to functioning as a general-purpose input-only port, PortG can also function as input functions of AD converter. The pin is always enabled for the following input signals: AD converter input AN0#1 to AN7#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) SYMBOL NAME Address 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 R PG PORTG 40H Input Figure 3.5.9 PortG PortG PG0 to PG7 (AN0 to AN7) Port read data AD converter input Table 3.5.8 PortG Register

3.5.8 Port L (PL0 to PL3)

PortL is a 4-bit general-purpose input-only port. In addition to functioning as a general-purpose input-only port, PortL can also function as input functions of AD converter. The pin is always enabled for the following input signals: AD converter input AN8#1 to AN11#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) SYMBOL NAME Address 7 6 5 4 3 2 1 0 - - - - PL3 PL2 PL1 PL0 R PL PORTL 54H Input Figure 3.5.10 PortL PortL PL0 to PL3 (AN8 to AN11) Port read data AD converter input Table 3.5.9 PortL Register

3.5.9 Port M (PM0 to PM4)

PortM is a 5-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PMCR and function register PMFC. In addition to functioning as a general-purpose I/O port, PM0 to PM3 can also function as I/O functions of serial expansion interface. PM4 can also function as I/O function of serial bus interface which employs clocked-synchronous 8-bit SIO. The pin is always enabled for the following input signals: slave select SS #1, transmitting/ receiving serial data MOSI#1, MISO#1, SEI clock SECLK#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortM to input port mode. PMCR register PMFC register PM register S Selector S 1 Selector Address bus Port read data PM0 (SS /A8) SS input Figure 3.5.11 PortM (PM0 to PM3) When PMODE register is “1”, PM1 to PM3 signals are open drain output. PM1 (MOSI/A9) PM2 (MISO/A10) PM3 (SECLK/A11) PMCR register PMFC register PM register S Selector S 1 Selector Port read data S Selector Address bus MOSI input MISO input SECLK input MOSI, MISO, SECLK output enable SEI monitor MOSI output MISO output SECLK output

Figure 3.5.12 PortM (PM4) SYMBOL NAME Address 7 6 5 4 3 2 1 0 - - - PM4 PM3 PM2 PM1 PM0 R/W - - - 0 0 0 0 0 PM PORTM 58H Input/Output - - - - ODEM3 ODEM2 ODEM1 - R/W - - - - 0 0 0 - PMODE PORTM Open Drain Enable Register 59H P M 3 output 0:CMOS 1:Open D r a i n PM2 output 0:CMOS 1:Open Drain PM1 output 0:CMOS 1:Open Drain - - - PM4C PM3C PM2C PM1C PM0C W - - - 0 0 0 0 0 PMCR PORTM Control Register 5AH (no RMW) 0:Input 1:Output - - - PM4F PM3F PM2F PM1F PM0F W - - - 0 0 0 0 0 PMFC PORTM Function Register 5BH (no RMW) 0 : P O R T 1:SCK2 0:PORT 1:SECLK A11 0:PORT 1:MISO A10 0:PORT 1:MOSI 0:PORT 1:SS PMCR PMFC - - - PM4 PM3 PM2 PM1 PM0 0 0 - - - Input Port, SCK2 (Input) Input Port Input Port Input Port Input Port, SS 1 0 - Output Port 1 1 - - - SCK2 (Output) SECLK MISO MOSI SS 0 1 - - - Don’t use this setting A11 A10 A9 A8 Table 3.5.10 PortM Registers PMCR register PMFC register PM register S Selector S 1 Selector Port read data S Selector SCK output (reserved) SCK input PM4 (SCK2)

3.5.10 Port N (PN0 to PN6)

PortN is a 7-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PNCR and function register PNFC. In addition to functioning as a general-purpose I/O port, PortN can also function as I/O functions of serial bus interface which employs clocked-synchronous 8-bit SIO and I2C. The pin is always enabled for the following input signals: SBI clock I/O (SIO) SCK0#1, SCK1#1, SBI data input (SIO) SI0#1, SI1#1, SBI clock I/O (I2C) SCL0#1, SCL1#1, SBI data I/O (I2C) SDA0#1, SDA1#1, SDA2#1. #1 : In IDLE3/STOP mode, input signal is invalid (Input gate closed) A reset initializes PortN to input port mode. PN0 (SCK0) PN3 (SCK1/A12) PNCR register PNFC register PN register S Selector S 1 Selector Port read data S Selector SCK output Address bus SCK input PN1 (SO0/SDA0) PN2 (SI0/SCL0) PN4 (SO1/SDA1/A13) PN5 (SI1/SCL1/A14) PN6 (SO2/SDA2/A15) PNCR register PNFC register PN register S Selector S 1 Selector Port read data S Selector SO/SDA output SCL output Address bus SDA input SI/SCL input When PNODE register is “1”, PN1, PN2, PN4, PN5 and PN6 signals are open drain output. Figure 3.5.13 PortN

Table 3.5.11 PortN Registers SYMBOL NAME Address 7 6 5 4 3 2 1 0 - PN6 PN5 PN4 PN3 PN2 PN1 PN0 R/W - 0 0 0 0 0 0 0 PN PORTN 5CH Input/Output ODE72 ODEN6 ODEN5 ODEN4 - ODEN2 ODEN1 - R/W R/W 0 0 0 0 - 0 0 - PNODE PORTN Open Drain Enable Register 5DH P72 output 0:CMOS 1:Open Drain PN6 output 0:CMOS 1:Open D r a i n PN5 output 0:CMOS 1:Open Drain PN4 output 0:CMOS 1:Open Drain PN2 output 0:CMOS 1:Open Drain PN1 output 0:CMOS 1:Open D r a i n - PN6C PN5C PN4C PN3C PN2C PN1C PN0C W - 0 0 0 0 0 0 0 PNCR PORTN Control Register 5EH (no RMW) 0:Input 1:Output - PN6F PN5F PN4F PN3F PN2F PN1F PN0F W - 0 0 0 0 0 0 0 PNFC PORTN Function Register 5FH (no RMW) 0:PORT 1: SO2 SDA2 A15 0:PORT SI1 1:SCL1 A 1 4 0:PORT 1:SO1 SDA1 A13 0:PORT 1:SCK1 A12 0:PORT SI0 1:SCL0 0:PORT 1:SO0 S D A 0 0:PORT 1:SCK0 PNCR PNFC - PN6 PN5 PN4 PN3 PN2 PN1 PN0 0 0 - Input Port Input Port, SI1 Input Port Input Port, SCK1 (Input) Input Port, SI0 Input Port Input Port, SCK0 (Input) 1 0 - Output Port 1 1 - SO2/SDA2 SCL1 SO1/SDA1 SCK1 (Output) SCL0 SO0/SDA0 SCK0 (Output) 0 1 - A15 A14 A13 A12 Don’t use this setting.

3.6 Memory Controller

3.6.1 Memory controller functions

TMP92CD54I has a memory controller with a variable 1-block external address area. The function is as follows. (1) 1-block external address area support. It specifies: ・ A start address ・ A block size for 1-block external address area (2) Connecting memory specifications. It specifies: ・ SRAM ・ ROM as memories to connect with the selected address area. (3) Data bus size 8-bit (4) Wait control ・ Wait specification ・ Wait input pin Both control the number of waits in the external access bus cycle. Read and write cycles can specify the number of waits individually. There are five modes all together:

3.6.2 Control register and Operation after reset release

This section describes the registers that contro l the memory controller, the state after reset release and necessary settings. (1) Control Registers (2) Operation after reset release After reset release, ・ The block address areas (specified by MSAR and MAMR) are set to address 000000H and FFFFEFH. ・ Then BCSL / H is set. ・ Set BCSH<BE> to 1 to enable the setting. 0 wait, 1 wait, 2 wait, 3 wait, N wait (N is controlled with WAIT pin)

• Control registers (BCSH/BCSL: Block Chip Select High / Low) ・ Sets the connecting memory type. (SRAM, ROM) ・ Sets the number of waits to be read and written.
• Memory Start Address Register (MSAR) ・ Sets a start address in the selected address areas.
• Memory Address Mask Register (MAMR) ・ Sets a block size in the selected address areas.

3.6.3 Basic functions and registers setting

In this section, Block address area specification, wait control and basic bus sizing are described. (1) Block address area specification If the bit BCSH<BM> is set to 0, then the block address area is set to addresses 000000H to FFFFEFH, which disables the use of both registers MSAR and MAMR. If the bit BCSH<BM> is set to 1, then the block address area is programmable. Therefore, the start address is set using MSAR (Memory Start Address register). MAMR (Memory Address Mask Register) sets the size of the block in the selected address area. The principle is to mask or enable the comparison of each bit of the address. The combination of masked / enabled bits give the block size. Then the memory controller compares (every bus cycle) the register value and the address in order to check whether it is an access to the external memory or not. Note that an address bit masked by MAMR (Memory Address Mask Register) is not compared. If the compared result is a match the memory controller sets the chip select signal CS to low. Figure 3.6.1 shows an example of connecting external memory to TMP92CD54I. In the example, RAM is connected using an 8-bit bus. Figure 3.6.1 Example of connecting external memory (external RAM) CS WR RD Data (D0 to D7) Address TMP92CD54I RAM OE WE CS

(i) Setting memory start address register The MS23 to 16 bits of MSAR respectively correspond with addresses A23 to A16. The lower start address A15 to 0 is always set to address 0000H. Therefore, the start addresses of the block address area are set to addresses 000000H to FF0000H every 64KB (Because the settable LSB bit is 16 th; 216 = 64 KB) (ii) Setting memory address mask register MAMR sets whether an address bit is compared or not. Set the register to 0 to compare, or to 1 not to compare. The combination of masked / enabled bits give the block size and therefore the address bit to be set depends on the block address area. Note: A23 is always compared. Thus, the block address area is between A22 and A15. The size to be set depending on the block address area is as follows: Size (bytes) CS area 256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M Note: After reset release, BCSH<BM> (block address area specification) is set to ‘0’, and the block address area is set to addresses 000000H to FFFFEFH. Setting BCSH<BM> to “1” specifies the start address (using MSAR) and the address area size (using MAMR). (iii) Example of register setting To set the block address area 64 KB from address 110000H, set the registers as follows: MSB LSB 7 6 5 4 3 2 1 0 MSAR 0 0 0 1 0 0 0 1 ; set start address to 110000H MAMR 0 0 0 0 0 0 0 1 ; set block address area size to 64k-bytes Memory Start Address Register MSAR<MS23:16> correspond with address A23 to A16. A15 to A0 are set to ‘0’. Therefore setting MSAR to the above mentioned value specifies the start address of the block address area to address 110000H. Memory Address Mask Register MAMR<MV22:15> set whether address A22 to 15 are compared or not. Set the register to ‘0’ to compare, or to ‘1’ not to compare. Remember that A23 is always compared. Setting the above-mentioned compares A23 to A16 with the values set as the start addresses. Therefore the block size is 64 KB (since the first bit set to 0 is A16 Î 216 = 64 KB) To summarize, 64 KB of addresses 110000H to 11FFFFH are set as the block address area, and compared with the addresses on the bus. If the compared result is a match, the chip select signal CS is set to Low.

(iv) Case of overlapping blocks When the set block address area overlaps with the built-in memory area, the block address area is processed according to priorities as follows: This means that the block address is not remapped but priorities are used to disable any conflict. Also note that any accessed areas outside the address spaces are set to 1 wait bus cycle ( CS signal is not outputted although RD and WR signal are outputted.). This factor depends on the speed of the external memory. It is a fixed parameter. (2) Wait control The external bus cycle completes a wait of two states at least (i.e. 100ns @fc = 20MHz). Setting the control register BCSL<BWW2:0> and <BWR2:0> specifies the number of waits in the read cycle and the write cycle. <BWWn> is set using the same method as for <BWRn>. Note that this setting is only for asynchronisation purpose. BWW/BWR bit (BCSL Regsiter) BWW2 BWR2 BWW1 BWR1 BWW0 BWR0 Function 0 0 1 2states (0 wait) access fixed mode 0 1 0 3states (1 wait) access fixed mode (Default) 1 0 1 4states (2 wait) access fixed mode 1 1 0 5states (3 wait) access fixed mode 0 1 1 WAIT pin input mode Others (Reserved) (i) Waits number fixed mode The bus cycle is completed with the set states. The number of states is selected from 2 states (0WAIT) to 5 states (3WAIT). (ii) WAIT pin input mode This mode continuously samples the WAIT input pins and inserts a wait if the pin is active. The bus cycle is minimum 2 states and is therefore completed at 2 states when the wait signal is non active (High level). The bus cycle extends if the wait signal is active at 2 states and more. Built-in I/O > Built-in memory > Block address area

(3) Basic bus timing

• External Read / Write Bus Cycle (0 WAIT)
• External Read / Write Bus Cycle (1 WAIT) ADDRESS CS RD D7 to 0 T1 T2 WR D7 to 0 input output read write CLK (20MHz) ADDRESS CS RD D7 to 0 T1 TW WR D7 to 0 input output read write CLK (20MHz)

• External Read / Write Bus Cycle (0 WAIT @ WAIT pin input mode)
• External Read / Write Bus Cycle (n WAIT @ WAIT pin input mode) ADDRESS CS RD CLK D7 to 0 T1 T2 WR D7 to 0 input output read write WAIT sampling (20MHz) ADDRESS CS RD CLK D7 to 0 T1 TW WR D7 to 0 input output read write WAIT sampling sampling (20MHz)

• Example of WAIT Input Cycle (5WAIT) D Q CK RES D Q CK RES D Q CK RES D Q CK RES D Q CK RES WAIT FF0 FF1 FF2 FF3 FF4 CLK CS RD WR FF2_Q RD CLK(20MHz) FF0_D 1 2 FF0_Q FF1_Q 3 4 5 6 7 FF_RES FF3_Q WAIT CS

3.6.4 List of registers

The memory control registers and the settings are described as follows. For the addresses of the registers, see List of Special Function Registers in section 5. (1) Control registers The control register is a pair of BCSL and BCSH. BCSL has the same configuration regardless of the block address areas. Block CS/WAIT control register (Low) 7 6 5 4 3 2 1 0 bit Symbol - BWW2 BWW1 BWW0 - BWR2 BWR1 BWR0 Read/Write W After Reset - 0 1 0 - 0 1 0 BWW[2:0] Specifies the number of write waits. 001 = 2 states (0 WAIT) access 010 = 3 states (1 WAIT) access 101 = 4 states (2 WAIT) access 110 = 5 states (3 WAIT) access 0 1 1 = W A I T p i n i n p u t m o d e O t h e r s = ( R e s e r v e d ) BWR[2:0] Specifies the number of read waits. 001 = 2 states (0 WAIT) access 010 = 3 states (1 WAIT) access 101 = 4 states (2 WAIT) access 110 = 5 states (3 WAIT) access 0 1 1 = W A I T p i n i n p u t m o d e O t h e r s = ( R e s e r v e d ) Block CS/WAIT control register (High) 7 6 5 4 3 2 1 0 bit Symbol BE BM - - BOM1 BOM0 BBUS1 BBUS0 Read/Write W After reset 1 0 0 (Fix to 0) 0(Fix to 0) 0 0 0 0 BCSL (0148H) BCSH (0149H) BE Enable bit 0 = No chip select signal output 1 = Chip select signal output (Default) BM Block address area specification 0 = Sets the block address area of CS to addresses 000000H to FFFFEFH. (Default) 1 = Sets the block address area of CS to programmable. Note: After reset release, the block address area of CS is set to addresses 000000H to FFFFEFH. BOM[1:0] 00 = SRAM or ROM(Default) others = (Reserved) BBUS[1:0] Sets the data bus width 00 = 8-bit (Default) others = (Reserved)

(2) Block address register A start address and an address area of the block address are specified by the memory start address register (MSAR) and the memory address mask register (MAMR). The bit to be set by the memory address mask register depends on the block address area. Memory Start Address Register 7 6 5 4 3 2 1 0 bit Symbol MS23 MS22 MS21 MS20 MS19 MS18 MS17 MS16 Read/Write R/W After Reset 1 1 1 1 1 1 1 1 MS[23:16] Sets a start address. Sets the start address of the block address areas. <MS23:16> corr espond to the address A23 to A16. Memory Address Mask Register 7 6 5 4 3 2 1 0 bit Symbol MV22 MV21 MV20 MV19 MV18 MV17 MV16 MV15 Read/Write R/W After reset 1 1 1 1 1 1 1 1 MV[22:15] Enables or masks c om parison of the addresses. <MV22:15> corr espond to addresses A22 to 15. If “0” is set, the comparison between the value of the address bus and the start address is enabled. If “1” is set, the comparison is masked. MSAR (014BH) MAMR (014AH)

3.7 8-bit Timers TMP92CD54I features eight built-in 8-bit timers (timers 0 to 7). These timers are paired into four modules: timers 01, timers 23, timers 45, and timers 67. Each module consists of two channels and can operate in any of the following four operating modes.

• 8-Bit Interval Timer Mode
• 16-Bit Interval Timer Mode
• 8-Bit Programmable Square Wave Pulse Genera tion Output Mode (PPG – variable duty with variable cycle)
• 8-Bit Pulse Width Modulation Output Mode (PWM – variable duty with constant cycle) Figure 3.7.1 to Figure 3.7.4 show block diagrams for timers 01, timers 23, timers 45 and timers 67. Each channel consists of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (special-function registers). Each of the four modules (timers 01, timers 23, timers 45 and timers 67) can be operated independently. All modules operate in the same manner; hence only the operation of timers 01 is explained here. Table 3.7.1 Registers and pins for each module Module Specification timers 01 timers 23 timers 45 timers 67 Input pin for external clock TI0 (shared with PC0) - TI4 (shared with PC3) - External pin Output pin for timer flip-flop TO1 (shared with PC1) TO3 (shared with PC2) TO5 (shared with PC4) TO7 (shared with PC5) Timer run register TRUN0 1 (0080H) TRUN23 (0088H) TRUN45 (0090H) TRUN67 (0098H) Timer register TREG0 (0082H) TREG1 (0083H) TREG2 (008AH) TREG3 (008BH) TREG4 (0092H) TREG5 (0093H) TREG6 (009AH) TREG7 (009BH) Timer mode register TMOD01 (0084H) TMOD23 (008CH) TMOD45 (0094H) TMOD67 (009CH) SFR (address) Timer flip-flop control register TFFCR1 (0085H) TFFCR3 (008DH) TFFCR5 (0095H) TFFCR7 (009DH)

3.7.1 Block diagrams

Figure 3.7.1 Timers 01 block diagram Timer 1 Interrupt output: INTT1 Match detect Run/Clear Prescaler clock: φT0 T0TRG External input clock: TI0 TMOD01 <PWM01, PWM00> Selector 8-bit up counter (UC0) 8-Bit comparator (CP0) Match detect Register buffer 0 8-Bit timer register TREG0 TRUN01 <T0RDE> TRUN01<T0RUN> φT1 φT4 φT16 2n Over flow Timer 0 Interrupt output: INTT0 TMOD01 <T01M1, T01M0> Timer 0 Match output: T0TRG Selector φT1 φT16 φT256 Internal bus TMOD01 <T0CLK1, T0CLK0> TMOD01 <T1CLK1, T1CLK0> 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Prescaler TRUN01 <T01PRUN> 8-Bit Up-Counter (UC1) 8-Bit comparator (CP1) TRUN01<T1RUN> Internal bus TMOD01 <T01M1, T01M0> TMOD01 <T01M1, T01M0> (16bit interval timer mode) Over flow (For 8-bit PPG mode) 8-Bit Timer Register TREG1 Timer Flip-Flop TFF1 TFFCR1 Timer flip-flop output: TO1 TMOD01 <T01M1, T01M0>

Figure 3.7.2 Timers 23 block diagram Timer 3 Interrupt output: INTT3 Match detect Run/Clear Prescaler clock: φT0 T2TRG TMOD23 <PWM21, PWM20> Selector 8-bit up counter (UC2) 8-Bit comparator (CP2) Match detect Register buffer 2 8-Bit timer register TREG2 TRUN23 <T2RDE> TRUN23<T2RUN> φT1 φT4 φT16 2n Over flow Timer 2 Interrupt output: INTT2 TMOD23 <T23M1, T23M0> Timer 2 Match output: T0TRG Selector φT1 φT16 φT256 Internal bus TMOD23 <T2CLK1, T2CLK0> TMOD23 <T3CLK1, T3CLK0> 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Prescaler TRUN23 <T23PRUN> 8-Bit Up-Counter (UC3) 8-Bit comparator (CP3) TRUN23<T3RUN> Internal bus TMOD23 <T23M1, T23M0> TMOD23 <T23M1, T23M0> (16bit interval timer mode) Over flow (For 8-bit PPG mode) 8-Bit Timer Register TREG3 Timer Flip-Flop TFF3 TFFCR3 Timer flip-flop output: TO3 TMOD23 <T23M1, T23M0>

Figure 3.7.3 Timers 45 block diagram Timer 5 Interrupt output: INTT5 Match detect Run/Clear Prescaler clock: φT0 T4TRG External input clock: TI4 TMOD45 <PWM41, PWM40> Selector 8-bit up counter (UC4) 8-Bit comparator (CP4) Match detect Register buffer 4 8-Bit timer register TREG4 TRUN45 <T4RDE> TRUN45<T4RUN> φT1 φT4 φT16 2n Over flow Timer 4 Interrupt output: INTT4 TMOD45 <T45M1, T45M0> Timer 4 Match output: T4TRG Selector φT1 φT16 φT256 Internal bus TMOD45 <T4CLK1, T4CLK0> TMOD45 <T5CLK1, T5CLK0> 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Prescaler TRUN45 <T45PRUN> 8-Bit Up-Counter (UC5) 8-Bit comparator (CP5) TRUN45<T5RUN> Internal bus TMOD45 <T45M1, T45M0> TMOD45 <T45M1, T45M0> (16bit interval timer mode) Over flow (For 8-bit PPG mode) 8-Bit Timer Register TREG5 Timer Flip-Flop TFF5 TFFCR5 Timer flip-flop output: TO5 TMOD45 <T45M1, T45M0>

Figure 3.7.4 Timers 67 block diagram Timer 1 Interrup7 output: INTT7 Match detect Run/Clear Prescaler clock: φT0 T6TRG TMOD67 <PWM61, PWM60> Selector 8-bit up counter (UC6) 8-Bit comparator (CP6) Match detect Register buffer 6 8-Bit timer register TREG6 TRUN67 <T6RDE> TRUN67<T6RUN> φT1 φT4 φT16 2n Over flow Timer 6 Interrupt output: INTT6 TMOD67 <T67M1, T67M0> Timer 6 Match output: T6TRG Selector φT1 φT16 φT256 Internal bus TMOD67 <T6CLK1, T6CLK0> TMOD67 <T7CLK1, T7CLK0> 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Prescaler TRUN67 <T67PRUN> 8-Bit Up-Counter (UC7) 8-Bit comparator (CP7) TRUN67<T7RUN> Internal bus TMOD67 <T67M1, T67M0> TMOD67 <T67M1, T67M0> (16bit interval timer mode) Over flow (For 8-bit PPG mode) 8-Bit Timer Register TREG7 Timer Flip-Flop TFF7 TFFCR7 Timer flip-flop output: TO7 TMOD67 <T67M1, T67M0>

3.7.2 Operation of each circuit

(1) Prescalers A 9-bit prescaler generates the input clock to timers 01. The clock T0 is the CPU clock fc divided by 4 and is the input to this prescaler. The prescaler’s operation can be controlled using TRUN01<T01PRUN> in the timer control register. Setting <T01PRUN> to 1 starts the count; setting <T10PRUN> to 0 clears the prescaler to zero and stops operation. At fc=20MHz Output clock Interval φT1 (8/fc) φT4 (32/fc) φT16 (128/fc) φT256 (2048/fc) 400 ns 1.6 µs 6.4 µs 102.4 µs 0 1 2 3 4 5 6 7 8 9-bit prescaler O S C ×4 ÷2 (10MHz) (10MHz) φT0 φT1 φT4 φT16 φT256 φT2 φT8 φT32 run/stop & clear TRUN01<T01PRUN> fIO (internal I/O clock) CPU clock fc (20MHz) 4/fc φT1 φT4 Figure 3.7.5 Prescaler Note: The following number in the parenthesis indicates the frequency when TMP92CD54I operates is the maximum frequency.

(2) Up-counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TMOD01. The input clock for UC0 is selectable and can be either the external clock input via the TI0 pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is specified by the value set in TMOD01<T01CLK1,T01CLK0>. The input clock for UC1 depends on the op eration mode. In 16-Bit Interval Timer Mode, the overflow output from UC0 is used as the input clock. In any mode other than 16-Bit Interval Timer Mode, the input clock is selectable and can either be one of the internal clocks φT1, φT16 or φT256, or the comparator output (the match detection signal) from timer 0. For each interval timer the timer operation control register bits TRUN01<T0RUN> and TRUN01<T1RUN> can be used to stop and clear the up-counters and to control their count. A Reset clears both up-counters, stopping the timers.

(3) Timer registers (TREG0 and TREG1) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TREG0 or TREG1 matches the value in the corresponding up-counter, the Comparator Ma tch Detect signal goes Active. If the value set in the timer register is 00H, the signal goes Active when the up-counter overflows. The TREG0 are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TRUN01<T0RDE> determines whether TREG0’s double buffer structure is enabled or disabled. It is disabled if <T0RDE> = 0 and enabled if <T0RDE> = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2 n overflow occurs in PWM Mode , or at the start of the PPG cycle in PPG Mode. Hence the double buffer cannot be used in Interval Timer Mode. A Reset initializes <T0RDE> to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set <T0RDE> to 1, and write the following data to the register buffer. Figure 3.7.6 shows the configuration of TREG0. Selector Write Shift trigger Write to TREG0 2n overflow of PWM TRUN01<T0RDE> Up-counter Comparator (CP0) Timer Registers 0 (TREG0) Register Buffers 0 Internal bus Matching detection in PPG cycle S A B Figure 3.7.6 Configuration of TREG0 Note: The same memory address is allocated to the timer register and the register buffer. When <T0RDE> = 0, the data is written in both registers (i.e. the Register buffer 0 and the 8-bit timer register TREG0) at the same time; when <T0RDE> = 1, only the register buffer is written to. The address of each timer register is as follows. TREG0: 000082H TREG1: 000083H TREG2: 00008AH TREG3: 00008BH TREG4: 000092H TREG5: 000093H TREG6: 00009AH TREG7: 00009BH All these registers are write-only and cannot be read.

(4) Comparator (CP0) The comparator compares the value in an up-counter with the value set in a timer register. If they match, the up-counter is cleared to zero and an interrupt signal (INTT0 or INTT1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TFF1) The timer flip-flop (TFF1) is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TFFCR1<TFF1IE> in the Timer Flip-Flop Control Register. A Reset clears the value of TFF1 to 0. Writing 01 or 10 to TFFCR1<TFF1C1,TFF1C0> sets TFF1 to 0 or 1. Writing 00 to these bits inverts the value of TFF1 (this is known as software inversion). The TFF1 signal is output via the TO1 pin (which can also be used as PC1). When this pin is used as the timer output, the timer flip-flop should be set beforehand using the Port C Function Register PCFC. TFF is inverted by …. 8-bit interval timer mode : UC0 matches TREG0. Or when UC1 matches TREG1. (Either one of the two is chosen) 16-bit interval timer mode : UC0 matches TREG0 and UC1 matches TREG1. 8-bit PWM mode : UC0 matches TREG0 or 2 n overflow is occurred. 8-bit PPG mode : UC0 matches TREG0 or UC0 matches TREG1. Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fc × 6) before the next overflow occurs by using an overflow interrupt. In the case of using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode: TREG0 and UC0 match tPWM (PWM cycle) 2n overflow interrupt TO1 Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt

3.7.3 SFRs

Bit symbol T0RDE - - - I2T01 T01PRUN T1RUN T0RUN Read/Write R/W R/W After Reset 0 - - - 0 0 0 0 Function Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate Timer Run/Stop control 0: Stop & Clear 1: Run (count up)

0 Stop & Clear

1 Run (count up)

(0080H) Timer Run/Stop control TREG0 double buffer control

0 Disable

1 Enable

I2T01: Operation in IDLE2 Mode T01PRUN: Run prescaler T1RUN: Run Timer 1 T0RUN: Run Timer 0 Note1: The values of bits 4 to 6 of TRUN01 are undefined when read. Note2: Needs to set <T0RDE> bit and enable double buffer in PPG/PWM mode. Timers 23 Run Register 7 6 5 4 3 2 1 0 Bit symbol T2RDE - - - I2T23 T23PRUN T3RUN T2RUN Read/Write R/W R/W After Reset 0 - - - 0 0 0 0 Function Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Rung Timer Run/Stop control 0: Stop & Clear 1: Run (count up) TRUN23 (0088H) Timer Run/Stop control TREG2 double buffer control I2T23: Operation in IDLE2 Mode T23PRUN: Run prescaler T3RUN: Run Timer 3 T2RUN: Run Timer 2 Note1: The values of bits 4 to 6 of TRUN23 are undefined when read. Note2: Needs to set <T2RDE> bit and enable double buffer in PPG/PWM mode. Figure 3.7.7 Register for 8-bit Timers

Bit symbol T4RDE - - - I2T45 T45PRUN T5RUN T4RUN Read/Write R/W R/W After Reset 0 - - - 0 0 0 0 Function Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate Timer Run/Stop control 0: Stop & Clear 1: Run (count up) TRUN45 (0090H) Timer Run/Stop control TREG4 double buffer control I2T45: Operation during IDLE2-Mode T45PRUN: Run for prescaler T5RUN: Run Timer 5 T4RUN: Run Timer 4 Note1: The values of bits 4 to 6 of TRUN45 are undefined when read. Note2: Needs to set <T4RDE> bit and enable double buffer in PPG/PWM mode. Timers 67 Run Register 7 6 5 4 3 2 1 0 Bit symbol T6RDE - - - I2T67 T67PRUN T7RUN T6RUN Read/Write R/W R/W After Reset 0 - - - 0 0 0 0 Function Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate Timer Run/Stop control 0: Stop & Clear 1: Run (count up) TRUN67 (0098H) Timer Run/Stop control TREG6 double buffer control

1 Enalbe

I2T67: Operation during IDLE2 Mode T67PRUN: Run prescaler T7RUN: Run Timer 7 T6RUN: Run Timer 6 Note1: The values of bits 4 to 6 of TRUN67 are undefined when read. Note2: Needs to set <T6RDE> bit and enable double buffer in PPG/PWM mode. Figure 3.7.8 Register for 8-bit Timers

Bit symbol T01M1 T01M0 PWM01 PWM00 T1CLK1 T1CLK0 T0CLK1 T0CLK0 Read/Write R/W After Reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode PWM cycle 00: reserved 01: 2 10: 27 11: 28 Source clock for Timer 1 00: T0TRG 01: φT1 10: φT16 11: φT256 Source clock for Timer 0 00: TI0 pin (Note) 01: φT1 10: φT4 11: φT16

00 TI0 (external input)

01 φT1 (prescaler) 10 φT4 (prescaler) 11 φT16 (prescaler) TMOD01 <T01M1∼T01M0>≠01 TMOD01 <T01M1∼T01M 0>=01

00 Comparator

01 φT1 10 φT16 11 φT256 Overflow output from Timer 0 (16-Bit Timer Mode) 00 reserved 01 2 6 × clock source 10 2 7 × clock source 11 2 8 × clock source

00 Two 8-bit timers

11 8-bit PWM (Timer 0) + 8-bit timer (Timer 1) Note : When setting the TI0 pin, first set the Port C setting, then TMOD01. PWM cycle selection TMOD01 (0084H) Timer 0 source clock selection Timer 1 source clock selection Timers 01 operation mode selection Figure 3.7.9 Register for 8-bit Timers

Bit Symbol T23M1 T23M0 PWM21 PWM20 T3CLK1 T3CLK0 T2CLK1 T2CLK0 Read/Write R/W After Reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode PWM cycle 00: reserved 01: 2 10: 27 11: 28 Source clock for Timer 3 00: T2TRG 01: φT1 10: φT16 11: φT256 Source clock for Timer 2 00: reserved 01: φT1 10: φT4 11: φT16

00 Do not set

01 φT1 (prescaler) 10 φT4 (prescaler) 11 φT16 (prescaler) TMOD23 <T23M1∼T23M0>≠01 TMOD23 <T23M1∼T23M0>=01

00 Comparator output

01 φT1 10 φT16 11 φT256 Overflow output from Timer 2 (16-Bit Timer Mode) 00 reserved 01 2 6 × clock source 10 2 7 × clock source 11 2 8 × clock source 11 8-bit PWM (Timer 2) + 8-bit timer (Timer 3) PWM cycle selection TMOD23 (008CH) Timer 2 source clock selection Timer 3 source clock selection Timers 23 operation mode selection Figure 3.7.10 Register for 8-bit Timers

Bit symbol T45M1 T45M0 PWM41 PWM40 T5CLK1 T5CLK0 T4CLK1 T4CLK0 Read/Write R/W After Reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode PWM cycle 00: reserved 01: 2 10: 27 11: 28 Source clock for Timer 5 00: T4TRG 01: φT1 10: φT16 11: φT256 Source clock for Timer 4 00: TI4 pin (Note) 01: φT1 10: φT4 11: φT16

00 TI4 (external input)

01 φT1 (prescaler) 10 φT4 (prescaler) 11 φT16 (prescaler) TMOD45 <T45M1∼T45M0>≠01 TMOD45 <T45M1∼T45M0>=01 01 φT1 10 φT16 11 φT256 Overflow output from Timer 4 (16-Bit Timer Mode) 00 reserved 01 2 6 × clock source 10 2 7 × clock source 11 2 8 × clock source 11 8-bit PWM (Timer 4) + 8-bit timer (Timer 5) Note : When setting the TI4 pin, first set the Port C setting, then TMOD45. PWM cycle TMOD45 (0094H) Source clock for Timer 4 Source clock for Timer 5 Operation mode for Timers 45 Figure 3.7.11 Register for 8-bit Timers

Bit symbol T67M1 T67M0 PWM61 PWM60 T7CLK1 T7CLK0 T6CLK1 T6CLK0 Read/Write R/W After Reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-Bit Timer Mode 01: 16-Bit Timer Mode 10: 8-Bit PPG Mode 11: 8-Bit PWM Mode PWM cycle 00: reserved 01: 2 10: 27 11: 28 Source clock for Timer 7 00: T6TRG 01: φT1 10: φT16 11: φT256 Source clock for Timer6 00: reserved 01: φT1 10: φT4 11: φT16 01 φT1 (prescaler) 10 φT4 (prescaler) 11 φT16 (prescaler) TMOD67 <T67M1∼T67M0>≠01 TMOD67 <T67M1∼T67M0>=01 01 φT1 10 φT16 11 φT256 Overflow output from Timer 6 (16-Bit Timer Mode 00 reserved 01 2 6 × clock source 10 2 7 × clock source 11 2 8 × clock source 11 8-bit PWM (Timer 6) + 8-bit timer (Timer 7) PWM cycle TMOD67 (009CH) Source clock for Timer 6 Source clock for Timer 7 Operation mode for Timers 67 Figure 3.7.12 Register for 8-bit Timers

Timer 1 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol - - - - TFF1C1 TFF1C0 TFF1IE TFF1IS Read/Write R/W After Reset - - - - 1 1 0 0 Function 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don’t care TFF1 Control for inversion 0: Disable 1: Enable TFF1 Inversion select 0: Timer 0 1: Timer 1

0 Inversion by Timer 0

1 Inversion by Timer 1

0 Disabled

1 Enabled

00 Inverts the value of TFF1

01 Sets TFF1 to 1

10 Clears TFF1 to 0

11 Don’t care

(0085H) Inverse signal for Timer Flop-Flop 1 (TFF1) (Don’t care except in 8-Bit Timer Mode) Inversion of TFF1 Note: The values of bits 4 to 7 of TFFCR1 are undefined when read. Read-Modify -Write instructions are prohibited. Figure 3.7.13 Register for 8-bit Timers

Timer 3 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol - - - - TFF3C1 TFF3C0 TFF3IE TFF3IS Read/Write R/W After Reset - - - - 1 1 0 0 Function 00: Invert TFF3 01: Set TFF3 10: Clear TFF3 11: Don’t care TFF3 Control for inversion 0: Disable 1: Enable TFF3 Inversion select 0: Timer 2 1: Timer 3

0 Inversion by Timer 2

1 Inversion by Timer 3

00 Inverts the value of TFF3

01 Sets TFF3 to 1

10 Clears TFF3 to 0

(008DH) Inverse signal for Timer Flip-Flop 3 (TFF3) (Don’t care except in 8-Bit Timer Mode) Inversion of TFF3 Note: The values of bits 4 to 7 of TFFCR3 are undefined when read. Read-Modify -Write instructions are prohibited. Figure 3.7.14 Register for 8-bit Timers

Timer 5 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol - - - - TFF5C1 TFF5C0 TFF5IE TFF5IS Read/Write R/W After Reset - - - - 1 1 0 0 Function 00: Invert TFF5 01: Set TFF5 10: Clear TFF5 11: Don’t care TFF5 Control for inversion 0: Disable 1: Enable TFF5 Inversion select 0: Timer 4 1: Timer 5

0 Inversion by Timer 4

1 Inversion by Timer 5

00 Inverts the value TFF5

01 Sets TFF5 to 1

10 Clears TFF5 to 0

(0095H) Inverse signal for Timer Flip-Flop 5 (TFF5) (Don’t care except in 8-Bit Timer Mode) Inversion of TFF5 Note: The values of bits 4 to 7 of TFFCR5 are undefined when read. Read-Modify -Write instructions are prohibited. Figure 3.7.15 Register for 8-bit Timers

Timer 7 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol - - - - TFF7C1 TFF7C0 TFF7IE TFF7IS Read/Write R/W After Reset - - - - 1 1 0 0 Function 00: Invert TFF7 01: Set TFF7 10: Clear TFF7 11: Don’t care TFF7 Control for invertsion 0: Disable 1: Enable TFF7 Inversion select 0: Timer 6 1: Timer 7

0 Inversion by Timer 6

1 Inversion by Timer 7

00 Inverts the value of TFF7

01 Sets TFF7 to 1

10 Clears TFF7 to 0

(009DH) Inverse signal for Timer Flip-Flop 7 (TFF7) (Don’t care except in 8-Bit Timer Mode) Inversion of TFF7 Note: The values of bits 4 to 7 of TFFCR7 are undefined when read. Read-Modify -Write instructions are prohibited. Figure 3.7.16 Register for 8-bit Timers

Timer Register (TREG 0 to 7) Symbol Address 7 6 5 4 3 2 1 0 W TREG0 82H (no RMW) Undefined W TREG1 83H (no RMW) Undefined W TREG2 8AH (no RMW) Undefined W TREG3 8BH (no RMW) Undefined W TREG4 92H (no RMW) Undefined W TREG5 93H (no RMW) Undefined W TREG6 9AH (no RMW) Undefined W TREG7 9BH (no RMW) Undefined TREG is for the comparator (When UC matches TREG, occur match detect signal). Refer to setting example in Section 3.7.4, Operation in each mode. Figure 3.7.17 Register for 8-bit Timers

3.7.4 Operation in each mode

(1) 8-Bit interval Timer Mode Both timer 0 and timer 1 can be used independently as 8-bit interval timers. c Generating interrupts at a fixed interval (using timer 1) To generate interrupts at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation mode, input clock and a cycle to TMOD01 and TREG1 register, respectively. Then, enable the interrupt INTT1 and start timer 1 counting. Example: To generate an INTT1 interrupt every 40 µseconds at fc = 20 MHz, set each register as follows: MSB LSB 7 6 5 4 3 2 1 0 TRUN01 ← – X X X – – 0 – Stop timer 1 and clear it to 0. TMOD01 ← 0 0 X X 0 1 - - Select 8-Bit Interval Timer Mode and select φT1 (0.4 µs at fc = 20 MHz) as the input clock. TREG1 ← 0 1 1 0 0 1 0 0 Set TREG1 to 40 µs ÷ φT1 = 100 = 64H INTET01 ← X 1 0 1 – – – – Set INTT1 interrupt level to 5. TRUN01 ← – X X X – 1 1 – Start timer 1 counting. Note: X = Don’t care; “−” = No change Select the input clock using Table 3.7.2. Table 3.7.2 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer Input Clock Interrupt Interval (at fc = 20 MHz) Resolution φT1 (8/fc) φT4 (32/fc) φT16 (128/fc) φT256 (2048/fc) 0.4 µs to 102.4 µs 1.6 µs to 409.6 µs 6.4 µs to 1.639 ms 102.4 µs to 26.22 ms 0.4 µs 1.6 µs 6.4 µs 102.4 µs Note: The input clocks for timer 0 and timer 1 differ as follows: timer 0: Uses timer 0 input (TI0) and can be selected from φT1, φT4 or φT16 timer 1: Match output of timer 0 (T0TRG) and can be selected from φT1, φT16, φT256 UC1 & TREG1 Match detect INTT1 interrupt request occur TREG1 = 64H = 40 µs ÷ φT1

d Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TFF1) is inverted at constant intervals and its status output via the timer output pin (TO1). Example: To output a 2.4-µs square wave pulse from the TO1 pin at fc = 20 MHz, use the following procedure to make the appropri ate register settings. This example uses timer 1; however, either timer 0 or timer 1 may be used. 7 6 5 4 3 2 1 0 TRUN01 ← – X X X – – 0 – Stop timer 1 and clear it to 0. TMOD01 ← 0 0 X X 0 1 – – Select 8-Bit Interval Timer Mode and select φT1 (0.4 µs at fc = 20 MHz) as the input clock. TREG1 ← 0 0 0 0 0 0 1 1 Set the timer register to 2.4 µs ÷ φT1 ÷ 2 = 3 TFFCR1 ← X X X X 1 0 1 1 Clear TFF1 to 0 and set it to invert on the match detect signal from timer 1. PCFC ← X X – – - – 1 - Set PC1 to function as the TO1 pin. TRUN01 ← – X X X – 1 1 – Start timer 1 counting. Note: X = Don’t care; “−” = No change 0.77 µs at @fc = 20 Bit7∼2 φT1 INTT1 UC1 Clear TFF1 Bit 0 Bit 1 TRUN01 <T1RUN> Up- counter Comparator timing Comparator output (match detect) TO1 0 1 1 1 2 2 2 3 3 3 0 00 Figure 3.7.18 Square wave output timing chart (50% Duty)

Example: To generate 1/4-duty 62.5 kHz pulses (at fc = 20 MHz): 16 µs Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 µs φT1 = 0.4 µs (at 20 MHz); 16 µs ÷ 0.4 µs = 40 Therefore set TREG1 to 40 (28H) The duty is to be set to 1/4: t × 1/4 = 16 µs × 1/4 = 4 µs 4 µs ÷ 0.4 µs = 10 Therefore, set TREG0 = 10 = 0AH. 7 6 5 4 3 2 1 0 TRUN01 ← 0 X X X – 0 0 0 Stop timer 0 and timer 1 and clear it to “0”. TMOD01 ← 1 0 X X X X 0 1 Set the 8-bit PPG mode, and select φT1 as input clock. TREG0 ← 0 0 0 0 1 0 1 0 Write 0AH TREG1 ← 0 0 1 0 1 0 0 0 Write 28H TFFCR1 ← X X X X 0 1 1 X Set TFF1 and enable inversion. 10 generates a negative logic pulse. PCFC ← X X – – - – 1 - Set PC1 as the TO1 pin. TRUN01 ← 1 X X X – 1 1 1 Set double buffer enable, and start timer 0 and timer 1 counting. Note: X = Don’t care; “−” = No change

In this mode the value of the register buffer will be shifted into TREG0 if 2 n overflow is detected when the TREG0 double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Up-counter = Q2 Up-counter = Q1 Q1 Q2 Shift into TREG0 Match with TREG0 2n overflow TREG0 (value to be compared) Register buffer TREG0 (register buffer) write Figure 3.7.26 Register buffer operation Example: To output the following PWM waves on the TO1 pin at fc = 20 MHz: 36.0 µs 51.2 µs To achieve a 51.2-µs PWM cycle by setting φT1 to 0.4 µs (at fc = 20 MHz): 51.2 µs ÷ 0.4 µs = 128 2 n = 128 Therefore n should be set to 7. Since the low-level period is 36.0 µs when φT1 = 0.4 µs, set the following value for TREG0: 36.0 µs ÷ 0.4 µs = 90 = 5AH MSB LSB 7 6 5 4 3 2 1 0 TRUN01 ← – X X X – – – 0 Stop timer 0 and clear it to 0. TMOD01 ← 1 1 1 0 – – 0 1 Select 8-Bit PWM Mode (cycle: 2 7) and select φT1 as the input clock. TREG0 ← 0 1 0 1 1 0 1 0 Write 5AH. TFFCR1 ← X X X X 1 0 1 X Clear TFF1 to 0, and enable the inversion. PCFC ← X X – – - – 1 - Set PC1 and the TO1 pin. TRUN01 ← 1 X X X – 1 - 1 Set double buffer enable, and start timer 0 counting. Note: X = Don’t care; “−” = No change

Table 3.7.3 PWM cycle PWM Interval (at fc = 20MHz) φT1 φT4 φT16 (5) Settings for each mode Table 3.7.4 shows the SFR settings for each mode. Table 3.7.4 Interval Timer mode setting registers Register name TMOD01 TFFCR1 <Bit Symbol> <T01M1:0> <PWM01:00> <T1CLK1:0> <T0CLK1:0> <TFF1IS> Function Interval Timer mode PWM cycle Upper timer input clock Lower timer input clock Timer F/F invert signal select 8-bit timer × 2 channels 00 − Lower timer match, φT1, φT16, φT256 (00, 01, 10, 11) External clock, φT1, φT4, φT16 (00, 01, 10, 11) 0: Lower timer output 1: Upper timer output 16-bit interval timer mode 01 − − External clock, φT1, φT4, φT16 (00, 01, 10, 11) 8-bit PPG × 1 channel 10 − − External clock, φT1, φT4, φT16 (00, 01, 10, 11) 8-bit PWM × 1 channel 11 26 , 27 , 28 (01, 10, 11) − External clock, φT1, φT4, φT16 (00, 01, 10, 11) 8-bit timer × 1 channel 11 − φT1, φT16 , φT256 (01, 10, 11) − Output disabled Note:“−” = Don’t care

3.8 16-Bit Timer/Event Counters TMP92CD54I incorporates two multifunctional 16-bit timer/event counters (timer 8 and timer A) which have the following operation modes:

• 16-Bit Interval Timer Mode
• 16-Bit Event Counter Mode
• 16-Bit Programmable Pulse Generation (PPG) Mode Can be used following operation modes by capture function:
• Frequency Measurement Mode
• Pulse Width Measurement Mode
• Time Differential Measurement Mode Each timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. Each timer/event counter is controlled by an 11-byte control SFR. The two channels (timer 8 and timer A) can be used independently. Both channels feature the same operations except for those described in Table 3.8.1. Thus, only the operation of timer 8 is explained below. Table 3.8.1 Differences between Timer 8 and Timer A Channel Specification Timer 8 Timer A TI8 (also used as PD0) TIA (also used as PD4) External clock / Capture trigger input pins TI9 (also used as PD1) TIB (also used as PD5) TO8 (also used as PD2) TOA (also used as PD6) External Pins Timer flip-flop output pins TO9 (also used as PD3) TOB (also used as PD7) Timer Run Register TRUN8 (00A0H) TRUNA (00B0H) Timer Mode Register TMOD8 (00A2H) TMODA (00B2H) Timer Flip-Flop Control Register TFFCR8 (00A3H) TFFCRA (00B3H) TREG8L (00A8H) TREGAL (00B8H) TREG8H (00A9H) TREGAH (00B9H) TREG9L (00AAH) TREGBL (00BAH) Timer Register TREG9H (00ABH) TREGBH (00BBH) CAP8L (00ACH) CAPAL (00BCH) CAP8H (00ADH) CAPAH (00BDH) CAP9L (00AEH) CAPBL (00BEH) SFR (address) Capture Register CAP9H (00AFH) CAPBH (00BFH)

3.8.1 Block diagrams

Intenal data bus Internal data bus Run/ Clear Match detection 16-Bit Comparator (CP8) 16-bit up counter (UC8) 16-Bit Time Register TREG9H/L Match detection Count Clock TMOD8<T8CLK1∼T8CLK0> TRUN8 <T8RDE> Slelector Capture, External INT input control TMOD8 <CAP89M1∼ CAP89M0> Prescaler clock: φT0 External INT input INT5 INT6 TFF1 TI8 TI9 φT1 φT4 φT16 TRUN8<T8RUN> TMOD8<T8CLE> (from timer 01 ) Capture Register 8 CAP8H/L TMOD8 <CAP8IN> Caputure register 9 CAP9H/L 32 16 8 4 2 φT1 φT4 φT16 TRUN8 <T8PRUN> Internal data-bus Internal data bus Timer Flip-Flop control TFF8 TFF9 Timer flip-flop TO8 TO9 Over flow INT INTTO8 Timer flip-flop output Register 0 INTTR8 Register 1 INTTR9 INT output 16-Bit Comparator (CP9) 16-Bit timer register TREG8H/L Register Buffer 8 Figure 3.8.1 Block Diagram of Timer 8

TMP92CD54IIntenal data busInternal data bus Run/ Clear Match detection16-Bit comparator (CPA) 16-Bit Up-Counter (UCA) 16-Bit Time Register TREGBH/L Match detection Count clock TMODA<TACLK1∼TACLK0> TB0RUN <TB0RDE> Slelector Capture, External INT input control TMODA <CAPABM1∼ CAPABM0> Prescaler clock : φT0 External INT input INT7 TFF1 TIA TIB φT1 φT4 φT16 TRUNA<TARUN> TMODA<TACLE> (from timer 01 ) Capture register A CAPAH/L TMODA <CAPAIN> Caputure Register B CAPBH/L 3216842 φT1 φT4 φT16 TRUNA <TAPRUN> Internal data bus Internal data bus Timer Flip-Flop control TFFA TFFB Timer flip-flop TOA TOB Over flow INT INTTOA Timer flip-flop output Register 0 INTTRA Register 1 INTTRB INT output 16-Bit comparator (CPB) 16-Bit Timer Register TREGAH/L Register Buffer A Figure 3.8.2 Block diagram of Timer A

3.8.2 Operation of each block

(1) Prescaler The 5-bit prescaler generates the source clock for timer 8. The prescaler clock (φT0) is divided clock (divided by 4) from fc. This prescaler can be started or stopped using TRUN8<T8PRUN>. Counting starts when <T8PRUN> is set to 1; the prescaler is cleared to zero and stops operation when <T8PRUN> is set to 0. Table 3.8.2 Prescaler clock resolution At fc=20MHz Output clock Interval φT1 ( 8/fc) φT4 ( 32/fc) φT16 (128/fc) 0.4 µs 1.6 µs 102.4 µs (2) Up-counter (UC8) UC8 is a 16-bit binary counter which counts up pulses input from the clock specified by TMOD8 <T8CLK1,T8CLK0>. Any one of the prescaler internal clocks φT1, φT4 and φT16 or an external clock input via the TI8 pin can be selected as the input clock. Counting or stopping & clearing of the counter is controlled by TRUN8<T8RUN>. When clearing is enabled, the up-counter UC8 will be cleared to zero each time its value matches the value in the timer register TREG9H/L. Clearing can be enabled or disabled using TMOD8<T8CLE>. If clearing is disabled, the counter operates as a free-running counter. A Timer Overflow interrupt (INTTO8) is generated when UC8 overflow occurs.

(3) Timer registers (TREG8H/L and TREG9H/L) These two 16-bit registers are used to set the interval time. When the value in the up-counter UC8 matches the value set in this timer register, the Comparator Match Detect signal will go Active. Setting data for timer register TREG8H/L and TREG9H/L is executed using 2 byte data transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order. The TREG8 timer register has a double-buffer structure, which is paired with register buffer 8. The value set in TRUN8<T8RDE> determines whether the double-buffer structure is enabled or disabled: it is disabled when <T8RDE> = 0, and enabled when <T8RDE> = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when the values in the up-counter (UC8) and the timer register TREG9 match. After a Reset, TREG8 and TREG9 are undefined. If the 16-bit timer is to be used after a Reset, data should be written to it beforehand. On a Reset <T8RDE> is initialized to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set <T8RDE> to 1, then write data to the register buffer as shown below. TREG8 and the register buffer both have the same memory addresses (0000A8H & 0000A9H) allocated to them. If <T8RDE> = 0, the value is written to both the timer register and the register buffer. If <T8RDE> = 1, the value is written to the register buffer only. The addresses of the Timer Registers are as follows: Upper 8 bits Lower 8 bits TREG8 0000A9H 0000A8H Upper 8 bits Lower 8 bits TREG9 0000ABH 0000AAH Timer 8 Upper 8 bits Lower 8 bits TREGA 0000B9H 0000B8H Upper 8 bits Lower 8 bits TREGB 0000BBH 0000BAH Timer A The Timer Registers are write-only registers and thus cannot be read.

(4) Capture Registers (CAP8H/L and CAP9H/L) These 16-bit registers are used to latch the values in the up-counter UC8. Data in the Capture Registers should be read using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. The addresses of the Capture Registers are as follows: Upper 8 bits Lower 8 bits CAP8 0000ADH 0000ACH Upper 8 bits Lower 8 bits CAP9 0000AFH 0000AEH Timer 8 Upper 8 bits Lower 8 bits CAPA 0000BDH 0000BCH Upper 8 bits Lower 8 bits CAPB 0000BFH 0000BEH Timer A The Capture Registers are read-only registers and thus cannot be written to. (5) Capture input control and external interrupt control This circuit controls the timing to latch the value of up-counter UC8 into CAP8, CAP8 and the generation of external interrupts. The latch timing for the capture register and selection of edge for external interrupt is determined by TMOD8<CAP89M1,CAP89M0>. The edge of external interrupt INT6 is fixed to rise edge. In addition, the value in the up-counter UC8 can be loaded into a capture register by software. Whenever 0 is written to TMOD8<CAP8IN>, the current value in the up-counter UC8 is loaded into capture regi ster CAP8. It is necessary to keep the prescaler in Run Mode (i.e. TRUN8<T8PRUN> must be held at a value of 1). (6) Comparators (CP8 and CP9) CP8 and CP9 are 16-bit comparators which compare the value in the up-counter UC8 with the value set in TREG8 or TREG9 respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTR8 or INTTR9 respectively). (7) Timer flip-flops (TFF8 and TFF9) These flip-flops are inverted by the matc h detect signals from the comparators and the latch signals to the Capture Registers. Inversion can be enabled and disabled for each element using TFFCR8<CAP9T8,CAP8T8,EQ9T8,EQ8T8>. After a reset the value of TFF8 and TFF9 are undefined. If 00 is written to TFFCR8<TFF8C1,TFF8C0> or <TFF9C1,TFF9C0>, TFF8 or TFF9 will be inverted. If 01 is written to the capture registers, the value of TFF8 or TFF9 will be set to 1.If 10 is written to the capture registers, the value of TFF8 or TFF9 will be set to 0. The values of TFF8 and TFF9 can be output via the Timer Output pins TO8 (which is s ha re d wit h P D2) a nd T O9 (which is s h ar e d wit h P D3) . T im e r o ut put s ho uld b e specified using the Port D SFRs.

3.8.3 SFR

Bit symbol T8RDE - - - I2T8 T8PRUN - T8RUN Read/Write R/W R/W R/W R/W R/W After Reset 0 0 - - 0 0 - 0 Function Double Buffer 0: Disable 1: Enable Write 0 IDLE2 0: Stop 1: Operate Timer Run/Stop control 0: Stop & Clear 1: Run (count up) TRUN8 (00A0H) Count operation

0 Stop and Clear

1 Count

I2T8: Operation during IDLE2-mode T8PRUN: Operation of prescaler Note: The 1, 4 and 5 of TRUN8 are read as underfined value. T8RUN: Operation of Timer 8 Timer A Run Register 7 6 5 4 3 2 1 0 Bit symbol TARDE - - - I2TA TAPRUN - TARUN Read/Write R/W R/W R/W R/W R/W After Reset 0 0 - - 0 0 - 0 Function Double Buffer 0: Disable 1: Enable Write 0 IDLE2 0: Stop 1: Operate

16 Bit Timer Run/Stop control

0: Stop & Clear 1: Run (count up) TRUNA (00B0H) Count Operation I2TA: Operation during IDLE2-mode TAPRUN: Operation of prescaler Note: The 1, 4 and 5 of TRUNA are read as underfined value. TARUN: Operation of Timer A Figure 3.8.3 Registers for 16-bit Timers

Bit symbol CAP9T9 EQ9T9 CAP8IN CAP89M1 CAP89M0 T8CLE T8CLK1 T8CLK0 Read/Write R/W W R/W After Reset 0 0 1 0 0 0 0 0 TFF9 inversion 0: Disable trigger 1: Enable trigger Function Invert when the UC value is captured to CAP9. Invert when the UC value matches the value in TREG9. Execute software capture 0: Execute 1: Don’t care Note) Always read as 1. Capture timing 00: Disable INT5 occurs on rising edge. 01: TI8 ↑ TI9 ↑ INT5 occurs on rising edge. 10: TI8 ↑ TI8 ↓ INT5 occurs on falling edge. 11: TFF1 ↑ TFF1 ↓ INT5 occurs on rising edge. Control up-counter 0: Disable clearing 1: Enable clearing Timer 8 source clock 00: TI8 pin 01: φT1 10: φT4 11: φT16 Timer 8 source clock

00 TI8 pin

01 φT1 10 φT4 11 φT16 Up-counter (UC8) clear control 1 Enable clearing by match with TREG9. Capture/Interrupt timing Capture control INT5 control

00 Disable

01 CAP8 at TI8 rise

INT5 occurs on rising edge of TI8.

10 CAP8 at TI8 rise

edge of TI8.

11 CAP8 at TFF1 rise

edge of TI8. Software capture 0 The value in the up-counter is captured to CAP8.

1 Don’t care

(00A2H) Figure 3.8.4 Registers for 16-bit Timers

Bit symbol CAPBTB EQBTB CAPAIN CAPABM1 CAPABM0 TACLE TACLK1 TACLK0 Read/Write R/W W R/W After Reset 0 0 1 0 0 0 0 0 TFFB inversion 0: Disable trigger 1: Enable trigger Function Invert when the UC value is captured to CAPB. Invert when the UC value matches the value in TREGB. Execute software capture 0: Execute 1: Don’t care Note) Always read as 1. Capture timing 00: Disable INT7 occurs on rising edge. 01: TIA ↑ TIB ↑ INT7 occurs on rising edge. 10: TIA ↑ TIA ↓ INT7 occurs on falling edge. 11: TFF1 ↑ TFF1 ↓ INT7 occurs on rising edge. Control up-counter 0: Disable clearing 1: Enable clearing Timer A source clock 00: TIA pin 01: φT1 10: φT4 11: φT16 Timer A source clock

00 TIA pin

01 φT1 10 φT4 11 φT16 Up-counter clear control 1 Enable clearing on match with TREGB. Capture/Interrupt timing Capture control INT7 control

01 CAPA at TIA rise

INT7 occurs on rising edge of TIA.

10 CAPA at TIA rise

edge of TIA.

11 CAPA at TFF1 rise

edge of TIA. Software capture 0 The value in the up-counter is captured to CAPA. (00B2H) Figure 3.8.5 Registers for 16-bit Timers

Timer 8 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TFF9C1 TFF9C0 CAP9T8 CAP8T8 EQ9T8 EQ8T8 TFF8C1 TFF8C0 Read/Write W R/W W After Reset 1 1 0 0 0 0 1 1 TFF8 inversion trigger 0: Disable trigger 1: Enable trigger Function Control TFF9 00: Invert 01: Set 10: Clear 11: Don’t care Note)Always read as 11 Invert when the UC value is loaded in to CAP9. Invert when the UC value is loaded in to CAP8. Invert when the UC value matches the value in TREG9. Invert when the UC value matches the value in TREG8. Control TFF8 00: Invert 01: Set 10: Clear 11: Don’t care Note)Always read as 11

00 Invert

01 Set to 1

10 Clear to 0

0 Disable trigger

1 Enable trigger

(00A3H) TFF8 control TFF8 Inverted when the UC value is matched to TREG8. TFF8 Inverted when the UC value is matched to TREG9. TFF8 Inverted when the UC value is loaded to CAP8. TFF8 Inverted when the UC value is loaded to CAP9. TFF9 control Figure 3.8.6 Registers for 16-bit Timers

Timer A Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TFFBC1 TFFBC0 CAPBTA CAPATA EQBTA EQATA TFFAC1 TFFAC0 Read/Write W R/W W After Reset 1 1 0 0 0 0 1 1 TFFA inversion trigger 0: Disable trigger 1: Enable trigger Function Control TFFB 00: Invert 01: Set 10: Clear 11: Don’t care Note)Always read as 11 Invert when the UC value is loaded in to CAPB. Invert when the UC value is loaded in to CAPA. Invert when the UC value matches the value in TREGB. Invert when the UC value matches the value in TREGA. Control TFFA 00: Invert 01: Set 10: Clear 11: Don’t care Note)Always read as 11 (00B3H) TFFA control TFFA Inverted when the UC value matches to TREGA. TFFA Inverted when the UC value matches to TREGB. TFFA Inverted when the UC value is loaded to CAPA. TFFA Inverted when the UC value is loaded to CAPB. TFFB control Figure 3.8.7 Registers for 16-bit Timers

Timer Register (Timer8, TimerA) Symbol Address 7 6 5 4 3 2 1 0 W TREG8L A8H (no RMW) Undefined W TREG8H A9H (no RMW) Undefined W TREG9L AAH (no RMW) Undefined W TREG9H ABH (no RMW) Undefined W TREGAL B8H (no RMW) Undefined W TREGAH B9H (no RMW) Undefined W TREGBL BAH (no RMW) Undefined W TREGBH BBH (no RMW) Undefined Capture Register (Timer8, TimerA） Symbol Address 7 6 5 4 3 2 1 0 R CAP8L ACH Undefined R CAP8H ADH Undefined R CAP9L AEH Undefined R CAP9H AFH Undefined R CAPAL BCH Undefined R CAPAH BDH Undefined R CAPBL BEH Undefined R CAPBH BFH Undefined Figure 3.8.8 Registers for 16-bit Timers.

3.8.4 Operation in each mode

(1) 16-Bit Interval Timer Mode Generating interrupts at fixed intervals In this example, the interrupt INTTR9 is set to be generated at fixed intervals. The interval time is set in the timer register TREG9. 7 6 5 4 3 2 1 0 TRUN8 ← 0 0 X X – 0 X 0 Stop timer 8. INTET89 ← X 1 0 0 X 0 0 0 Set INTTR9 Interrupt Level to 4. Disable INTTR8. TFFCR8 ← 1 1 0 0 0 0 1 1 Disable the trigger. TMOD8 ← 0 0 1 0 0 1 * * Select internal clock for input and (** = 01, 10, 11) disable the capture function. TREG9 ← * * * * * * * * Set the interval time (16 bits). TRUN8 ← 0 0 X X – 1 X 1 Start timer 8. Note: X = Don't care; “−” = No change (2) 16-Bit Event Counter Mode As described above, in 16-Bit Timer Mode, if the external clock (TI8 pin input) is selected as the input clock, the timer can be used as an event counter. The counter counts at the rising edge of TI8 pin input. To read the value of the counter, first perform “software capture” once, then read the captured value. 7 6 5 4 3 2 1 0 TRUN8 ← 0 0 X X – 0 X 0 Stop timer 8. PDFC ← - - - - - - - 1 Set PD0 to TI8. INTET89 ← X 1 0 0 X 0 0 0 Set INTTR9 Interrupt Level to 4. Disable INTTR8. TFFCR8 ← 1 1 0 0 0 0 1 1 Disable the trigger. TMOD8 ← 0 0 1 0 0 1 0 0 Select TI8 as the input clock. TREG9 ← * * * * * * * * Set the number of counts (16 bits). TRUN8 ← 0 0 X X – 1 X 1 Start timer 8. Note: X = Don't care; “−” = No change When the timer is used as an event counter, set the prescaler in Run Mode (i.e. with TRUN8<T8PRUN> = 1).

The following block diagram illustrates this mode. Figure 3.8.11 Block Diagram of 16-bit PPG Output Mode The following example shows how to set 16-Bit PPG Output Mode: 7 6 5 4 3 2 1 0 TRUN8 ← 0 0 X X – 0 X 0 Disable the TREG8 double buffer and stop timer 8. TREG8 ← * * * * * * * * Set the duty ratio (16 bits). TREG9 ← * * * * * * * * Set the frequency (16 bits). TRUN8 ← 1 0 X X – 0 X 0 Enable the TREG8 double buffer. (The duty and frequency are changed on an INTTR9 interrupt.) TFFCR8 ← X X 0 0 1 1 1 0 Set the mode to invert TFF8 at the match with TREG8/TREG9. Set TFF8 to 0. TMOD8 ← 0 0 1 0 0 1 * * Select the internal clock as the input clock and disable (** = 01, 10, 11) the capture function. PDFC ← – – - - – 1 - - Set PD2 to function as TO8. TRUN8 ← 1 0 X X – 1 X 1 Start timer 8. Note: X = Don't care; “−” = No change Selector Selector TRUN8<T8RDE> Match 16-Bit up-counter UC8 F/F (TFF8) 16-Bit Comparator Internal bus TREG9 TREG8-W TI8 φT1 φT4 φT16 TO8 (PPG output) TRUN8<T8RUN clear Register buffer 8 TREG8 16-Bit Comparator

(4) Capture function The capture function can be used in many ways. The following are examples: c As a one-shot pulse output from external trigger pulse d For frequency measurement e For pulse width measurement f For time difference measurement c One-shot pulse output from external trigger pulse Set the up-counter UC8 to Free-Running Mode with the internal input clock, input an external trigger pulse via the TI8 pin, and load the value of the up-counter into the capture register CAP 8 on the rising edge of the TI8 input signal. When the interrupt INT5 is generated on the rising edge of the TI8 input, set the CAP8 value (c) plus a delay time (d) in TREG8 and set this value (c + d) plus the one-shot pulse width (p) in TREG9. (Thus TREG8 = c + d and TREG9 = c + d + p). When the interrupt INT5 occurs, TFFCR8<EQ9T8,EQ8T8> should be set to 11 and that the TFF8 inversion is enabled only when the up-counter value matches TREG8 or TREG9. When an INTTR9 interrupt occurs, a one-shot pulse will be output and inversion will be disabled. (c), (d) and (p) correspond to c, d and p in Figure 3.8.12. Figure 3.8.12 One-shot pulse output (with delay) Timer output pin TO8 c + d + pc + dc Disables inversion caused by loading of the Inversion enable (p)(d) Pulse widthDelay time Inversi on INTTR9 occurred Load the up-counter value into Capture Register (CAP8) and INT5 occurred Count clock (internal clock) Set the counter in Free-Running Mode. TI8 pin input (external trigger pulse) Match with TREG8 Match with TREG9

Setting example: To output a 2-ms one-shot pulse with a 3-ms delay to the external trigger pulse via the TI8 pin. Main settings Keep counting (maintain free-running counter). Count using φT1. TMOD8 ← X X 1 0 1 0 0 1 Load the up-counter value into CAP8 on the rising edge TFFCR8 ← X X 0 0 0 0 1 0 of the input to the TI8 pin. Clear TFF8 to zero. Disable TFF8 inversion. PDFC ← – – - - – 1 - - Set PD2 to function as the TO8 pin. INTE56 ← X – – – X 1 0 0 Set INT5 Interrupt level to 4. INTET89 ← X 0 0 0 X 0 0 0 Disable INTTR8 and INTTR9. TRUN8 ← – 0 X X – 1 X 1 Start timer 8. Setting of INT5 TREG8 ← CAP8 + 3 ms/φT1 TREG9 ← TREG8 + 2 ms/φT1 Enable TFF8 inversion when the up-counter value matches the value of TREG8 or TREG9. INTET89 ← X 1 0 0 X – – – Enable INTTR9. Setting INTTR9 Disable TFF8 inversion when the up-counter value matches the value of TREG8 or TREG9. INTET89 ← X 0 0 0 X – – – Disable INTTR9. Note: X = Don't care; “−” = No change If no delay time is necessary, invert the timer flip-flop TFF8 when the up-counter value is loaded into the capture register (CAP8) and set the value of TREG9 to the value of CAP8 (c) plus the one-shot pulse width (p) when the interrupt INT5 occurs. TFF8 inversion should be enabled when the up-counter (UC8) value matches TREG9, and disabled when generating the interrupt INTTR9.

This mode allows the H-level width of an external pulse to be measured. With the 16-bit timer / event counter operating as a free-running counter counting the pulses from the internal cl ock input, the external pulse is input via the TI8 pin. Then, the capture function is used to load values from UC8 into CAP8 and CAP9 on the rising and falling edges of the external trigger pulse respectively. The interrupt INT5 occurs on the falling edge of TI8. The pulse width is obtained from the difference between the values in CAP8 and CAP9 and the period of the internal clock. For example, if the period of the inte rnal clock is 0.8 microseconds and the difference between the values in CAP8 and CAP9 is 100, the pulse width is 100 × 0.8 µs = 80 µs. In addition, the pulse width which is over the UC8 maximum count time specified by the clock source can be measured by changing software. Figure 3.8.15 Pulse width measurement Note: In Pulse Width Measuring Mode only (i.e. when TMOD8<CAP89M1,CAP89M0> = 10), the external interrupt INT5 occurs on the falling edge of the signal input to the TI8 pin. In other modes it occurs on the rising edge. The width of the L level is obtained by multiplying the difference between the first C9 and the second C8 at the second INT5 interrupt by the period of the internal clock. C9C8 Count clock (internal clock) TI8 pin (external pulse) Loading UC into CAP8 INT5 Loading UC into CAP9

f Time difference measurement This mode is used to measure the time difference between the rising edges of the external pulses input via TI8 and TI9. With the 16-bit timer / event counter (timer 8) operating as a free-running counter counting the pulses from the internal clock input, load the UC8 value into CAP8 on the rising edge of the signal input via TI8. This generates the interrupt INT5. Similarly, the UC8 value is loaded into CAP9 on the rising edge of the signal input via TI9, generating the interrupt INT6. The time difference between these pulses can be obtained by multiplying the value subtracted CAP8 from CAP9 and the internal clock cycle together at which loading the up-counter value into CAP8 and CAP9 has been done. Figure 3.8.16 Time difference measurement Time digerence C9C8 TI8 pin input TI9 pin input INT5 Loading UC into CAP8 INT6 Loading UC into CAP9 Count clock (internal clock)

3.9 Serial Channels

TMP92CD54I includes two serial I/O channels. For both channels either UART Mode (asynchronous transmission) or I/O Interface Mode (synchronous transmission) can be selected. In Mode 1 and Mode 2, a parity bit can be added. Mode 3 has a wake-up function for making the master controller start slave controllers in a serial link (a multi-controller) system. Serial Channels 0 and 1 can be used independently. Both channels operate in the same function ex cept for the following points; thus only the operation of Channel 0 is explained below. Table 3.9.1 Differences between Channels 0 to 1 Channel 0 Channel 1 Pin Name TXD0 (PF0) RXD0 (PF1) 0CTS /SCLK0 (PF2) TXD1 (PF3) RXD1 (PF4) CTS1 /SCLK1 (PF5) Figure 3.9.1 Data formats

• I/O Interface Mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extendin g I/O.
• UART Mode Mode 1: 7-bit data Mode 2: 8-bit data Mode 3: 9-bit data bit 0 1 2 3 45 6start stop bit 0 1 2 3 45 6start stop parity bit 0 1 2 3 45 6 bit 0 1 2 3 45 6 start stop start stop parity bit 0 1 2 3 45 6start 87 stop bit 0 1 2 3 45 6start stop (Wake-up) bit 87 When Bit 8 = 1, an address (select code) is denoted. When Bit 8 = 0, data is denoted.
• Mode 0 (I/O Interface Mode) Transfer direction
• Mode 1 (7-Bit UART Mode)
• Mode 2 (8-Bit UART Mode)
• Mode 3 (9-Bit UART Mode) No parity Parity No parity Parity 7bit 0 1 2 3 45 6

3.9.1 Block diagrams

<BR0CK1, 0> T0TRG (from timer 0) 16 32 64 84 2 φT2 φT8 φT32 φT0 BR0CR <BR0S3 to 0> BR0ADD <BR0K3 to 0> Selector Selector Selector Prescaler φT0 φT2 φT8 φT32 BR0CR <BR0ADDE> φ1(fC/2) I/O Interface Mode Selector SC0CR <IOC> SC0MOD0 <W U> Receive Counter (UART only ÷ 16) Serial channel interrupt control Transmision counter (UART only ÷ 16) Transmission Control Receive Control Receive Buffer1 (shift register) RB8 Receive Buffer2 (SC0BUF) Error flag SIOCLK UART Mode SC0MOD0 <SC1, 0> SC0MOD0 <SM1, 0> TB8 Transmission Buffer INT request INTRX0 INTTX0 SC0CR 0CTS shared with PF2 SC0MOD0 <CTSE> RXD0 shared with PF1 <PE> SC0CR <EVEN> TXDCLK SC0MOD0 <RXE> Parity control Serial clock generation circuit SCLK0 shared with PF2 SCLK0 shared with PF2 Baud rate generator RXDCLK TXD0 shared with PF0 Internal bus I/O interface mode Figure 3.9.2 Block diagram of the Serial Channel 0

<BR1CK1, 0> T0TRG (from timer 0) 16 32 64 84 2 φT2 φT8 φT32 φT0 BR1CR <BR1S3 to 0> BR1ADD <BR1K3 to 0> Selector Selector Selector Prescaler φT0 φT2 φT8 φT32 BR1CR <BR1ADDE> φ1(fC/2) I/O Interface Mode Selector I/O interface mode SC1CR <IOC> SC1MOD0 <W U> Receive Counter (UART only ÷ 16) Serial Channel Interrupt Control Transmision counter (UART only ÷ 16) Transmission Control Receive Control Receive Buffer1 (shift register) RB8 Receive buffer2 (SC1BUF) Error flag SIOCLK UART Mode SC1MOD0 <SC1, 0> SC1MOD0 <SM1, 0> TB8 Transmission Buffer INT request INTRX1 INTTX1 SC1CR 1CTS shared with PF5 SC1MOD0 <CTSE> RXD1 shared with PF4 <PE> SC1CR <EVEN> TXDCLK SC1MOD0 <RXE> Parity Control Serial clock generation circuit SCLK1 shared with PF5 SCLK1 shared with PF5 Baud rate generator RXDCLK TXD1 shared with PF3 Internal bus Figure 3.9.3 Block diagram of the Serial Channel 1

3.9.2 Operation for each circuit

(1) Prescaler, Prescaler clock select There is a 6-bit prescaler for making serial clock. The prescaler can be run by selecting the ba ud rate generator as the making serial clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator. Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator At fc=20MHz Output clock Clock resolution φT0 ( 4/fc) 0.2 µs φT2 ( 16/fc) 0.8 µs φT8 ( 64/fc) 3.2 µs φT32 (256/fc) 12.8 µs The Baud Rate Generator selects between 4 clock inputs : φT0, φT2, φT8, and φT32 among the prescaler outputs. ×4 ÷2 (10MHz) (10MHz) φT0 φT2 φT8 φT32 fIO fIO (Internal I/O clock) System clock fc (20MHz) OSC 0 1 2 3 4 5 6-bit Prescaler

(2) Baud rate generator The baud rate generator is a circuit whic h generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler. One of these input clocks is selected using the BR0CR<BR0CK1 to BR0CK0> field in the Baud Rate Generator Control Register. The baud rate generator includes a frequency divider, which divides the frequency by N (N=1 to 16) or by N + (16-K) / 16 (N=2 to 15 and K = 1 to 15). Note that the part (16-K)/16 can be disabled, resulting in a division of N. A division of N+(16-K)/16 can be [ 2+1/16; 2+2/16; …… ; 2+15/16; : ; : ; : ; : ; : ; : ; : ; : ; A division of N can be [ 1; 2; 3; …; 14; 15; 16; ] so the overall division can take any value in the range [1; N+(16-K)/16; 16] with N = 2, The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3 to BR0S0> and BR0ADD<BR0K3 to BR0K0>: BR0CR<BR0ADDE>: +(16-K)/16 division 0: Disabled 1: Enabled BR0CR<BR0S3 to BR0S0>: setting of the divided frequency 0000: N=16 (Unselectable when using the division N+(16-K)/16) 0001: N= 1 0010: N= 2 1111: N=15 BR0ADD<BR0K3 to BR0K0>: sets the frequency divisor “K” (when using the division N+(16-K)/16) 0000: Disabled 0001: K=1 1111: K=15

• In UART Mode (1) When BR0CR<BR0ADDE> = 0 - The settings BR0ADD<BR0K3 to BR0K0> are ignored. - The baud rate generator divides the selected prescaler clock by N. - N is set in BR0CK<BR0S3 to BR0S0>. (N = 1, 2, 3, …, 16) (2) When BR0CR<BR0ADDE> = 1 - The N + (16 – K) / 16 division function is enabled. - N is set in BR0CR<BR0S3 to BR0S0> (N = 2, 3, 4, …, 15) - K is set in BR0ADD<BR0K3 to BR0K0> (K = 1, 2, 3,…, 15) NOTE: At N=1 or N=16, the N+(16-K)/16 division function is disabled. Therefore set BR0CR<BR0ADDE> to “0”.

• In I/O Interface Mode - The N + (16 - K) / 16 division function is not available in I/0 Interface Mode - Set BR0CR<BR0ADDE> to “0” - Therefore the settings BR0ADD<BR0K3 to BR0K0> are ignored - The baud rate generator divides the selected prescaler clock by N - N is set in BR0CR<BR0S3 to BR0S0> (N=1, 2, 3, …, 16) The method for calculating the transfer rate when the baud rate generator is used is explained below.
• In UART Mode B a u d R a t e = ÷ 16
• In I/O Interface Mode B a u d R a t e = ÷ 2 Baud rate generator input clock frequency Frequency divider for baud rate generator Baud rate generator input clock frequency Frequency divider for baud rate generator

• Integer divider (N divider) For example, when the source clock frequency (fc) is 19.6608 MHz, the input clock is φ T2 (fc/16), the frequency divider N (BR0CR<BR0S3 to BR0S0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART Mode is as follows: Baud Rate = ÷ 16 = 19.6608 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps) Note: The N + (16 – K) / 16 division function is disabled and setting BR0ADD<BR0K3 to BR0K0> is invalid.
• N+(16-K)/16 divider (UART Mode only) Accordingly, when the source clock frequency (fc) = 15.9744 MHz, the input clock is φ T2 (fc/16), the frequency divider N (BR0CR<BR0S3 to BR0S0>) = 6, K (BR0ADD<BR0K3 to BR0K0>) = 8, and BR0CR <BR0ADDE> = 1, the baud rate in UART Mode is as follows: Baud Rate = ÷ 16 Table 3.9.3 to 4 show examples of UART Mode transfer rates. Additionally, the external clock input is available in the serial clock. (Serial Channels 0 & 1). The method for calculating the baud rate is explained below:
• In UART Mode Baud rate = external clock input frequency ÷ 16 (External clock input frequency) must be less than or equal to fc/4
• In I/O Interface Mode Baud rate = external clock input frequency (External clock input frequency) must be less than or equal to fc/16 fc/16 fc/16 6 + (16 – 8)/16

Table 3.9.3 Selection of Transfer Rate(1) (when baud rate generator Is used and BR0CR <BR0ADDE> = 0) fc [MHz] Input Clock Frequency Divider φT0 (4/fc) φT2 (16/fc) φT8 (64/fc) φT32 (256/fc) 16 19.200 4.800 1.200 0.300 Note: Transfer rates in I/O Interface Mode are eight times faster than the values given above. Table 3.9.4 Selection of Transfer Rate(2) (When timer 0 with input Clock φT1 is used) fc TREG0 MHz 19.6608 MHz MHz 02H 76.8 62.5 04H 38.4 31.25 05H 31.25 08H 19.2 10H 9.6 Method for calculating the transfer rate (when timer 0 is used): Note: The timer 0 match detect signal cannot be used as the transfer clock in I/O Interface Mode. Unit (kbps) Unit (kbps) Transfer rate = fc TREG0 × 8 × 16 (when timer 0 (input clock φT1) is used)

(3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data.

• In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK Input Mode with the setting SC0CR<IOC> = 1, the rising edge or falling edge will be detected according to the setting of the SC0CR<SCLKS> register to generate the basic clock.
• In UART Mode The SC0MOD0 <SC1, SC0> setting determ ines whether the baud rate generator clock, the internal clock φ1 (fc/2), the match detect signal from timer 0 or the external clock (SCLK0) is used to generate the basic clock SIOCLK. (4) Receiving counter The receiving counter is a 4-bit binary counter used in UART Mode which counts up the pulses of the SIOCLK cloc k. It takes 16 SIOCLK pulses to receive 1 bit of data; each data bit is sampled three times – on the 7th, 8th and 9th clock cycles. The value of the data bit is determined fr om these three samples using the majority rule. For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is taken to be 0. (5) Receiving control
• In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the RXD0 signal is sampled on the rising edge of the shift clock which is output on the SCLK0 pin. In SCLK Input Mode with the setting SC0CR<IOC> = 1, the RXD0 signal is sampled on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.
• In UART Mode The receiving control block has a circuit which detects a start bit using the majority rule. Received bits are sampled three times; when two or more out of three samples are 0, the bit is recognized as the start bit and the receiving operation commences. The values of the data bits that are received are also determined using the majority rule.

(6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving Buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads Receiving Buffer 2 (SC0BUF). Even before the CPU has finished reading the contents of Receiving Buffer 2 (SC0BUF), more data can be received and stored in Receiving Buffer 1. However, if Receiving Buffer 2 (SC0BUF) has not been read completely before all the bits of the next data item are received by Receiving Buffer 1, an Overrun error occurs. If an Overrun error occurs, the contents of Receiving Buffer 1 will be lost, althou gh the contents of Re ceiving Buffer 2 and SC0CR<RB8> will be preserved. SC0CR<RB8> is used to store either the parity bit – added in 8-Bit UART Mode – or the most significant bit (MSB) – in 9-Bit UART Mode. In 9-Bit UART Mode the wake-up function for the slave controller is enabled by setting SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the value of SC0CR<RB8> is 1. (7) Transmission counter The transmission counter is a 4-bit binary counter which is used in UART Mode and which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16 SIOCLK clock pulses. SIOCLK TXDCLK 15 1612 4 5 67 89 1 0 11 12 13 1415 16 3 1 2 Figure 3.9.5 Generation of the transmission clock (8) Transmission controller

• In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the data in the Transmission Buffer is output one bit at a time to the TXD0 pin on the rising edge of the shift clock which is output on the SCLK0 pin. In SCLK Input Mode with the setting SC0CR<IOC> = 1, the data in the Transmission Buffer is output one bit at a time to the TXD0 pin on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.
• In UART Mode When transmission data sent from the CPU is written to the Transmission Buffer, transmission starts on the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT.

(9) Transmission Buffer The Transmission Buffer (SC0BUF) shifts out and sends the transmission data written from the CPU, in order one bit at a time starting with the least significant bit (LSB) and finishing with the most significant bit (MSB). When all the bits have been shifted out, the empty Transmission Buffer generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR<PE> in the Serial Channel Control Register is set to 1, it is possible to transmit and receive data with parity. However, parity can be added only in 7-Bit UART Mode or 8-Bit UART Mode. The SC0CR<EVEN> field in the Serial Channel Control Register allows either even or odd parity to be selected. In the case of transmission, parity is automatically generated when data is written to the Transmission Buffer SC0BUF. The data is transmitted after the parity bit has been stored in SC0BUF<TB7> in 7-Bit UART Mode or in SC0MOD0<TB8> in 8-Bit UART Mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission data is written to the Transmission Buffer. In the case of receiving, data is shifted into Receiving Buffer 1, and the parity is added after the data has been transferred to Receiving Buffer 2 (SC0BUF), and then compared with SC0BUF<RB7> in 7-Bit UART Mode or with SC0CR<RB8> in 8-Bit UART Mode. If they are not equal, a Parity error is generated and the SC0CR<PERR> flag is set. (11) Error flags Three error flags are provided to increase the reliability of data reception. 1. Overrun error <OERR> If all the bits of the next data item have been received in Receiving Buffer 1 while valid data still remains stored in Receiving Buffer 2 (SC0BUF), an Overrun error is generated. The below is a processing example of when Overrun error is occurred. (INTRX routine) 1)Read Received-Buffer 2)Read error-flag 3)if<OERR>=1 then 4)Disable receiving(write 0 to <RXE>) 5)Wait for terminating current frame 6)Read received-buffer 7)Readerror-flag 8)Enable receiving(write 1 to <RXE>) 9)Request to resend 10)Process other job 2. Parity error <PERR> The parity generated for the data shifted into Receiving Buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a Parity error is generated. 3. Framing error <FERR> The stop bit for the received data is sampled three times around the center. If the majority of the samples are 0, a Framing error is generated.

(12) Timing generation c In UART Mode Receiving Mode 9-Bit (Note) 8-Bit + Parity (Note) 8-Bit, 7-Bit + Parity, 7-Bit Interrupt timing Center of last bit (bit 8) Center of last bit (parity bit) Center of stop bit Framing error timing Center of stop bit Center of stop bit Center of stop bit Parity error timing - Center of last bit (parity bit) Center of last bit (parity bit) Overrun error timing Center of last bit (bit 8) Center of last bit (parity bit) Center of stop bit Note: In 9-Bit Mode and 8-Bit + Parity Mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to allow a 1-bit period to elapse (so that the stop bit can be transferred) in order to allow proper framing error checking. Transmitting Mode 9-Bit 8-Bit + Parity 8-Bit, 7-Bit + Parity, 7-Bit Interrupt timing Just before stop bit is transmitted Just before stop bit is transmitted Just before stop bit is transmitted d I/O interface SCLK Output Mode Immediately after rise of last SCLK signal. (See figure 3.9 20.) Transmission Interrupt timing SCLK Input Mode Immediately after rise of last SCLK signal Rising Mode, or immediately after fall in Falling Mode. (See figure 3.9 21.) SCLK Output Mode Timing used to transfer received data to Receive Buffer 2 (SC0BUF) Interrupt timing SCLK Input Mode Timing used to transfer received data to Receive Buffer 2 (SC0BUF)

3.9.3 SFR

Bit symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0 Read/Write R/W After Reset undefined 0 0 0 0 0 0 0 Function Transfer data bit 8 Hand shake 0: CTS disable 1: CTS enable Receive function 0: Receive disable 1: Receive enable Wa ke up function 0: disable 1: enable Serial Transmission Mode 00: I/O interface Mode 01: 7-bit UART Mode 10: 8-bit UART Mode 11: 9-bit UART Mode Serial transmission clock (UART) 00: T0TRG 01: Baud rate generator 10: Internal clock φ1 11: External clcok (SCLK0 input) Serial transmission clock source (UART)

00 Timer 0 match detect signal (T0TRG)

01 Baud rate generator

10 Internal clock φ1

11 External clock (SCLK0 input)

Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC0CR). Serial Transmission Mode

00 I/O Interface Mode

0 Interrupt generated when

1 Interrupt generated only

when RB8 = 1

0 Receive disabled

1 Receive enabled

0 Disabled (always transferable)

Handshake function (CTS pin) Enable Transmission data bit 8 Don’t care SC0MOD0 (00C2H) Figure 3.9.8 Serial Mode Control Register (channel 0, SC0MOD0)

Bit symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0 Read/Write R/W After Reset undefined 0 0 0 0 0 0 0 Function Transfer data bit 8 Hand shake 0: CTS disable 1: CTS enable Receive function 0: Receive disable 1: Receive enable Wa ke up function 0: disable 1: enable Serial Transmission Mode 00: I/O interface Mode 01: 7-bit UART Mode 10: 8-bit UART Mode 11: 9-bit UART Mode Serial transmission clock (UART) 00: T0TRG 01: Baud rate generator 10: Internal clock φ1 11: External clcok (SCLK1 input) Serial transmission clock source (UART)

11 External clock (SCLK1 input)

Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC1CR). Serial Transmission Mode when RB8 = 1 Don’t care SC1MOD0 (00CAH) Handshake function (CTS pin) Enable Figure 3.9.9 Serial Mode Control Register (channel 1, SC1MOD0)

bit Symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC Read/Write R R/W R(cleared to 0 when read) R/W After Reset undefined 0 0 0 0 0 0 0 Function Received data bit 8 Parity 0: odd 1: even Parity addition 0: disable 1: enable Overrun Parity Framing 0: SCLK0 1: SCLK0 0: baud rate generator 1: SCLK0 pin input SC0CR (00C1H) I/O interface input clock selection Framing Error flag Parity Error flag Overrun Error flag

0 Transmits and receivers

data on rising edge of SCLK0.

1 Transmits and receivers

data on falling edge SCLK0. Edge selection for SCLK0 pin (Input Mode Only) Even parity addition/check 1: error

0 Baud rate generator

1 SCLK0 pin input

1 Even parity

Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction. Figure 3.9.10 Serial Control Register (channel 0, SC0CR)

bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC Read/Write R R/W R (cleared to 0 when) R/W After Reset undefined 0 0 0 0 0 0 0 Function Received data bit 8 Parity 0: odd 1: even Parity addition 0: disable 1: enable Overrun Parity Framing 0: SCLK1 1: SCLK1 0: baud rate generator 1: SCLK1 pin input SC1CR (00C9H) I/O interface input clock select Framing Error flag Parity Error flag Overrun Error flag

0 Transmits and receives

data on rising edge of SCLK1.

1 Transmits and receives

data on falling edge of SCLK1. Edge selection for SCLK1 pin (input mode only) Even parity addition/check 1: error

1 SCLK1 pin input

0 Odd parity

Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction. Figure 3.9.11 Serial Control Register (channel 1, SC1CR)

bit Symbol － BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function (Note) Always fixed to “0” +(16 −K)/16 division 0: Disable 1: Enable 00 : φT0 01 : φT2 10 : φT8 11 : φT32 7 6 5 4 3 2 1 0 Bit symbol BR0K3 BR0K2 BR0K1 BR0K0 Read/Write R/W After Reset 0 0 0 0 Function Set frequency divisor K (divided by N + (16 − K)/16) Baud rate generator frequency divisor setting BR0CR<BR0ADDE> = 1 (UART only) BR0CR<BR0ADDE> = 0 (UART and I/O interface modes) BR0CR <BR0S3:0> BR0ADD <BR0K3:0> 0000(N = 16) or 0001(N = 1) 0010(N = 2) to 1111(N = 15) 0001(N = 1) (UART Only) to 1111(N = 15) 0000(N = 16)

0000 Disable * Disable *

0001(K = 1) to 1111(K = 15) Disable * Divided by N + (16 − K) / 16 Divided by N *: as the N+(16-K)/16 division function is disabled in UART mode, set BR0ADDE to “0” Division by N with N=[1;2;3;…;16] Note 1: Set BR0CR <BR0ADDE> to “1” after setting K (K = 1 to 15) to BR0ADD <BR0K3 to 0> when + (16 − K) / 16 division function is used. Note 2: + (16 − K) / 16 division functions is possible to use in only UART mode. Set BR0CR <BR0ADDE> to “0” to disable + (16 − K) / 16 division in I/O interface mode. Figure 3.9.12 Baud rate generator control (channel 0, BR0CR, BR0ADD) +(16 - K) / 16 division enable

00 Internal clock φT0

01 Internal clock φT2

10 Internal clock φT8

11 Internal clock φT32

Input clock selection for baud rate generator Setting of the divided frequency BR0CR (00C3H) BR0ADD (00C4H)

bit Symbol - BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function (Note) Always fixed to “0” +(16 −K)/16 division 0: Disable 1: Enable 00 : φT0 01 : φT2 10 : φT8 11 : φT32 7 6 5 4 3 2 1 0 Bit symbol - - - - BR1K3 BR1K2 BR1K1 BR1K0 Read/Write R/W After Reset - - - - 0 0 0 0 Function Set frequency divisor K (divided by N + (16 − K)/16) Baud rate generator frequency divisor setting BR1CR<BR1ADDE> = 1 (UART only) BR1CR<BR1ADDE> = 0 (UART and I/O interface modes) BR1CR <BR1S3:0> BR1ADD <BR1K3:0> 0000(N = 16) or 0001(N = 1) 0010(N = 2) to 1111(N = 15) 0001(N = 1) (UART Only) to 1111(N = 15) 0000(N = 16) 0001(K = 1) to 1111(K = 15) Disable * Divided by N + (16 − K) / 16 Divided by N *: as the N+(16-K)/16 division function is disabled in UART mode, set BR1ADDE to “0” Division by N with N=[1;2;3;…;16] Note 1: Set BR1CR <BR1ADDE> to “1” after setting K (K = 1 to 15) to BR1ADD <BR1K3 to 0> when + (16 − K) / 16 division function is used. Note 2: + (16 − K) / 16 division functions is possible to use in only UART mode. Set BR1CR <BR1ADDE> to “0” to disable + (16 − K) / 16 division in I/O interface mode. Figure 3.9.13 Baud rate generator control (channel 1, BR1CR, BR1ADD) BR1CR (00CBH) +(16 - K) / 16 division enable Input clock selection for baud rate generator Setting of the divided frequency BR1ADD (00CCH)

3.9.4 Operation for each mode

(1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input external synchronous clock SCLK. Output extension TMP92CD54I TXD SCLK Port Input extension TC74HC595 or equivalent TC74HC165 or equivalent TMP92CD54IA B C D E F G H RxD SCLK Port Shift register A B C D E F G H SI SCK RCK QH CLOCK Shift register S/L Figure 3.9.18 Example of SCLK Output Mode Connection TMP92CD54I TXD SCLK Port TMP92CD54IA B C D E F G H RxD SCLK Port Shift register A B C D E F G H SI SCK RCK QH CLOCK External clock Output extension Input extension TC74HC595 or equivalent TC74HC165 or equivalent External clock Shift register S/L Figure 3.9.19 Example of SCLK Input Mode Connection

e Transmission and Receiving (Full Duplex Mode) When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output Baud rate = 9600 bps fc = 19.6608 MHz Main routine 7 6 5 4 3 2 1 0 INTES0 X 0 0 1 X 0 0 0 Set the INTTX0 level to 1. Set the INTRX0 level to 0. PFCR – – – – – 1 0 1 Set PF0, PF1 and PF2 to function as the TXD0, RXD0 PFFC – – – – – 1 – 1 and SCLK0 pins respectively SC0MOD0 0 0 0 0 0 0 0 0 Select I/O Interface Mode. SC0MOD1 1 1 0 0 0 0 0 0 Select Full Duplex Mode. SC0CR 0 0 0 0 0 0 0 0 Sclk_out, transmit on negative edge, receive on positive edge BR0CR 0 0 1 1 0 1 0 0 Baud rate = 9600 bps SC0MOD0 0 0 1 0 0 0 0 0 Enable receiving SC0BUF * * * * * * * * Set the transmit data and start. INTTX0 interrupt routine Acc ← SC0BUF Read the receiving buffer. SC0BUF * * * * * * * * Set the next transmit data. Note: X = Don't care; “−” = No change

(2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0<SM1,SM0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the Serial Channel Control Register SC0CR<PE> bit; whether even parity or odd parity will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (enabled). Setting example: When transmitting data of the following format, the control registers should be set as described below. 7 6 5 4 3 2 1 0 PFFC ← − − − − − − − 1 Set PF0 to function as the TXD0 pin. SC0MOD0 ← X 0 − X 0 1 0 1 Select 7-Bit UART Mode. SC0CR ← X 1 1 X X X 0 0 Add even parity. BR0CR ← 0 0 1 0 1 0 0 0 Set the transfer rate to 2400 bps. INTES0 ← X 1 0 0 − − − − Enable the INTTX0 interrupt and set it to Interrupt Level 4. SC0BUF ← * * * * * * * * Set data for transmission. Note: X = Don’t care; “−” = No change (3) Mode 2 (8-Bit UART Mode) 8-Bit UART Mode is selected by setting SC0MOD0<SM1,SM0> to 10. In this mode a parity bit can be added (use of a parity bit is enabled or disabled by the setting of SC0CR<PE>); whether even parity or odd parity will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (enabled). Setting example: When receiving data of the following format, the control registers should be set as described below. Transmission direction (transmission rate: 2400 bps at fc = 19.6608 MHz) start bit 0 1 2 3 5 4 6 even parity stop Transmission direction (transmission rate: 9600 bps at fc = 19.6608 MHz) start bit 0 1 2 3 5 4 6 odd parity stop 7

PFCR ← − − − − − − 0 − Set PF1 to function as the RXD0 pin. SC0MOD0 ← − 0 1 X 1 0 0 1 Enable receiving in 8-Bit UART Mode. SC0CR ← X 0 1 X X X 0 0 Add odd parity. BR0CR ← 0 0 0 1 1 0 0 0 Set the transfer rate to 9600 bps. INTES0 ← − − − − X 1 0 0 Enable the INTTX0 interrupt and set it to Interrupt Level 4. Interrupt processing Acc ← SC0CR AND 00011100 if Acc ≠ 0 then ERROR Check for errors. Acc ← SC0BUF Read the received data. Note: X = Don’t care; “−” = No change (4) Mode 3 (9-Bit UART Mode) 9-Bit UART Mode is selected by setting SC0MOD0<SM1,SM0> to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the MSB is read or written first, before the rest of the SC0BUF data. Wake-up function In 9-Bit UART Mode, the wake-up function for slave controllers is enabled by setting SC0MOD0<WU> to 1. The interrupt INTRX0 can only be generated when<RB8> = 1. TXD Master Slave 1 Slave 2 Slave 3 RXD TXD RXD TXD TXD RXD RXD Note: The TXD pin of each slave controller must be in Open-Drain Output Mode. Figure 3.9.24 Serial Link using Wake-up function

c Select 9-Bit UART Mode on the master and slave controllers. d Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. e The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller. The MSB (bit 8) of the data (<TB8>) is set to 1. Select code of slave controller start bit 0 1 2 3 5 46 s t o p 78 “1” f Each slave controller receives the above frame. Each controller checks the above select code against its own select code. The controller whose code matches clears its <WU> bit to 0. g The master controller transmits data to the specified slave controller (the controller whose SC0MOD0<WU> bit has been cleared to 0). The MSB (bit 8) of the data (<TB8>) is cleared to 0. Data “0” start bit 0 1 2 3 5 4 6 stop 7b i t 8 h The other slave controllers (whose <WU> bits remain at 1) ignore the received data because their MSBs (bit 8 or <RB8>) are set to 0, disabling INTRX0 interrupts. The slave controller whose <WU> bit = 0 can also transmit to the master controller. In this way it can signal the master controller that the data transmission from the master controller has been completed.

Setting example: To link two slave controllers serially with the master controller using the internal clock φ1 as the transfer clock. TXD Master Slave 1 Slave 2 Select code 00000001 RXD TXD RXD TXD RXD Select code 00001010

• Setting the master controller Main Set PF0 and PF1 to function as the TXD0 and RXD0 pins respectively. INTES0 ← X 1 0 0 X 1 0 1 Enable the INTTX0 interrupt and set it to Interrupt Level 4. Enable the INTRX0 interrupt and set it to Interrupt Level 5. SC0MOD0 ← 1 0 1 0 1 1 1 0 Set φ1 as the transmission clock for 9-Bit UART Mode. SC0BUF ← 0 0 0 0 0 0 0 1 Set the select code for slave controller 1. INTTX0 interrupt SC0BUF ← * * * * * * * * Set data for transmission.
• Setting the slave controller Main PFCR ← − − − − − − 00 Select PF1 and PF0 to function as the RXD0 and TXD0 pins PFFC ← - - - - - - - 1 respectively (open-drain output). INTES0 ← X 1 0 1 X 1 1 0 Enable INTRX0 and INTTX0. SC0MOD0 ← 0 0 1 1 1 1 1 0 Set <WU> to 1 in 9-Bit UART Transmission Mode using φ1 as the transfer clock. INTRX0 interrupt Acc ← SC0BUF if Acc = select code then SC0MOD0 ← - - - 0 - - - - Clear <WU> to 0.

3.10 Serial Bus Interface (SBI)

TMP92CD54I has 3-channels serial bus interface which employs a clocked-synchronous 8-bit SIO mode and an I2C bus mode. It is called SBI0, SBI1 and SBI2. I 2C bus Clocked-synchronous 8-bit SIO SBI0 SCL0 (PN2), SDA0 (PN1) PNODE<ODEN2, ODEN1> SCK0 (PN0), SO0 (PN1), SI0 (PN2) SBI1 SCL1 (PN5), SDA1 (PN4) PNODE<ODEN5, ODEN4> SCK1 (PN3), SO1 (PN4), SI1 (PN5) SBI2 SCL2 (P72), SDA2 (PN6) PNODE<ODE72, ODEN6> SCK2 (PM4), SO2 (PN6), SI2 (P72) Since each channel carries out the same operation, it explains only SBI0. The serial bus interface is connected to an external device through PN1 (SDA0) and PN2 (SCL0) in the I 2C bus mode; and through PN0 (SCK0), PN1 (SO0) and PN2 (SI0) in the clocked-synchronous 8-bit SIO mode. Each pin is specified as follows. PNODE <ODEN2, ODEN1> PNCR <PN2C, PN1C, PN0C> PNFC <PN2F, PN1F, PN0F> I2C Bus Mode 11 11X 11X Clocked Synchronous 8-Bit SIO Mode XX 011 010 011 X: Don’t care

3.10.1 Configuration

I C bus Clock Sync. Control Noise Canceller Shift Register SBI0CR2/ SBI0SR SBI0DBR INTSBS0 Interrupt request (stop condition) φT SBI0 Control Register 2/ SBI0 Status Register I2C bus 0 Address Register SBI0 Data Buffer Register SBI0 Control Register 1 SBI0 baud rate Ragister 0, 1 SDA0 SO0 SI0 SCL0 SCK0 PN0 PN1 PN2 (SCK0) (SO0/SDA0) (SI0/SCL0) SIO Clock Control Divider SBI0CR1 SBI0BR0, 1 Nosie Canceller I2C bus Data Control SIO Data Control Input/ Output Control INTSBE0 Interrupt request (address / data) I2C0AR Transfer Control Circuit Figure 3.10.1 Serial Bus Interface 0 (SBI0)

3.10.2 Serial Bus Interface (SBI) Control

The following registers are used to control the serial bus interface and monitor the operation status.

• Serial bus interface 0 control register 1 (SBI0CR1)
• Serial bus interface 0 control register 2 (SBI0CR2)
• Serial bus interface 0 data buffer register (SBI0DBR)
• I2C bus 0 address register (I2C0AR)
• Serial bus interface 0 status register (SBI0SR)
• Serial bus interface 0 baud rate register 0 (SBI0BR0)
• Serial bus interface 0 baud rate register 1 (SBI0BR1) The above registers differ depending on a mode to be used. Refer to Section “3.10.4 I2C bus Mode Control” and “3.10.7 Clocked-synchronous 8-bit SIO Mode Control”.

3.10.3 The Data Formats in the I 2C Bus Mode

The data formats in the I2C bus mode are shown below. S (a) Addressing format (b) Addressing format (with restart) (c) Free data format (data transferred from master device to slave device) Slave address Data A C K P S S SP P 8 bits 1 to 8 bits1 1 1 or more 1 to 8 bits A C K A C K Slave address Data Data A C K A C K A C K A C K 8 bits 1 to 8 bits 8 bits 1 to 8 bits 1 1 1 1 8 bits 1 to 8 bits 1 to 8 bits Data Data Data Data A C K A C K A C K 1 1 1 Slave address 1 or more 1 1 or more 1 or more R W R W R W Note: S: Start condition : Direction bit ACK: Acknowledge bit P: Stop condition R / W Figure 3.10.2 Data Format in the I2C Bus Mode

3.10.4 I 2C Bus Mode Control Register

The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode. Seirial Bus Interface 0 Conrol Register 1 7 6 5 4 3 2 1 0 Bit Symbol BC2 BC1 BC0 ACK SCK3 SCK2 SCK1 SWRMON/ SCK0 Read/Write W R/W W R/W After Reset 0 0 0 0 1 0 0 1/0(Note3) Function Number of transferred bits (Note 1) Acknowledge mode specification 0: Not generate 1: Generate Internal serial clock selection and software reset monitor (Note 2) Internal serial clock selection <SCK3 to 0> @ write 0001 0010 0011 0100 0101 0110 1000 1111 other n = 6 n = 7 n = 8 n = 9 n = 10 n = 11 Fast Standard 75.8 kHz 38.5 kHz 19.4 kHz 9.73 kHz 4 0 0 k H z 1 0 0 k H z (reserved) CPU clock: fc = 20 MHz internal SCL output ( f s c l = [ Hz ] ) ( fscl = fc/50 [ Hz ] ) ( fscl = fc/200 [ Hz ] ) Software reset state monitor <SWRMON> @ read

0 During software reset

1 Initial data

Acknowledge mode specification

0 Not generate clock pulse for acknowledge signal

1 Generate clock pulse for acknowledge signal

Number of bits transferred <ACK> = 0 <ACK> = 1 <BC2 : 0> Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 SBI0CR1 (0170H) Note 1: Set the <BC2 to 0> to “000” before switching to a clock-synchronous 8-bit SIO mode. Note 2: For the frequency of the SCL line clock, see 3.10.5 (3) Serial clock. Note 3: Initial data of SCK0 is “0”, SWRMON is “1”. fc 2n + 8 Prohibit Read- modify-write Figure 3.10.3 Registers for the I2C Bus Mode

Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Bit Symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 Read/Write W W (Note 1) W (Note 1) After Reset 0 0 0 1 0 0 0 0 Function Master/Slave selection Transmitter/ Receiver selection Start/Stop generation Cancel INTSBE0 interrupt request Serial bus interface operating mode selection (note 2) 00: Port Mode 01: SIO Mode 10: I2C Bus Mode 11: (reserved) Software reset generate write “10” and “01”, then an internal reset signal is generated. Serial bus interface operating mode selection (Note 2)

00 Port Mode (Serial Bus Interface output disabled)

01 Clocked Synchronous 8-Bit SIO Mode

10 I2C Bus Mode

11 (reserved) INTSBE0 interrupt request 0 −

1 Cancel interrupt request

0 Generates the stop condition

1 Generates the start condition

Transmitter / receiver selection

0 Receiver

1 Transmitter

(0173H) Note1: Reading this register function as SBI0SR register. Note2: Switch a mode to port mode after confirming that the bus is free. Switch a mode between I2C bus mode and clock-synchronous 8-bit SIO mode after confirming that input signals via port are high-level. Prohibit Read- modify-write Figure 3.10.4 Registers for the I2C Bus Mode

Serial Bus Interface 0 Status Register 7 6 5 4 3 2 1 0 Bit Symbol MST TRX BB PIN AL AAS AD0 LRB Read/Write R After reset 0 0 0 1 0 0 0 0 Function Master/ Slave status monitor Transmitter/ Receiver status monitor I C bus status monitor INTSBE0 interrupt request monitor Arbitration lost detection monitor 0: − 1: Detected Slave address match detection monitor Undetected 1: Detected GENERAL CALL detection monitor Undetected 1: Detected Last received bit monitor 0: “0” 1: “1” Last received bit monitor

0 Last received bit was “0”

1 Last received bit was “1”

GENERAL CALL detection monitor

0 Undetected

1 GENERAL CALL detected

Slave address match detection monitor

1 Slave address match or GENERAL

Arbitration lost detection monitor 0 −

1 Arbitration lost

INTSBE0 interrupt request monitor

0 Interrupt requested

1 Interrupt canceled

0F r e e ( N o t e 2 ) 1B u s y Transmitter / receiver status monitor Master / Slave status monitor 0S l a v e 1M a s t e r SBI0SR (0173H) Prohibit Read- modify-write Note1: Writing in this register functions as SBI0CR2. Note2: If SBI0SR<BB> drops down from 1 to 0 (falling edge), INTSBS0 will be generated in both case of Master mode and Slave mode. Figure 3.10.5 Registers for the I2C Bus Mode

Serial Bus Interface 0 Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit Symbol - I2SBI0 - - - - - - Read/Write W R/W After Reset 0 0 - - - - - - Function (Note) Fixed to “0” IDLE2 0: Stop 1: Run Operation during IDLE 2 Mode

0 Stop

Serial Bus Interface 0 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit Symbol P4MON/ P4EN - - - - - - - Read/Write R/W After Reset 0 - - - - - - - Function Internal clock 0: Stop 1: Operate Baud rate clock control Sirial Bus Interface 0 Data Buffer Register 7 6 5 4 3 2 1 0 Bit Symbol RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Read/Write R (received)/W (transfer) After Reset Undefined Note: When writing transmitted data, start from the MSB (bit 7). I2C Bus 0 Address Register 7 6 5 4 3 2 1 0 Bit Symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS Read/Write W After Reset 0 0 0 0 0 0 0 0 Function Slave address selection for when device is operating as slave device Addressing or free dat a format Address recognition mode specification

0 Addressing format

1 Free data format

(0174H) SBI0DBR (0171H) I2C0AR (0172H) Prohibit Read- modify-write Prohibit Read- modify-write SBI0BR1 (0175H) Prohibit Read- modify-write Addressing or free data format impact both slave and master configuration. When addressing format is used (<ALS>=0), TRX bit is updated relying on R/W bit (=8 th bit of first received byte after start condition). Moreover in slave mode, MCU spies the bus after start condition to recognize its address. When free data format is used (<ALS>=1) all words on the bus are considered as data words, that means no address recognition is done and TRX is not updated. Figure 3.10.6 Registers for the I2C Bus Mode

Seirial Bus Interface 1 Conrol Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK SCK3 SCK2 SCK1 SWRMON/ SCK0 Read/Write W R/W W R/W After Reset 0 0 0 0 1 0 0 1/0(Note3) Function Number of transferred bits (Note 1) Acknowledge mode specification 0: Not generate 1: Generate Internal serial clock selection and software reset monitor (Note 2) Internal serial clock selection <SCK3 to 0> @ write 0001 0010 0011 0100 0101 0110 1000 1111 other n = 6 n = 7 n = 8 n = 9 n = 10 n = 11 Fast Standard 75.8 kHz 38.5 kHz 19.4 kHz 9.73 kHz 400 kHz 100 kHz (reserved) CPU clock: fc = 20 MHz internal SCL output (fscl = [ Hz ] ) (fscl = fc/50 [ Hz ] ) (fscl = fc/200 [ Hz ] ) Software reset state monitor <SWRMON> @ read Acknowledge mode specification Number of bits transferred <ACK> = 0 <ACK> = 1 <BC2 : 0> Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 SBI1CR1 (0178H) Note 1: Set the <BC2 to 0> to “000” before switching to a clock-synchronous 8-bit SIO mode. Note 2: For the frequency of the SCL line clock, see 3.10.5 (3) Serial clock. Note 3: Initial data of SCK0 is “0”, SWRMON is “1”. Prohibit Read- modify-write fc 2n + 8 Figure 3.10.7 Registers for the I2C Bus Mode

Serial Bus Interface 1 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 Read/Write W W (Note 1) W (Note 1) After Reset 0 0 0 1 0 0 0 0 Function Master/Slave selection Transmitter/ Receiver selection Start/Stop generation Cancel INTSBE1 interrupt request Serial bus interface operating mode selection (note 2) 00: Port Mode 01: SIO Mode 10: I2C Bus Mode 11: (reserved) Software reset generate write “10” and “01”, then an internal reset signal is generated. Serial bus interface operating mode selection (Note 2) 11 (reserved) INTSBE1 interrupt request 0 − Transmitter / receiver selection (017BH) Note1: Reading this register function as SBI1SR register. Note2: Switch a mode to port mode after confirming that the bus is free. Switch a mode between I2C bus mode and clock-synchronous 8-bit SIO mode after confirming that input signals via port are high-level. Prohibit Read- modify-write Figure 3.10.8 Registers for the I2C Bus Mode

Serial Bus Interface 1 Status Register 7 6 5 4 3 2 1 0 Bit Symbol MST TRX BB PIN AL AAS AD0 LRB Read/Write R After reset 0 0 0 1 0 0 0 0 Function Master/ Slave status monitor Transmitter/ Receiver status monitor I C bus status monitor INTSBE1 interrupt request monitor Arbitration lost detection monitor 0: − 1: Detected Slave address match detection monitor Undetected 1: Detected GENERAL CALL detection monitor Undetected 1: Detected Last received bit monitor 0: “0” 1: “1” Last received bit monitor GENERAL CALL detection monitor Slave address match detection monitor Arbitration lost detection monitor 0 − INTSBE1 interrupt request monitor 0F r e e ( N o t e 2 ) 1B u s y Transmitter / receiver status monitor 0R e c e i v e r 1T r a n s m i t t e r Master / Slave status monitor 0S l a v e 1M a s t e r SBI1SR (017BH) Prohibit Read- modify-write Note1: Writing in this register functions as SBI1CR2. Note2: If SBI1SR<BB> drops down from 1 to 0 (falling edge), INTSBS1 will be generated in both case of Master mode and Slave mode. Figure 3.10.9 Registers for the I2C Bus Mode

Serial Bus Interface 1 Baud Rate Regster 0 7 6 5 4 3 2 1 0 Bit Symbol - I2SBI0 - - - - - - Read/Write W R/W After Reset 0 0 - - - - - - Function (Note) Fixed to “0” IDLE2 0: Stop 1: Run Operation during IDLE 2 Mode Serial Bus Interface 1 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4MON/ P4EN - - - - - - - Read/Write R/W After Reset 0 - - - - - - - Function Internal clock 0: Stop 1: Operate Baud rate clock control Sirial Bus Interface 1 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Read/Write R (received)/W (transfer) After Reset Undefined Note: When writing transmitted data, start from the MSB (bit 7). I2C Bus 1 Address Register 7 6 5 4 3 2 1 0 Bit Symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS Read/Write W After Reset 0 0 0 0 0 0 0 0 Function Slave address selection for when device is operating as slave device Addressing or free dat a format Address recognition mode specification (017CH) SBI1DBR (0179H) I2C1AR (017AH) Prohibit Read- modify-write Prohibit Read- modify-write SBI1BR1 (017DH) Prohibit Read- modify-write Addressing or free data format impact both slave and master configuration. When addressing format is used (<ALS>=0), TRX bit is updated relying on R/W bit (=8 th bit of first received byte after start condition). Moreover in slave mode, MCU spies the bus after start condition to recognize its address. When free data format is used (<ALS>=1) all words on the bus are considered as data words, that means no address recognition is done and TRX is not updated. Figure 3.10.10 Registers for the I2C Bus Mode

Seirial Bus Interface 2 Conrol Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK SCK3 SCK2 SCK1 SWRMON/ SCK0 Read/Write W R/W W R/W After Reset 0 0 0 0 1 0 0 1/0(Note3) Function Number of transferred bits (Note 1) Acknowledge mode specification 0: Not generate 1: Generate Internal serial clock selection and software reset monitor (Note 2) Internal serial clock selection <SCK3 to 0> @ write 0001 0010 0011 0100 0101 0110 1000 1111 other n = 6 n = 7 n = 8 n = 9 n = 10 n = 11 Fast Standard 75.8 kHz 38.5 kHz 19.4 kHz 9.73 kHz 400 kHz 100 kHz (reserved) CPU clock: fc = 20 MHz internal SCL output (fscl = [ Hz ] ) (fscl = fc/50 [ Hz ] ) (fscl = fc/200 [ Hz ] ) Software reset state monitor <SWRMON> @ read Acknowledge mode specification Number of bits transferred <ACK> = 0 <ACK> = 1 <BC2 : 0> Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 SBI2CR1 (0180H) Note 1: Set the <BC2 to 0> to “000” before switching to a clock-synchronous 8-bit SIO mode. Note 2: For the frequency of the SCL line clock, see 3.10.5 (3) Serial clock. Note 3: Initial data of SCK0 is “0”, SWRMON is “1”. Prohibit Read- modify-write fc 2n + 8 Figure 3.10.11 Registers for the I2C Bus Mode

Serial Bus Interface 2 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 Read/Write W W (Note 1) W (Note 1) After Reset 0 0 0 1 0 0 0 0 Function Master/Slave selection Transmitter/ Receiver selection Start/Stop generation Cancel INTSBE1 interrupt request Serial bus interface operating mode selection (note 2) 00: Port Mode 01: SIO Mode 10: I2C Bus Mode 11: (reserved) Software reset generate write “10” and “01”, then an internal reset signal is generated. Serial bus interface operating mode selection (Note 2) 11 (reserved) INTSBE1 interrupt request 0 − Transmitter / receiver selection (0183H) Note1: Reading this register function as SBI2SR register. Note2: Switch a mode to port mode after confirming that the bus is free. Switch a mode between I2C bus mode and clock-synchronous 8-bit SIO mode after confirming that input signals via port are high-level. Prohibit Read- modify-write Figure 3.10.12 Registers for the I2C Bus Mode

Serial Bus Interface 2 Status Register 7 6 5 4 3 2 1 0 Bit Symbol MST TRX BB PIN AL AAS AD0 LRB Read/Write R After reset 0 0 0 1 0 0 0 0 Function Master/ Slave status monitor Transmitter/ Receiver status monitor I C bus status monitor INTSBE1 interrupt request monitor Arbitration lost detection monitor 0: − 1: Detected Slave address match detection monitor Undetected 1: Detected GENERAL CALL detection monitor Undetected 1: Detected Last received bit monitor 0: “0” 1: “1” Last received bit monitor GENERAL CALL detection monitor Slave address match detection monitor Arbitration lost detection monitor 0 − INTSBE1 interrupt request monitor 0F r e e ( N o t e 2 ) 1B u s y Transmitter / receiver status monitor 0R e c e i v e r 1T r a n s m i t t e r Master / Slave status monitor 0S l a v e 1M a s t e r SBI2SR (017BH) Prohibit Read- modify-write Note1: Writing in this register functions as SBI2CR2. Note2: If SBI2SR<BB> drops down from 1 to 0 (falling edge), INTSBS2 will be generated in both case of Master mode and Slave mode. Figure 3.10.13 Registers for the I2C Bus Mode

Serial Bus Interface 2 Baud Rate Regster 0 7 6 5 4 3 2 1 0 Bit Symbol - I2SBI0 - - - - - - Read/Write W R/W After Reset 0 0 - - - - - - Function (Note) Fixed to “0” IDLE2 0: Stop 1: Run Operation during IDLE 2 Mode Serial Bus Interface 2 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4MON/ P4EN - - - - - - - Read/Write R/W After Reset 0 - - - - - - - Function Internal clock 0: Stop 1: Operate Baud rate clock control Sirial Bus Interface 2 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Read/Write R (received)/W (transfer) After Reset Undefined Note: When writing transmitted data, start from the MSB (bit 7). I2C Bus 2 Address Register 7 6 5 4 3 2 1 0 Bit Symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS Read/Write W After Reset 0 0 0 0 0 0 0 0 Function Slave address selection for when device is operating as slave device Addressing or free dat a format Address recognition mode specification (0184H) SBI2DBR (0181H) I2C2AR (0182H) Prohibit Read- modify-write Prohibit Read- modify-write SBI2BR1 (0185H) Prohibit Read- modify-write Addressing or free data format impact both slave and master configuration. When addressing format is used (<ALS>=0), TRX bit is updated relying on R/W bit (=8 th bit of first received byte after start condition). Moreover in slave mode, MCU spies the bus after start condition to recognize its address. When free data format is used (<ALS>=1) all words on the bus are considered as data words, that means no address recognition is done and TRX is not updated. Figure 3.10.14 Registers for the I2C Bus Mode

3.10.5 Control in I 2C Bus Mode

(1) Specifying acknowledge mode To operate the device in the acknowledge mode set the SBI0CR1<ACK> to “1”. When operating in the master mode this device generates an additional clock pulse as an acknowledge signal; when operating in the slave mode it counts a clock pulse as an acknowledge signal. In the transmitter mode the SDA0 pin is released during the clock pulse cycle so that it can receive the acknowledge signal from the receiver. In the receiver mode the SDA0 pin is set to the low-level during the clock pulse cycle in order to generate the acknowledge signal. To operate the device in non-acknowledge mode, clear the SBI0CR1<ACK> to “0”. When operating in the master mode this device does not generate a clock pulse as an acknowledge signal; when operating in the slave mode it does not count a clock pulse as an acknowledge signal. (2) Number of transfer bits The SBI0CR1<BC2 to 0> setting determines the number of data bits to be transmitted or received. Since the SBI0CR1<BC2 to 0> is cleared to “000” on start-up, a slave address and direction bit transmissions are executed in 8 bits. Other than these, the <BC2 to 0> retains a specified value. (3) Serial clock i) Clock source The SBI0CR1 <SCK3 to 0> is used to specify the maximum transfer frequency for output on the SCL0 pin in the master mode. Formula SBI0CR1 <SCK3 to 0> n tLOW = 2n-1 / fc tHIGH = 2n-1 / fc + 8 / fc fscl = 1 / (tLOW + tHIGH) = fc / (2n + 8) 0011 0100 0101 0110 tLOW = 32 / fc, tHIGH = 18 / fc fscl = fc / 50 1000 − tLOW = 100 / fc, tHIGH = 100 / fc fscl = fc / 200 1111 − Figure 3.10.15 Clock Source tHIGH tLOW 1/fscl

ii) Clock synchronization In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to the low-level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure. This device has a clock synchronization func tion which allows normal data transfer even when more than one master exists on the bus. The following example explains the clock synchronization procedures used when there are two masters present on the bus. Internal SCL0 output (Master A) Internal SCL0 output (Master B) SCL0 line Reset a counter of high-level width of a clock pulse Wait counting high-level width of a clock pulse Start couting high-level width of a clock pulse a b c Figure 3.10.16 Clock Synchronization When Master A pulls the internal SCL0 output to the low-level at point “a”, the SCL0 line of the bus goes to the low-level. After detecting this, Master B resets a counter of high-level width of an own clock pulse and sets the internal SCL0 output the low-level. Master A finishes counting low-level width of an own clock pulse at point “b” and sets the internal SCL0 output to the high-level. Since Master B is holding the SCL0 line of the bus at the low-level, Master A waits for counting high-level width of an own clock pulse. After Master B has finished counting low-level width of an own clock pulse at point “c” and Master A detects the SCL0 line of the bus at the high-level, and starts counting high-level of an own clock pulse. The clock pulse on the bus is determined by the master device with the shortest high-level width and the master device with the longest low-level width from among those master devices connected to the bus. (4) Slave address and address recognition mode specification When this device is to be used as an I2C slave device, set the slave address <SA6 to 0> and <ALS> in I2C0AR. Clear the <ALS> to “0” for addressing format. When this devices is to be used as an I2C master device, clear <ALS> to “0” for addressing format. When this device is tu be used in free data format system (as slave or master) set <ALS> to “1” for free data format. (5) Master/slave selection To operate this device as a master device set the SBI0CR2<MST> to “1”. To operate it as a slave device clear the SBI0CR2<MST> to “0”. The <MST> is cleared to “0” in hardware when a stop condition is detected on the bus or when arbitration is lost.

(8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 by transfer of the slave address or the data (INTSBE0) is generated, the SBI0SR<PIN> is cleared to “0”. The SCL0 line is pulled down to the low-level while the <PIN> = “0”. The <PIN> is cleared to “0” when a single word of data is transmitted or received. Either writing data to or reading data from SBI0DBR sets the <PIN> to “1”. The time from the <PIN> being set to “1” until the release of the SCL0 line is t LOW. In the address recognition mode (i.e. when <ALS> = “0”; Addressing format), the <PIN> is cleared to “0” when the slave address matches the value set in I2C0AR or when a GENERAL CALL is received (all 8-bit data are “0” after a start condition). Although the SBI0CR2<PIN> can be set to “1” by a program, writing “0” to the SBI0CR2<PIN> does not clear it to “0”. (9) Serial bus interface operation mode selection The SBI0CR2<SBIM1 to 0> is used to specify the serial bus interface operation mode. Set the SBI0CR2<SBIM1 to 0> to “10” when the device is to be used in I 2C Bus Mode. Switch to port mode confirming that the bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on the bus in I2C Bus Mode, a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data. Data on the SDA0 line is used for I 2C bus arbitration. The following example illustrates the bus arbitration procedure when there are two master devices on the bus. Master A and Master B output the same data until point “a”. After Master A outputs “L” and Master B, “H”, the SDA0 line of the bus is wire-AND and the SDA0 line is pulled down to the low level by Master A. When the SCL0 line of the bus is pulled up at point “b”, the slave device reads the data on the SDA0 line, that is, data in Master A. Data transmitted from Master B becomes invalid. The Master B state is known as “ARBITRATION LOST”. Master B device which loses arbitration releases the internal SDA0 output in order not to affect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word. Internal SDA0 output becomes “1” after arbitration has been lost. SCL0 line Internal SDA0 output (Master A) Internal SDA0 output (Master B) SDA0 line ab Figure 3.10.19 Arbitration Lost

This device compares the levels on the bus’s SDA0 line with those of the internal SDA0 output on the rising edge of the SCL0 line. If the levels do not match, arbitration is lost and the SBI0SR<AL> is set to “1”. When the <AL> is set to “1”, the SBI0SR<MST,TRX> are cleared to “00” and the mode is switched to a slave receiver mode. This device generates the clock pulse until data is transmitted when the <AL> is “1”. The <AL> is cleared to “0” when data is written to or read from SBI0DBR or when data is written to SBI0CR2. <AL> <MST> <TRX> Stop the clock pulse Keep Internal SDA0 output to high-level as losing arbitration Accessed to SBI0DBR or SBI0CR2 Internal SDA0 output Internal SCL0 output Master A Master B 2 3456789 1 2 3 4 D7A D6B D4A D3A D2A D1A D0A D7A’ D6A’ D5A’ D4A’ 1 2 3 D7B D6A Internal SDA0 output Internal SCL0 output D5A Figure 3.10.20 Example of a Master Device B (D7A = D7B, D6A = D6B) (11) Slave address match detection monitor The SBI0SR<AAS> is set to “1” in the slave mode, in the address recognition mode (i.e. when the I2C0AR<ALS> = “0”), when a GENERAL CALL is received, or when a slave address matches the value set in I2C0AR. When the I2C0AR<ALS> = “1”, the SBI0SR<AAS> is set to “1” after the first word of data has been received. The SBI0SR<AAS> is cleared to “0” when data is written to or read from the data buffer register SBI0DBR. (12) GENERAL CALL detection monitor The SBI0SR<AD0> is set to “1” in the slave mode, when a GENERAL CALL is received (all 8-bit received data is “0”, after a start condition). The SBI0SR<AD0> is cleared to “0” when a start condition or stop condition is detected on the bus. (13) Last received bit monitor The value on the SDA0 line detected on the rising edge of the SCL0 line is stored in the SBI0SR<LRB>. In the acknowledge mode, immediately after an INTSBE0 interrupt request has been generated, an acknowledge signal is read by reading the contents of the SBI0SR<LRB>.

(14) Software Reset function The software Reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal Reset signal pulse can be generated by setting SBI0CR2<SWRST1 to 0> to “10” and “01”. This initializes the SBI circuit internally. All control registers and status registers excluding SBI0CR2<SBIM1 to 0> are initialized as well. The SBI0CR2<SWRST1 to 0> is automatically cleared to “00” after the SBI circuit has been initialized. The initialization of SBI circuit can be confirmed by monitoring SBI0CR1<SWRMON>. (15) Serial Bus Interface Data Buffer Register (SBI0DBR) The received data can be read and the transferred data can be writtenby reading or writing the SBI0DBR. When the start condition has been generated in the master mode, the slave address and the direction bit are set in this register. (16) I 2C Bus Address Register (I2C0AR) I2C0AR<SA6 to 0> is used to set the slave address when this device functions as a slave device. ALS bit is used to select between addressing and free data format. - For I2C bus, addressing format is used (<ALS>=0) ; then TRX bit is updated relying on R/W bit (=8 th bit of first received byte after start condition). Moreover, in slave mode, MCU spies the bus after start condition to recognize its address - For free data format (ALS=1) all words on the bus are considered as data words, that means no address recognition is done and TRX is not updated (17) Baud Rate Register (SBI0BR1) Write “1” to the SBI0BR1<P4EN> before operation commences. (18) Setting register for IDLE2 mode operation (SBI0BR0) The setting of SBI0BR0<I2SBI0> determines whether the device is operating or is stopped in IDLE2 Mode. Therefore, setting <I2SBI0> is necessary before the HALT instruction is executed.

3.10.6 Data Transfer in I 2C Bus Mode

(1) Device Initialization Set the SBI0BR1<P4EN> and the SBI0CR1<ACK,SCK2 to 0>. Set the SBI0BR1<P4EN> to “1” and clear bits 7 to 5 and 3 of the SBI0CR1 to “0”. Set a slave address in I2C0AR<SA6 to 0> and the I2C0AR<ALS> (<ALS> = “0” when an addressing format.) For specifying the default setting to a slave receiver mode, clear “000” to the <MST, TRX, BB>, set “1” to the <PIN>, set “10” to the <SBIM1 to 0> and set “00” to the <SWRST1 to 0>. (2) Start Condition Generation and Slave Address Generation i) Master mode In the master mode the start condition and the slave address are generated as follows. Check a bus free status (when <BB>= ”0”). Set the SBI0CR1<ACK> to “1” (acknowledge mode) and specify a slave address and a direction bit to be transmitted to the SBI0DBR. When the <BB> is ”0”, the start condition is generated by writing “1111” to the SBI0CR2<MST,TRX,BB,PIN>. Subsequently to the start condition, nine clocks are output from the SCL0 pin. The slave address and the direction bit set to the SBI0DBR will be outputting during the 8 clocks. At the 9th clock pulse the SDA0 line is released and the acknowledge signal is received from the slave device. An INTSBE0 interrupt request occurs on the falling edge of the ninth clock pulse. The <PIN> is cleared to “0”. In the master mode the SCL0 pin is pulled down to the low-level while the <PIN> is “0”. When an INTSBE0 interrupt request occurs, the value of <TRX> is changed according to the direction bit setting only if the slave device returns an acknowledge signal. ii) Slave mode In the slave mode the start condition and the slave address are received. After the start condition has been received from the master device, while eight clocks are input from the SCL0 pin, the slave address and the direction bit which are output from the master device are received. When a GENERAL CALL or an address matching the slave address set in I2C0AR is received, the SDA0 line is pulled down to the low level at the 9th clock pulse and an acknowledge signal is output. An INTSBE0 interrupt request occurs on the falling edge of the ninth clock pulse. The <PIN> is cleared to “0”. In the slave mode the SCL0 line is pulled down to the low-level while the <PIN> = “0”. When an interrupt request occurs, the value of <TRX> is changed according to the direction bit setting only if the slave device returns an acknowledge signal. SCL0 Start condtion Slave address + derection bit Acknowledge signal from a slave device SDA0 2 345678 9 A5 A4 A3 A2 A1 A0 WR/ <PIN> INTSBE0 interrupt request ACK output of Master output of Slave Figure 3.10.21 Start Condition Generation and Slave Address Transfer

(3) 1-word Data Transfer Check the <MST> setting using an INTSBE0 interrupt process after the transfer of each word of data is completed and determine whether the device is in the master mode or the slave mode. i) When the <MST> is “1” (Master mode) Check the <TRX> setting and determine whether the device is in the transmitter mode or the receiver mode. Note: TRX bit is only valid in addressing format (<ALS>=0). When the <TRX> is “1” (Transmitter mode) Check the <LRB> setting. When the <LRB> = “1”, there is no receiver requesting data. Implement the process for generating a stop condition (see Section 3.10.6 (4) ) and terminate data transfer. When the <LRB> = “0”, the receiver is requesting new data. When the next transmitted data is 8 bits, write the transmitted data to the SBI0DBR. When the next transmitted data is other than 8 bits, set the <BC2 to 0>, set the <ACK> to “1” and write the transmitted data to the SBI0DBR. After the data has been written, the <PIN> is set to “1”, a serial clock pulse is generated to trigger transfer of the next word of data via the SCL0 pin, and the word is transmitted. After the data has been transmitted, an INTSBE0 interrupt request is generated. The <PIN> is set to “0” and the SCL0 line is pulled down to the low-level. If the length of the data to be transferred is greater than one word, repeat the latter steps of the procedure, starting from the check of the <LRB> setting. SCL0 line Acknowledge signal from a receive SDA0 line 2 3 456789 D6 D5 D4 D3 D2 D1 <PIN> INTSBE0 interrupt request ACK Output from Master Output from Slave Write to SBI0DBR Figure 3.10.22 Example in which <BC2 to 0> = “000” and <ACK> = “1” in Transmitter Mode

ii) When the <MST> is “0” (Slave mode) In the slave mode, this device operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBE0 interrupt request occurs when this device receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or after matching a received slave address. In the master mode, this device operates in a slave mode if it is losing arbitration. An INTSBE0 interrupt request occurs when word data transfer terminates after losing arbitration. When an INTSBE0 interrupt request occurs, the <PIN> is cleared to “0”, and the SCL0 pin is pulled down to the low-level. Either reading data to or writing data from the SBI0DBR, or setting the <PIN> to “1” releases the SCL0 pin after taking t LOW time . If the stop condetion is detected and SBI0SR<BB> drops down from 1 to 0, INTSBS0 will be generated. Check the SBI0SR<AL>, <TRX>, <AAS> and <AD0> and implements processes according to conditions listed in the next table. Note: The <PIN> is set to "0" and the SCL0 pin is pulled down to the low-level, when this device as a master loses arbitration while sending slave address and is called as the slave. In the following 2 cases, the interrupt request is generated when data transfer is finished after losing arbitration, but <PIN> is not set to "0". - The case that this device as a master loses arbitration while sending slave address and the slave address sent from another device does not correspond to this device. - The case that this device as a master loses arbitration while sending the data.

Table 3.10.1 Operation in the Slave Mode <TRX> <AL> <AAS> <AD0> Conditions Process 1 1 0 This device loses arbitration when transmitting a slave address and receives a slave address of which the value of the direction bit sent from another master is “1”. 1 0 In the salve receiver Mode, this device receives a slave address of which the value of the direction bit sent from the master is “1”. Set the number of bits in 1-word to the <BC2 to 0> and write the transmitted data to the SBI0DBR. 0 0 In the salve transmitter mode, 1-word data is transmitted. Check the <LRB>. If the <LRB> is set to “1”, set the <PIN> to “1” since the receiver does not request the next data. Then, clear the <TRX> to “0” to release the bus. If the <LRB> is cleared to “0”, set the number of bits in a word to the <BC2 to 0> and write transmitted data to the SBI0DBR since the receiver requests next data. 1 1/0 This device loses arbitration when transmitting a slave address and receives a GENERAL CALL or slave address of which the value of the direction bit sent from another master is “0”. Read the SBI0DBR for setting the <PIN> to “1” (reading dummy data) or set the <PIN> to “1”. 0 0 This device loses arbitration when transmitting a slave address or data and terminates transferring word data. Although INTSEBE0 interrupt occurs after finishing transmitting, this device is slave receiver mode. In this case the <PIN> is not cleared to '0'. Execute the program again in the case of transmitting again as a master. 1 1/0 In the slave receiver mode, this device receives a GENERAL CALL or slave address of which the value of the direction bit sent from the master is “0”. Read the SBI0DBR for setting the <PIN> to “1” (reading dummy data) or set the <PIN> to “1”. 0 1/0 In the slave receiver mode, the device terminates receiving 1-word data. Set the number of bits in a word to the <BC2 to 0> and read received data from the SBI0DBR.

(4) Stop condition generation When the SBI0SR<BB> is “1”, the sequence of generating a stop condition is started by setting “111” to the SBI0CR2<MST,TRX,PIN> and “0” to the SBI0CR2<BB>. Do not modify the contents of the SBI0CR2<MST,TRX,PIN,BB> until a stop condition is generated on a bus. When a SCL0 line of bus is pulled down by other devices, this device generates a stop condition after they release a SCL0 line and the SDA0 becomes “1”. An INTSBS0 interrupt request occurs at the timing of the SBI0SR<BB> becomes “0” in both case of master mode and slave mode.. Whenever a stop condition is detected, an INTSBS0 interrupt request will be generated in both case of master mode and slave mode, regardless of whether it means to stop data transfer or not. SCL0 line SDA0 line <PIN> <BB> (Read) Stop condition 1 → <MST> 1 → <TRX> 0 → <BB> 1 → <PIN> INTSBS0 interrupt request Figure 3.10.25 Stop Condition Generation

(5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when this device is in the master mode. Clear the SBI0CR2<MST,TRX,BB> to “000” and set the SBI0CR2<PIN> to “1” to release the bus. The SDA0 line remains the high-level and the SCL0 pin is released. Since a stop condition is not generated on the bus, other devices assume the bus to be in a busy state. Check the SBI0SR<BB> until it becomes “0” to check that the SCL0 pin of this device is released. Check the <LRB> until it becomes 1 to check that the SCL0 line on a bus is not pulled down to the low-level by other devices. After confirming that the bus stays in a free state, generate a start condition with procedure described in 3.10.6 (2). In order to meet set-up time when restarting, take at least 4.7 us of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition. 0 → <MST> 0 → <TRX> 0 → <BB> 1 → <PIN> 1 → <MST> 1 → <TRX> 1 → <BB> 1 → <PIN> SCL0 line Internal SCL0 output SDA0 line <LRB> Fast : 600ns Standard: 4.7 µs Start codnition <BB> <PIN> Figure 3.10.26 Timing Diagram when Restarting

3.10.7 Clocked Synchronous 8-Bit SIO Mode control

The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked synchronous 8-bit SIO mode. Serial Bus Interface 0 Control Register 1 7 6 5 4 3 2 1 0 Bit symbol SIOS SIOINH SIOM1 SIOM0 - SCK2 SCK1 SCK0 Read/Write W W W After Reset 0 0 0 0 1 0 0 0 Function Transfer start 0: stop 1: start Continue/ abort transfer 0: Continue transfer 1: Abort transfer Transfer mode select 00: Transmit Mode 01: (reserved) 10: Transmit/Receive Mode 11: Receive Mode Note2) Write 0 to this bit. Serial clock selection Serial clock selection <SCK2 to 0> @ write 000 001 010 011 100 101 110 111 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 n = 10

1.25 MHz

78.1 kHz 39.1 kHz 19.5 kHz external clock : CPU clcok: fc fc = 20 MHz (output to SCK pin) fscl = [Hz] Software reset state monitor <SWRMON> @ read

1 Not during software reset

01 (reserved) 10 8-bit transmit / receive mode 11 8-bit receive mode Continue / abort transfer

0 Continue transfer

1 Abort transfer (automatically cleared after transfer

aborted) Indicate transfer start / stop 0S t o p 1S t a r t Serial Bus interface 0 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Read/Write R (receiver) / W (transfer) After Reset Undefined SBI0CR1 (0170H) Note1: Set the tranfer mode and the serial clock after setting <SIOS> to “0” and <SIOINH> to “1”. Note2: Write 0 to this bit in SIO mode. Prohibit Read- modify-write SBI0DBR (0171H) Prohibit Read- modify-write fc SCK0 Figure 3.10.27 Register for the SIO Mode

Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol - - - - SBIM1 SBIM0 - - Read/Write W W W After Reset - - - - 0 0 0 0 Function Serial bus interface operation mode selection 00: Port mode 01: SIO mode 10: I 2C bus mode 11: (reserved) (Note2) (Note2) Serial bus interface operation mode selection

01 Clocked-Synchronous 8-bit SIO mode

11 (reserved) Note1: Set the SBI0CR1<BC2 to 0> “000” before switching to a clocked-synchronous 8-bit SIO mode. Note2: Please always write “00” to SBI0CR2<1:0>. Serial Bus Interface 0 Status Register 7 6 5 4 3 2 1 0 bit Symbol - - - - SIOF SEF - - Read/Write R After reset - - - - 0 0 - - Function Serial transfer operation status monitor Shift operation status monitor Shift operation status monitor

0 Shift operation terminated

1 Shift operation in progress

Serial transfer operating status monitor

0 Transfer terminated

1 Transfer in progress

(0173H) SBI0SR (0173H) Prohibit Read- modify-write Figure 3.10.28 Registers for the SIO Mode

Serial B us Interface 0 Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol - I2SBI0 - - - - - - Read/Write W R/W After Reset 0 0 - - - - - - Function (Note) Fixed to “0” IDLE2 0: STOP 1: RUN Operation during IDLE 2 mode Serial Bus Interface 0 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4MON/ P4EN - - - - - - - Read/Write R/W After Reset 0 - - - - - - - Function Internal clock 0: Stop 1: Operate Baud rate clock control (0174H) SBI0BR1 (0175H) Prohibit Read- modify-write Figure 3.10.29 Registers for the SIO Mode

Serial Bus Interface 1 Control Register 1 7 6 5 4 3 2 1 0 Bit symbol SIOS SIOINH SIOM1 SIOM0 - SCK2 SCK1 SCK0 Read/Write W W W After Reset 0 0 0 0 1 0 0 0 Function Transfer start 0: stop 1: start Continue/ abort transfer 0: Continue transfer 1: Abort transfer Transfer mode select 00: Transmit Mode 01: (reserved) 10: Transmit/Receive Mode 11: Receive Mode Note2) Write 0 to this bit. Serial clock selection Serial clock selection <SCK2 to 0> @ write 000 001 010 011 100 101 110 111 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 n = 10 78.1 kHz 39.1 kHz 19.5 kHz external clock : CPU clcok: fc fc = 20 MHz (output to SCK pin) fscl = [Hz] Software reset state monitor <SWRMON> @ read 01 (reserved) 10 8-bit transmit / receive mode 11 8-bit receive mode Continue / abort transfer aborted) Indicate transfer start / stop 0S t o p 1S t a r t Serial Bus interface 1 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Read/Write R (receiver) / W (transfer) After Reset Undefined Note1: Set the tranfer mode and the serial clock after setting <SIOS> to “0” and <SIOINH> to “1”. Note2: Write 0 to this bit in SIO mode. SBI1DBR (0179H) Prohibit Read- modify-write fc SCK1 SBI1CR1 (0178H) Prohibit Read- modify-write Figure 3.10.30 Register for the SIO Mode

Serial Bus Interface 1 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol - - - - SBIM1 SBIM0 - - Read/Write W W W After Reset - - - - 0 0 0 0 Function Serial bus interface operation mode selection 00: Port mode 01: SIO mode 10: I 2C bus mode 11: (reserved) (Note2) (Note2) Serial bus interface operation mode selection 11 (reserved) Note1: Set the SBI1CR1<BC2 to 0> “000” before switching to a clocked-synchronous 8-bit SIO mode. Note2: Please always write “00” to SBI1CR2<1:0>. Serial Bus Interface 1 Status Register 7 6 5 4 3 2 1 0 bit Symbol - - - - SIOF SEF - - Read/Write R After reset - - - - 0 0 - - Function Serial transfer operation status monitor Shift operation status monitor Shift operation status monitor Serial transfer operating status monitor (017BH) SBI1SR (017BH) Prohibit Read- modify-write Figure 3.10.31 Registers for the SIO Mode

Serial Bus Interface 1 Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol - I2SBI1 - - - - - - Read/Write W R/W After Reset 0 0 - - - - - - Function (Note) Fixed to “0” IDLE2 0: STOP 1: RUN Operation during IDLE 2 mode Serial Bus Interface 1 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4MON/ P4EN - - - - - - - Read/Write R/W After Reset 0 - - - - - - - Function Internal clock 0: Stop 1: Operate Baud rate clock control (017CH) SBI1BR1 (017DH) Prohibit Read- modify-write Figure 3.10.32 Registers for the SIO Mode

Serial Bus Interface 2 Control Register 1 7 6 5 4 3 2 1 0 Bit symbol SIOS SIOINH SIOM1 SIOM0 - SCK2 SCK1 SCK0 Read/Write W W W After Reset 0 0 0 0 1 0 0 0 Function Transfer start 0: stop 1: start Continue/ abort transfer 0: Continue transfer 1: Abort transfer Transfer mode select 00: Transmit Mode 01: (reserved) 10: Transmit/Receive Mode 11: Receive Mode Note2) Write 0 to this bit. Serial clock selection Serial clock selection <SCK2 to 0> @ write 000 001 010 011 100 101 110 111 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 n = 10 78.1 kHz 39.1 kHz 19.5 kHz external clock : CPU clcok: fc fc = 20 MHz (output to SCK pin) fscl = [Hz] Software reset state monitor <SWRMON> @ read 01 (reserved) 10 8-bit transmit / receive mode 11 8-bit receive mode Continue / abort transfer aborted) Indicate transfer start / stop 0S t o p 1S t a r t Serial Bus interface 2 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Read/Write R (receiver) / W (transfer) After Reset Undefined Note1: Set the tranfer mode and the serial clock after setting <SIOS> to “0” and <SIOINH> to “1”. Note2: Write 0 to this bit in SIO mode. SBI2DBR (0181H) Prohibit Read- modify-write fc SCK2 SBI2CR1 (0180H) Prohibit Read- modify-write Figure 3.10.33 Register for the SIO Mode

Serial Bus Interface 2 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol - - - - SBIM1 SBIM0 - - Read/Write W W W After Reset - - - - 0 0 0 0 Function Serial bus interface operation mode selection 00: Port mode 01: SIO mode 10: I 2C bus mode 11: (reserved) (Note2) (Note2) Serial bus interface operation mode selection 11 (reserved) Note1: Set the SBI2CR1<BC2 to 0> “000” before switching to a clocked-synchronous 8-bit SIO mode. Note2: Please always write “00” to SBI2CR2<1:0>. Serial Bus Interface 2 Status Register 7 6 5 4 3 2 1 0 bit Symbol - - - - SIOF SEF - - Read/Write R After reset - - - 0 0 - Function Serial transfer operation status monitor Shift operation status monitor Shift operation status monitor Serial transfer operating status monitor (0183H) SBI2SR (0183H) Prohibit Read- modify-write Figure 3.10.34 Registers for the SIO Mode

Serial Bus Interface 2 Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol - I2SBI1 - - - - - - Read/Write W R/W After Reset 0 0 - - - - - - Function (Note) Fixed to “0” IDLE2 0: STOP 1: RUN Operation during IDLE 2 mode Serial Bus Interface 2 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4MON/ P4EN - - - - - - - Read/Write R/W After Reset 0 - - - - - - - Function Internal clock 0: Stop 1: Operate Baud rate clock control (0184H) SBI2BR1 (0185H) Prohibit Read- modify-write Figure 3.10.35 Registers for the SIO Mode

ii) Shift edge Data is transmitted on the falling edge of the clock and received on the rising edge. Falling edge shift Data is shifted on the falling edge of the serial clock (on the falling edge of the SCK0 pin input/output). Rising edge shift Data is shifted on the rising edge of the serial clock (on the rising edge of the SCK0 pin input/output). bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SO0 pin output SCK0 pin output Shift register SCK0 pin SI0 pin Shift register (a) Falling edge shift (b) Rising edge shift Note: * = Don’t care bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Figure 3.10.38 Shift Edge

(2) Transfer Modes The SBI0CR1<SIOM1 to 0> is used to select a transmit, receive or transmit/receive mode. i) 8-bit transmit mode Set a control register to a transmit mode and write transmission data to the SBI0DBR. After the transmit data has been written, set the SBI0CR1<SIOS> to “1” to start data transfer. The transmitted data is transferred from the SBI0DBR to the shift register and output, starting with the least significant bit (LSB), via the SO0 pin and synchronized with the serial clock. When the transmission data has been transferred to the shift register, the SBI0DBR becomes empty. The INTSBE0 (buffer empty) interrupt request is generated to request new data. When the internal clock is used, the serial clock will stop and the automatic wait function will be initiated if new data is not loaded to the data buffer register after the specified 8-bit data is transmitted. When new transmission data is written, the automatic wait function is canceled. When the external clock is used, data should be written to the SBI0DBR before new data is shifted. The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the SBI0DBR by the interrupt service program. When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the SO0 pin holds final bit of the last data until falling edge of the SCK0. Data transmission ends when the <SIOS> is cleared to “0” by the INTSBE0 interrupt service program or when the <SIOINH> is set to “1”. When the <SIOS> is cleared to “0”, the transmitted mode ends when all data is output. In order to confirm whether data is being transmitted properly by the program, the <SIOF> (bit 3 of the SBI0SR) to be sensed. The SBI0SR<SIOF> is cleared to “0” when transmission has been completed. When the <SIOINH> is set to “1”, transmitting datat stops. The <SIOF> turns “0”. When the external clock is used, it is also necessary to clear the <SIOS> to “0” before new data is shifted; otherwise, dummy data is transmitted and operation ends.

<SIOS> <SIOF> <SEF> SCK0 pin (output) SO0 pin b a0 a 1 a 2 a 3 a 4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b 6 b 7 * Clear<SIOS> a Write transmitted data (a) Internal clock SBI0DBR INTSBE0 interrupt request <SIOS> <SIOF> <SEF> SCK0 pin (input) SO0 pin b a0 a 1 a 2 a 3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b 6 b 7 * Clear <SIOS> a Write transmitted data (b) External clock Figure 3.10.39 Transfer Mode Example: Program to stop data transmission (when an external clock is used) STEST1: BIT 2, (SBI0SR) ; If <SEF> = 1 then loop JR NZ, STEST1 STEST2: BIT 0, (PN) ; If SCK0 = 0 then loop JR Z, STEST2 LD (SBI0CR1), 00000111B ; <SIOS> ← 0

<SIOF> SO0 pin bit 6 tSODH = Min. 3.5/fC [s] Figure 3.10.40 Transmitted Data Hold Time at End of Transmission ii) 8-bit receive mode Set the control register to receive mode and set the SBI0CR1<SIOS> to “1” for switching to receive mode. Data is received into the shift register via the SI0 pin and synchronized with the serial clock, starting from the least significant bit (LSB). When the 8-bit data is received, the data is transferred from the shift register to the SBI0DBR. The INTSBE0 (buffer full) interrupt request is generated to request that the received data be read. The data is then read from the SBI0DBR by the interrupt service program. When the internal clock is used, the serial clock will stop and the automatic wait function will be in effect until the received data is read from the SBI0DBR. When the external clock is used, since shift operation is synchronized with an external clock pulse, the received data should be read from the SBI0DBR before the next serial clock pulse is input. If the received data is not read, further data to be received is canceled. The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when the received data is read. Receiving of data ends when the <SIOS> is cleared to “0” by the INTSBE0 interrupt service program or when the <SIOINH> is set to “1”. If <SIOS> is cleared to “0”, received data is transferred to the SBI0DBR in complete blocks. The received mode ends when the transfer is complete. In order to confirm whether data is being received properly by the program, the SBI0SR<SIOF> to be sensed. The <SIOF> is cleared to “0” when receiving is complete. When it is confirmed that receiving has been completed, the last data is read. When the <SIOINH> is set to “1”, data receiving stops. The <SIOF> is cleared to “0” (the received data becomes invalid, therefore no need to read it). Note: The transfer mode needs to be changed, after reading the last received data with instruction to finish data receiving by clearing the <SIOS> to "0".

<SIOS> <SIOF> <SEF> SCK0 pin (output) SI0 pin b Clear <SIOS> a a0 a 1 a 2 a 3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b 6 b 7 Read receiver data Read receiver data Figure 3.10.41 Receiver Mode (example: Internal clock) iii) 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBI0DBR. After the data is written, set the SBI0CR<SIOS> to “1” to start transmitting/receiving. When data is transmitted, the data is output from the SO0 pin, starting from the least significant bit (LSB) and synchronized with the falling edge of the serial clock signal. When data is received, the data is input via the SI0 pin on the rising edge of the serial clock signal. 8-bit data is transferred from the shift register to the SBI0DBR and the INTSBE0 interrupt request is generated. The interrupt service program reads the received data from the data buffer register and writes the data which is to be transmitted. The SBI0DBR is used for both transmitting and receiving. Transmitted data should always be written after received data is read. When the internal clock is used, the automatic wait function will be in effect until the received data is read and the next data is written. When the external clock is used, since the shift operation is synchronized with the external clock, the received data is read and transmitted data is written before a new shift operation is executed. The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time at which received data is read and transmitted data is written. When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the SO0 pin holds final bit of the last data until falling edge of the SCK0. Transmitting/receiving data ends when the <SIOS> is cleared to “0” by the INTSBE0 interrupt service program or when the SBI0CR1<SIOINH> is set to “1”. When the <SIOS> is cleared to “0”, received data is transferred to the SBI0DBR in complete blocks. The transmit/receive mode ends when the transfer is complete. In order to confirm whether data is being transmitted/received properly by the program, set the SBI0SR to be sensed. The <SIOF> is set to “0” when transmitting/receiving is completed. When the <SIOINH> is set to “1”, data transmitting/receiving stops. The <SIOF> is then cleared to “0”. Note: When the transfer mode is changed, the contents of the SBI0DBR will be lost. If the mode must be changed, conclude data transmitting/receiving by clearing the <SIOS> to “0”, read the last data, then change the transfer mode.

3.11 Serial Expansion Interface (SEI)

3.11.1 Overview

The SEI is one of the serial in terfaces built in the TMP92CD54I, which can be connected to peripheral devices, by full duplex synchronous communication protocol. TMP92CD54I incorporates 1 channel of this SEI. Also the SEI can support the micro DMA mode corresponds to the micro DMA transfer. (1) Features z The master outputs the shift clock only during data transfer. z The clock polarity and phase are programmable z The data is 8 bits long z The MSB first or LSB first can be selected z Micro DMA mode support for micro DMA transfers z Transfer rate: 4Mbps, 2Mbps or 500kbps (when operating at fc = 20MHz) z Error detection function ① Write collision detection: when write to the shift register during the data transfer ② Overflow detection: when receive the new data with the transfer end flag is set (only slave) ③ Mode fault detection: when the input to the SS pin goes L in Master mode (driver output immediately turns off) Figure 3.11.1 SEI Block Diagram SEI Control Unit Port Control Unit Shift Register Read Buffer Clock Control Unit SEI Data Register Clock Selector Bit Order MUX SEI Control Register SEI Status Register MISO Internal SEI Clock D<7:0> SEE MODE MSTR CPHA CPOL BOS SER1:0 TMSE TASM SEF TSRC TSTC MODF WCOL SOVF MOSI SECLK SS A<1:0> SEICS Clock Divider ÷2 ÷4 ÷16 INTSEM INTSEE INTSER INTSET

Table 3.11.1 Pin Function of SEI Channels SEI SS (PM0) MOSI (PM1) MISO (PM2) SECLK (PM3)

3.11.2 SEI operation

During a SEI transfer, data is simultaneously transmitted (shifted out serially) and received serially (shifted in serially). In order to shift or sample the information on two serial data lines (MOSI/MISO), SEI clock (SECLK) takes the synchronization. Slave selection line ( SS ) individually selects the slave device. The slave device not selected cannot use the SEI bus. Because the master function is turned off in the master device when the multi master bus is connected, slave selection line ( SS ) can be used. (1) SEI clock phase and polarity controls Software can select any four combinations of serial clock phase and polarity using two bits in the SEI control register (SECR). The clock polarity is set by < CPOL > bit, and selects the clock of active "H" or active "L". The clock phase <CPHA> cont rol bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SEI device and the communicating slave device. (2) SEI data and clock timing The programmable clock timing and data of SEI can connect almost all devices around synchronous serial. Please see “3.11.4 SEI transfer format” for a detailed description of the transfer format.

3.11.3 SEI signal lines

There are four input/output pin signals associated with the SEI transfer. Every signal depends on the mode (master/slave) of the SEI device. (1) SECLK The SECLK pin functions as an output pin when the SEI is set for master and functions as an input pin when the SEI is set for slave. When the SEI is set for master, the SECLK signal is supplied by the internal SEI clock generation circuit. When the master starts transferring data, eight cycles clock are automatically output at the SECLK pin. When the SEI is set for slave, the SECLK pin functions as an input pin, in which case the SECLK signal from the master synchronizes data transfers between the master and slave. The slave device ignores the SECLK signal if the slave select SS pin is high. In both master and slave SEI devices, data is shifted in or out at each rising or falling edge of the SECLK signal and is sampled at the opposite edge. Edge polarity is determined by the SEI transfer protocol. (2) MISO/MOSI The MISO and MOSI pins are used for transmitting and receiving serial data. When the SEI is configured as a master, MISO is the data input line and MOSI is the data output line. When the SEI is configured as a slave, these pins reverse roles. In a multiple-master system, all SECLK pins are tied together, all MOSI pins are tied together and all MISO pins are tied together. Refer to Figure 3.11.5. A single SEI device is configured as a master, all other SEI devices on the SEI bus are configured as slaves. The single master drives the transfer clock and data out it’s SECLK and MOSI pins to the SECLK and MOSI pins of the slaves. One selected slave device optionally drives data out it’s MISO pin to the MISO master pin. The SECLK, MISO and MOSI pins can be set to function as open-drain pins. (3) SS The SS pin behaves differently on master and slave devices. On a slave device, this pin is used to enable the SEI slave for transfer and receive. If the SS pin of a slave is inactive (high), the device ignores SECLK clocks and keeps the MISO output pin in the high-impedance state. On a master device, the SS pin serves as an error-detection input for the SEI. If the SS pins go low while the SEI is a master, it indicates that some other device on the SEI bus is attempting to be master. This attempt causes the master device sensing the error to immediately exit the SEI bus to avoid potentially damaging driver contentions. This error is called mode fault. Set whether to permit the mode fault detection by < MODE > bit of the SECR register or to prohibit it. When the <MODE> bit = 0, the SS pin is enabled for mode fault detection input. When the <MODE> bit = 1, the SS pin is disabled from mode fault detection input.

3.11.4 SEI transfer format

The transfer format is decided the setting of the <CPHA> bit and <CPOL> bit in the SECR register. <CPHA> bit switches between two different transfer protocols. (1) Transfer Format of <CPHA>=0 Figure 3.11.2 shows the transfer format for a <CPHA>=0 transfer. SECLK cycle 1 2 3 4 5 6 7 8 S E C L K ( < C P O L > = 0 ) S E C L K ( < C P O L > = 1 ) Internal shift clock MOSI MISO SS <SEF>(compatibility mode) < T S R C > ( m i c r o D M A m o d e ) < T S T C > ( m i c r o D M A m o d e & m a s t e r ) < T S T C > ( m i c r o D M A m o d e & S l a v e ) Figure 3.11.2 Transfer Format of <CPHA>=0 <CPHA>=0 No communication (idle) SECLK level Data shift Data sampling <CPOL>=0 L Shift clock falling edge Shift clock rising edge <CPOL>=1 H Shift clock rising edge Shift clock falling edge In master mode, writing new data to the SEDR register starts the transfer. The new data are switched on the MOSI pin half a clock before the shift clock starts the operation. SECR<BOS> selects whether the data are shifted out from the MSB or from the LSB. After the final shift cycle, the <SEF> flag is set to 1 if Compatibility mode is selected, and the <TSRC> and <TSTC> flags are set to 1 if Micro DMA mode is selected. In slave mode, writing to the SEDR register is prohibited while the SS pin is L. Attempting a write during this period triggers a write collision and sets the SESR register’s <WCOL> flag to 1. This terminates the transfer. At this time the software must wait until the SS pin goes H again before writing the next data to the SEDR register, even if the <SEF> or <TSRC> flag is set to 1. When using micro DMA for transferring data to the SEDR register in slave mode, the setting of the <TSTC> flag is delayed until the SS pin goes H.

3.11.5 Functional description

Figure 3.11.4 shows master-to-slave connection via the SEI. The different nodes on a SEI bus function like a dist ributed shift register. When data is sent from the MOSI pin of the master device to the corresponding pin of the slave device, data from the slave is sent back from the MISO pin of the slave device to the corresponding pin of the master device. This means that data is communicated in full-duplex mode and data output and data input are synchronized by the same clock signal. After a transfer, the transmission data of eight bit shift register is replaced with receive data. Master Slave 8-bit shift register 8-bit shift register MISO MISO SEI clock generator SECLK SECLK 5V 0V Figure 3.11.4 Connection between Master and Slave in SEI Figure 3.11.5 shows a configuration of the SEI system. The port used as the output of SEI, can be set for open -drain output programmable. Therefore, this port can be connected to multiple devices. Master Slave 0 Slave 1 PORTn PORTn’ SS SECLK MOSI MISO SS SECLK MOSI MISO SS SECLK MOSI MISO PORTn, n’: any output ports Figure 3.11.5 Configuration of SEI System (Comprised of One Master and Two Slaves) VCC MOSIMOSI SS SS

3.11.6 Operation Modes

SEI allows the programmer the choice between 2 different operation modes, the compatibility mode and the micro DMA mode. Those operation modes differ in terms of flag clearing, interrupt generation and use propriety of micro DMA. The table below shows the differences between the two operation modes. Table 3.11.2 Differences between the Two Operation Modes compatibility mode micro DMA mode error flag clearing Reading a register with the Status flag set, followed by SECR register or SEDR register access Writing a “1” to the status register transfer status flag clearing Reading a register with the Status flag set, followed by an access to the data register Writing a “1” to the status register or by reading or writing the data register interrupt generation INTSEM: <MODF> INTSEE: <SEF> INTSEM: <MODF> INTSEE: <WCOL> or <SOVF> INTSER: <TSRC> INTSET: <TSTC> micro DMA usage No yes SEI can be switched between these operation modes, if SEI is disabled (<SEE> = 0) by setting the <TMSE> bit in the SESR register.

3.11.7 SEI registers

Use SEI control register SECR, SEI status register SESR, and SEI data register SEDR to set SEI. (1) SEI control register (SECR) SEI Control Register 7 6 5 4 3 2 1 0 SECR bit Symbol MODE SEE BOS MSTR CPOL CPHA SER1 SER0 (0060H) Read/Write W R/W After reset 0 0 0 0 0 1 1 1 Read-modify -write instructions prohibited. Function Mode fault detection 0:enabled 1:disabled SEI operation 0:stopped 1:operating Bit order selection 0:MSB first 1:LSB first Mode selection 0:slave 1:master Clock polarity selection see figure 3.11.2, 3.11.3 Clock Phase selection see figure 3.11.2, 3.11.3 SEI transfer rate selection 00: Reserved 01: divide-by- 2 10: divide-by- 4 11: divide-by-16 <MODE>: Mode fault detection enable 0: Mode fault detection enabled. 1: Mode fault detection disabled. Only the master mode is effective and invalid at the slave mode. <SEE>: SEI function enable 0: SEI function is off. It is necessary to disable the SEI function to switch between the micro DMA mode and the compatibility mode. Wait until the transfer in progress is completed before you clear the <SEE> bit to stop the SEI operation. Clear <SEE> to 0 before executing HALT instruction in IDLE1, IDLE3 or STOP mode. 1: SEI function is on. Before using the SEI, make sure that the port function needs to be set as SEI function. <BOS>: Bit order select The bit order selection bit <BOS> selects whether the data to be transferred is MSB first or LSB first. 0: The MSB bit of the SEDR register (bit 7) will be transmitted first. 1: The LSB bit of the SEDR register (bit 0) will be transmitted first. <MSTR>: Master/Slave mode select 0: SEI is configured as slave. 1: SEI is configured as master. <CPOL>: Clock polarity select 0: Select the clock of active "H". The SECLK clock is "L" level at non-communication state. 1: Select the clock of active "L". The SECLK clock is "H" level at non-communication state. <CPHA>: Clock phase select <CPHA> bit selects one of two, different transfer format. <SER1:0>: SEI bit rate select The following table shows the relationship between the <SER1> and <SER0> control bits and the bit rate for transfers when the TSEI is operating as a master. When the TSEI is operating as a slave, the serial clock is input from the master, therefore, the <SER1> and <SER0> control bits have no meaning.

Table 3.11.3 SEI transfer bit rate <SER1> <SER0> Divide-by-rate of internal SEI clock Transfer rate (@ fc = 20 MHz) 0 0 Don’t use this setting. 0 1 2 4 Mbps 1 0 4 2 Mbps 1 1 16 500 Kbps Note: internal SEI clock = 2/5×fc (2) SEI status register (SESR) SEI Status Register 7 6 5 4 3 2 1 0 SESR bit Symbol SEF WCOL SOVF MODF - - - TMSE (0061H) Read/Write R R/W After reset 0 0 0 0 - - - 0 compati- bility mode Function SEI transfer complete flag 1:transfer completed Write collision flag 1:write collided Overflow flag (slave) 1:overflow occurred Mode fault flag (master) 1:fault occurred SEI mode select 0:compati- bility mode 1:micro DMA mode SEI Status Register 7 6 5 4 3 2 1 0 SESR bit Symbol - WCOL SOVF MODF TSRC TSTC TASM TMSE (0061H) Read/Write R R/W After reset - 0 0 0 0 0 0 0 micro DMA mode Read- modify-write instructions prohibited. Function Write collision flag 1:write collided Overflow flag (slave) 1:overflow occurred Mode fault flag (master) 1:fault occurred SEI receive complete flag 1:receive completed SEI transmit complete flag 1:transmit completed SEI automated shift mode (master) interrupt mask (slave) SEI mode select 0:compati- bility mode 1:micro DMA mode <SEF>: Transfer complete flag Compatibility mode: The <SEF> flag is automatically set to one at the end of a SEI transfer. The <SEF> flag is automatically cleared to 0 by reading the SESR register with <SEF> flag set to 1, followed by an access of the SEDR register. Micro DMA mode: Always reads as undefined, writes to this flag have no effect. <WCOL>: Write collision error flag Compatibility mode: The <WCOL> flag is automatically set to 1, if the SEDR register is written while a transfer is in progress. The write itself has no effect on the running transmission. The <WCOL> flag is automatically cleared to 0 by reading the SESR register with <WCOL> bit set followed by an access to the SEDR register. No interrupt will be generated on the assertion of this flag. Micro DMA mode: The <WCOL> flag is automatically set to 1, if the SEDR register is written while a transfer is in progress. The write itself has no effect on the running transmission. The flag can only be reset by writing a “1” to it. Writing a “0” has no effect. An interrupt will be generated on INTSEE on a transition from “0” to “1”, if the module is configured as a slave and the <TASM> bit is equal to “0”.

<SOVF>: Slave mode overflow error flag Master mode: Always reads as undefined, writes to this flag have no effect. Slave mode: Compatibility mode: The <SOVF> flag is automatically set to 1, if a new byte has been completely received and the <SEF> flag is still set to 1. The <SOVF> flag is automatically cleared to 0 by reading the SESR register with the <SOVF> flag is set to 1 followed by an access to the SEDR register. The <SOVF> flag will also be cleared to 0 by switch to the master mode. In compatibility mode, no interrupt will be generated on the setting of <SOVF> flag. Micro DMA mode: The <SOVF> flag is automatically set to 1, if a new byte has been completely received and the <TSRC> flag is still set to 1. The <SOVF> flag can only be cleared to 0 by writing a “1” to it. Writing a “0” to it has no effect. INTSEE is generated with <TASM> =1, if <SOVF> flag from 0 to 1. <MODF>: Mode-fault error flag Master mode: Compatibility mode: The <MODF> flag is set to 1, if the SS signal goes to active low while the SEI is configured as a master. In this case: 1. The SEI output pin drivers are disabled and the output pins are placed in high-impedance state. 2. The <MSTR> bit in the SECR register is cleared to 0. 3. The <SEE> bit is forcibly cleared to 0 to disable the SEI system. 4. An interrupt INTSEM is generated. The <MODF> flag is automatically cleared to 0 by reading the SESR register with the <MODF> bit set to 1, followed by a write to SECR register. Micro DMA mode: It is the same as that of the compatibility mode, except the <MODF> flag's clearance. This flag can only be cleared to 0 by writing a “1” to it. Writing a “0” to this flag has no effect. Slave mode: Always reads as undefined, writes to this flag have no effect. <TSRC>: Receive completion flag Compatibility mode: Always reads as undefined, writes to this flag have no effect. Micro DMA mode: The <TSRC> flag is set to 1 when a receiving has been completed, that is when eight cycles where shifted on the SECLK signal. It is cleared to 0 by performing a read operation on the SEI data register, by switching to compatibility mode or by writing a “1” to this flag. Writing a “0” to this flag has no effect. An interrupt INTSER will be generated on the assertion of this flag.

<TSTC>: Transmit completion flag Compatibility mode: Always reads as undefined, writes to this flag have no effect. Micro DMA mode: Timing where the flag is set by transfer format and master/slave is different though < TSTC > flag is set when to 0 by performing a write operation on the SEI data regi ster, by switching to compatibility mode or by writing a “1” to this flag. Writing a “0” to this flag has no effect. An interrupt INTSET will be generated on the assertion on this flag. <TASM>: Automated shift mode（master）／INTSEE interrupt mask（slave） Compatibility mode: Always reads as undefined, writes to this flag have no effect. Micro DMA mode: The function of this bit is depending on <MSTR> bit setting. Master mode: 0: Disables the automated shift mode. 1: Enables the automated shift mode. In this mode a read access to the SEI data register SEDR will perform the following functions. ・ The SEI data register will be cleared to 00 hex. ・ A new transfer will be initiated, thus in master mode 8 low bits will be sent, 8 new bits will be received. The automated shift mode also works when it is combined with a micro DMA. It has no effect, when SEI is in the slave mode. Slave mode: This bit functions as a mask for the interrupt INTSEE generation of the <SOVF> and <WCOL> flags. 0: An interrupt INTSEE will be generated when the <WCOL> flag is set to “1”, but not effect on the <SOVF> flag. 1: An interrupt INTSEE will be generated when the <SOVF> flag is set to “1”, but not effect on the <WCOL> flag. <TMSE>: SEI mode select 0: Compatibility mode. 1: Micro DMA mode. Selects the micro DMA mode, which also allows micro DMA transfers. It is necessary to disable the SEI system before switching to the micro DMA mode.

(3) SEI data register (SEDR) SEI Data Register SEDR 7 6 5 4 3 2 1 0 (Transmission) bit Symbol SED7 SED6 SED5 SED4 SED3 SED2 SED1 SED0 (0062H) Read/Write W After reset 0 0 0 0 0 0 0 0 SEDR 7 6 5 4 3 2 1 0 (Receiving) bit Symbol SED7 SED6 SED5 SED4 SED3 SED2 SED1 SED0 (0062H) Read/Write R After reset 0 0 0 0 0 0 0 0 Note: SEDR is not able to read, modify, write. This register is used to transmit and receive data. When the SEI system configured as a master, transfers are started by a software write to the SEDR register. After once starting transmission, please write after checking that the transmission end flag has surely set by interrupt or polling when master device writes to SEDR register. Only when the <SEE> bit of the SECR register is “1”, a read/write to the SEDR register is possible. When the <SEE> bit is “0”, the write access is ignored and “00H” will be read whenever it read.

3.11.8 SEI system errors

Three system errors can be detected by the SEI device. The first type error arises in a multiple-master system when more than one SEI device simultaneously tries to be master. This error is called a mode fault. The second type error, a write collision, indicates that an attempt has been made to write data to the SEDR while a transfer was in progress. The third error occurs when the SEI system is configured as a slave and a new byte of data has been completely shifted in by the remote bus master before the old byte could be read. (1) Mode-fault error In the SEI system, if more than one device is simultaneously set as the master, competition arises among the drivers. When an SEI device is set as the master, a mode fault error occurs when the SS pin input goes L and the driver output goes off. This phenomenon can be used to avoid competition among masters. When a mode fault error occurs, the following action is immediately taken. z The SECR register’s <MSTR> bit is forcibly cleared to 0 to set the SEI for slave. z The SECR register’s <SEE> bit is forcibly cleared to 0 to disable the SEI system. z The SESR register’s <MODF> flag is set to 1, and INTSEM interrupt pulse is generated. z The SEI output pin drivers are disabled and the output pins are placed in the high-impedance state. When the problem which has caused the mode fault is resolved in software, the <MODF> flag is cleared to 0 and the SEI system can be set up to return to normal operation. The writing is not able to the SECR register while the <MODF>flag is set. In compatibility mode the <MODF> flag is automatically cleared by reading the SESR register while the <MODF> flag is set to 1, and then writing to the SECR register. In micro DMA mode the <MODF> flag is cleared to 0 by writing a 1 to it. Only when two or more devices are selected at the same time as the master, this product detects a mode fault error. The collision of the MISO output when two or more slave devices are selected on the SEI system cannot be detected. The drivers can be protected from latch-up by means of an open-drain. This involves changing the SEI output driver to be of open-drain type. The SECLK pin, MOSI pin and MISO pin can be individually set as open-drain programmably. In the case, an additional external pull-up register is necessary. (2) Write collision error A write collision occurs is the SEDR register is written to while a transfer is in progress. Because the SEDR register is not a double buffer in the direction of the transmission, writing before transfer in the SEDR register is writing directly in the SEI shift register. Because this write corrupts any transfer in progress, a write collision error is generated. The transfer continues undisturbed and the write data which caused the error is not written to the shift register. A write collision is normally a slave error because a slave has no control over when a master will initiate a transfer. A master knows when a transfer is in progress, thus, there is no excuse for a master generating a write collision error. Despite this, the SEI device can detect write collision in a master as well as in a slave. In slave mode a write collision is likely to occur, since the master shifts data faster, than it can be handled by the slave. A write collision will occur, when the slave is transferring a new value to the data register after the master started the next shift cycle. In micro DMA mode an interrupt on INTSEE will occur if the module is configured as a slave, the <TASM> bit is clear to 0 and the <WCOL> flag is set to 1.

(3) Slave mode overflow error On an SEI bus the transmission bit rate is determined by the master. It becomes easy to cause the problem that the slave cannot follow to the master's transmission by a high-speed bit rate, i.e. that the data is shifted in faster than it can be processed by slave. The SEI device detects data overflowing with < SOVF > flag of the SESR register. The <SOVF> flag will be set to 1 when: z The SEI is configured as a slave. z An old byte of data is still waiting to be read when a new byte of data has been completely received. When <SOVF> is set to 1, it signifies that SEDR has been overwritten by new byte data. Since this error only occurs in slave mode, the <TASM> bit can be used as an interrupt mask for this flag. If the <SOVF> flag in the status register is set to 1, an interrupt is only generated on INTSE0 if the current mode is micro DMA mode and the <TASM> bit is 1.

3.11.9 Interrupt generation

Interrupt processing differs for the two SEI operating modes, which can be selected using the <TMSE> bit in the SESR register. It generates four interrupts par one SEI that are INTSEM, INTSEE, INTSER and INTSET. (1) Compatibility mode In compatibility mode the INTSEM* and INTSEE are used. *The SEI generates the INTSEM interrupt, if the <MODF> flag in the SESR register shows a transition from “0” to “1”. And it generates the INTSEE interrupt, if the <SEF> flag shows a transition from “0” to “1”. INTSEM Interrupt on <MODF> INTSEE Interrupt on <SEF> INTSER Inactive INTSET Inactive (2) Micro DMA mode In micro DMA mode all four interrupts are used to allow the micro DMA transfers to and from the SEI data register. The INTSEM is generated on a transition of the <MODF> flag from “0” to “1”. The INTSEE is generated if the module is in slave mode on a transition of the <WCOL> flag from “0” to “1” with <TASM> bit is “0” or on a transition of the <SOVF> flag from “0” to “1” with <TASM> bit is “1”. After a completed transfer both the <TSRC> flag and the <TSTC> flag in the SESR register are set to 1 simultaneously. However, there is an exception for <CPHA> equals “0” in slave mode. Please see “3.11.4(1) transfer format of <CPHA>=0”. Both flags trigger the INTSER and INTSET interrupts. The <TSRC> flag generates an interrupt INTSER on a transition from “0” to “1”. The <TSRC> flag can be cleared by either reading the SEDR register or by writing a “1” value to this flag. The <TSTC> flag generates an interrupt INTSET on a transition from “0” to “1”. The <TSTC> flag is cleared to 0 by either writing the SEDR register or by writing a “1” value to this flag. In order to use the micro DMA, the INTSER interrupt and the INTSET interrupt are used as a trigger of micro DMA transmission. The INTSER interruption: The data read from the SEDR register is used as a trigger of micro DMA transfer. The INTSET interruption: A new data write to the SEDR register is used as a trigger of micro DMA transfer. Thus initiating a new transfer. INTSEM Interrupt on <MODF> INTSEE Interrupt on <WCOL>１） or <SOVF> ２） INTSER Interrupt on <TSRC> INTSET Interrupt on <TSTC> Note 1) In slave mode, it is at the time of <TASM> =0 Note 2) In slave mode, it is at the time of <TASM> =1 The Interrupts can be disabled individually at the interrupt controller.

3.11.10 Usage of the micro DMA of SEI ( micro DMA mode )

The usage of the micro DMA for larger SEI transfers allows speed up the communication on the SEI by z reducing the CPU effort for interrupt processing, z reducing the time gap between two successive transfers. The micro DMA transfers can be used in both the master and the slave mode. (1) Read/write micro DMA transfer In this mode two micro DMA channels are used. One micro DMA channel is used to send the receive data from the SEDR register to the memory. The other micro DMA channel is used to send the new data from the memory to the SEDR register. The data transfer will be completely handled by the micro DMA controller. ① Initiation In this mode, set < TMSE > bit of the SESR register to 1 and set it to micro DMA mode. Two micro DMA channels have to be set up for the transfer. One micro DMA is triggered on the INTSER to transfer the value that was received from the SEDR register to the memory. The other micro DMA is triggered on the INTSET to write new data from the memory to the SEDR register. Restart transfer by this setting in the master mode. The micro DMA with the lower channel has to be assigned to the INTSER interrupt since it takes precedence over the micro DMA with the higher channel number. The micro DMA transfer is initiated the first time by writing the first transfer value to the SEDR register. The following transfers will be handled automatically by the micro DMA controller. Table 3.11.4 SEI setting when micro DMA transfer (read/write) 0:Slave INTSEE interrupt mask 1 1:Master 0 1 ② Micro DMA transfer Once initiated the micro DMA wait to be triggered by a completed transfer. On a completed transfer both <TSRC> and <TSTC> flags are set to 1 and both SEI receive completed interrupt pulse INTSER and SEI transmit completed interrupt pulse INTSET are generated. Since the micro DMA channel with the lower channel number takes precedence, the read micro DMA transfer is performed before the write micro DMA transfer. The read micro DMA reads the value from the SEDR register and stores the value at the location specified within the micro DMA control registers. The read access also clears the <TSRC> flag to 0 in effect. After this the write micro DMA transfers a value from a specified memory address to the SEDR register. The write access to the SEDR register automatically clears the <TSTC> flag in the SESR register to 0 and starts a new transfer when the module is in master mode. After each micro DMA transfer the count registers for both micro DMA are decreased. This procedure continues until the counters reach the value of “0”. A micro DMA interrupt will be generated to indicate the end of the micro DMA transfer. An interrupt service routine triggered on the end of the micro DMA transfer can be used to re-initiate the micro DMA transfers.

Figure 3.11.6 Flowchart for Micro DMA Read/Write Transfer Setup lower micro DMA register for automated read, triggered on INTSER Initiation SEI for micro DMA mode Refer to Table 3.11.4 Setup higher micro DMA register for automated read, triggered on INTSER If SEI is setup as a master, start the first write transfer by writing the first value to the SEDR register. Write data in the SEDR register before transfer when SEI is slave mode. Register initial setting Wait on transfer completed <TSRC>,<TSTC>=1 generates INTSER,INTSET Read micro DMA transfer (Since the read micro DMA owns the lower channel number the read micro DMA is processed first.) Micro DMA is written at the address which reads SEDR register and was set up by transmission destination address register. The read-access to the SEDR register automatically clears the <TSRC>flag to 0. Write micro DMA transfer Decrease micro DMA counter Micro DMA reads the address set to by transmitting agency address register, and writes it to SEDR register. According to a setup of transmission mode register, transmission destination address register serves as address increment, decrement, or fixation. Decrease micro DMA counter The write-access to the SEDR register automatically clears the <TSTC>flag to 0. Generate micro DMA transfer end interrupts for both channels NO YES END According to a setup of transmission mode register, transmission destination address register serves as address increment, decrement, or fixation. micro DMA counter = 0?

(2) Read only micro DMA transfer This mode is used to shift in lager blocks of data, while “don’t care data” is shifted out (e.g.: reads from serial EEPROM). Only a single micro DMA is used to store the data read from the SEDR register to a specified RAM area. ① Initiation For this mode the SEI has to be configured for micro DMA mode by setting the SESR<TMSE> to 1. When SEI is acting as master, the <TASM> bit has to be set additionally to allow the automated shifting. Just one micro DMA has to be set up to transfer the SEDR data to a memory location specified within the micro DMA destination address register. The SEI receive completion interrupt INTSER is used to trigger this micro DMA. The SEI transfer completion interrupt INTSET is disabled at the interrupt controller. If SEI is set up as a master, the first transfer has to be initiated by writing the SEDR register. Table 3.11.5 SEI setting when micro DMA transfer (read) 0: Slave INTSEE interrupt mask1 1: Master 1 1 ② Micro DMA transfer After initiating the first transfer, the micro DMA waits for the transfer to be completed. With the completion of the transfer both the SESR<TSRC> and SESR<TSTC> are set to 1. On setting the <TSRC> to 1, the INTSER interrupt is generated to trigger the micro DMA. The <TSTC> flag will be set to 1 simultaneously and will remain set to 1 till the end of the block transfer. The micro DMA moves the received value from the SEDR register to the memory location specified in its destination address register. After the micro DMA transfer, the count register of the micro DMA is decreased. When the SEDR register is read, the SEDR register (shift register) is cleared to "00H" automatically because <TASM>bit is 1. Simultaneously a new transfer is started automatically. This procedure will repeat until the micro DMA counter reaches a value of “0”. A micro DMA interrupt will be generated to indicate the end of the micro DMA transfer. Moreover, about the <TSTC> flag, it remains set to 1 after the first transmission end, unless it is reset.

m i c r o D M A c o u n t e r = 0 ? Figure 3.11.7 Flowchart for Micro DMA Read only Transfer If SEI is setup as a master, start the first write transfer by writing the first value to the SEDR register. Set SEI to micro DMA mode. Set it to the automatic shift mode (<TASM>=1) when SEI is a master. Refer to Table 3.11.5 <TSRC>=1 generates INTSER Register initial setting Setup micro DMA channel for automated read, triggered on INTSER. transfer beginning Wait on transfer completed Read micro DMA transfer Micro DMA is written at the address which reads SEDR register and was set up by read transmission destination address register. According to a setup of transmission mode register, transmission destination address register serves as address increment, decrement, or fixation. Decrease micro DMA counter The read-access to the SEDR register automatically clears <TSRC>flag to 0. When <TASM>=1 1, Clears SEDR register (00H) 2, Start a new transfer automatically 3, new 8 bits are shifted in Generate micro DMA transfer end interrupts NO YES END

(3) Write only micro DMA transfer The write only transfer mode is used to transmit larger blocks of data while the incoming data is ignored. Only a single micro DMA is used to transfer new transmit data from a memory location specified by the micro DMA source address register to the SEDR register. ① Initiation For this mode the module has to be configured for micro DMA mode by setting the SESR<TMSE> to 1. One of the micro DMA channels has to be set up for the automated write to the SEDR register. This micro DMA is triggered by the SEI transmit completion interrupt INTSET. The SEI receive completion interrupt INTSER is disabled at the interrupt controller. If SEI is set up as a master, the first transfer is initiated by writing the first value to the SEDR register. Table 3.11.6 SEI setting when micro DMA transfer (write) 0: Slave INTSEE interrupt mask1 1: Master 0 1 ② Micro DMA transfer After starting the first transfer the micro DMA waits for the transfer to be completed. On completion both the <TSRC> and <TSTC> flags in the SEI status register are set to 1. Disregard <TSRC>flag and <SOVF>flag because reception is not used. After the first transmission end, the <TSRC> flag is set and it remains set to 1 unless it is reset. Once the <SOVF> flag is set to 1, the <SOVF> flag remains being 1, unless it is reset. The <TSTC> flag generates the INTSET interrupt, which will trigger the micro DMA transfer. The micro DMA reads a value from the memory address specified in its source register and transfers it to the SEDR register. After the micro DMA transfer, the count register of the micro DMA is decreased. The write access to the SEDR register clears the <TSTC> flag to 0 and starts a new transfer on the SEI bus when the module is in master mode. This procedure continues until the Micro DMA counter reaches a value of “0”. A micro DMA interrupt will be generated to indicate the end of the micro DMA transfer.

micro DMA counter = 0? Figure 3.11.8 Flowchart for Micro DMA Write only Transfer Register initial setting If SEI is setup as a master, start the first write transfer by writing the first value to the SEDR register. Set SEI to micro DMA mode. Refer to Table 3.11.6 <TSTC>=1 generates INTSET Setup micro DMA channel for automated read, triggered on INTSET. transfer beginning Wait on transfer completed Write micro DMA transfer Micro DMA is written at the address set up by transmitting agency address register, and writes it to SEDR register. According to a setup of transmission mode register, transmission destination address register serves as address increment, decrement, or fixation. Decrease micro DMA counter The write-access to the SEDR register automatically clears <TSTC>flag to 0. Generate micro DMA transfer end interrupts NO YES END

3.12 CAN Controller

(1) Overview z Supports CAN version 2.0B z Supports standard format and extended format z Supports data frames and remote frames in both format z 16 Mailboxes (15 Receive & Transmit + 1 Receive only) z Baud rate up to 1Mbps on the CAN bus (at fc = 20MHz) z Programmable baud rate with bit time parameter z Built in baud rate prescaler z 2 selectable mechanism for internal arbitration of transmit messages ① mailbox number ② identifier priority z Time stamp for receive and transmit messages z Operation modes ① Normal operation mode ② Configuration mode ③ Sleep mode (Wake up on CAN bus activity or CPU access) ④ Halt mode ⑤ Test loop back mode (Enable the stand alone operation by self acknowledge) ⑥ Test error mode (Write enable to error counter) z Acceptance filter ① Programmable global mask for mailboxes 0 to 14 ② Programmable local mask for mailbox 15 z Acceptance mask bit for identifier extended bit z Flexible interrupt structure (3 interrupts) ① INTCR: Receive interrupt ② INTCT: Transmit interrupt ③ INTCG: Global interrupt (include warning level, error passive, bus off, and so on) (2) Nomenclature z R/W Read and write access by the CPU z R Read access by the CPU z W Write access by the CPU z R/S Read access and set (write with 1) by the CPU z R/C Read access and clear (write with 1) by the CPU z The bit Symbol “ ” in the mailbox denotes blank bits. The values of these bits are indeterminate when read. z The column of after Reset “ – ” in the mailbox indicates that the initial value is indeterminate. z The bit Symbol “ ” in the control register denotes reserved bits. They indicate that the value is indeterminate when read. Always write “0” when write.

(3) Architecture Figure 3.12.1 Block Diagram of CAN Controller (4) CAN bus interface The interface to the Can bus is a simple two-wire line, consisting of an input pin RX and an output pin TX. This CAN bus interface is suitable for the operation with CAN bus transceivers based on ISO/DIS 11898. CAN State Machine Mailbox 16×128 bits CPU Interface Control Register Interrupt Logic CAN Protocol Controller Transmit buffer Data field Identifier Transmit multiplexor Transmit data Data Address SaveData Receive Data TX RX Internal Priority Compare register Control Bus Internal Control ADR Data R D W R D A RD W R D A Mailbox Data Out Mailbox Data In Write decoder Temporary receive buffer Data field Identifier Match ID R D W R A Time stamp counter GAM mask LAM mask Acceptance filter Compare register Write Identifier (Compare) INTCR INTCT INTCG

3.12.1 Memory map

The mailboxes and control registers used by the CAN are mapped to the memory locations shown below. Table 3.12.1 CAN Mailboxes and Control Registers Address Register Description 000200H * 000202H * 0002FEH * MB0MI0 MB0MI1 MB15TSV Mailbox 000300H MC Mailbox Configuration Register 000302H MD Mailbox Direction Register 000304H * TRS Transmit Request Set Register 000306H * TRR Transmit Request Reset Register 000308H * TA Transmission Acknowledge Register 00030AH * AA Abort Acknowledge Register 00030CH * RMP Receive Message Pending Register 00030EH * RML Receive Message Lost Register 000310H LAM0 (high) Local Acceptance Mask Register 0 (bit 28 to 16) 000312H LAM1 (low) Local Acceptance Mask Register 1 (bit 15 to 0) 000314H GAM0 (high) Global Acceptance Mask Register 0 (bit 28 to 16) 000316H GAM1 (low) Global Acceptance Mask Register 1 (bit 15 to 0) 000318H MCR Master Control Register 00031AH GSR Global Status Register 00031CH BCR1 Bit Configuration Register 1 00031EH BCR2 Bit Configuration Register 2 000320H * GIF Global Interrupt Flag Register 000322H GIM Global Interrupt Mask Register 000324H * MBTIF Mailbox Transmit Interrupt Flag Register 000326H * MBRIF Mailbox Receive Interrupt Flag Register 000328H MBIM Mailbox Interrupt Mask Register 00032AH CDR Change Data Request Register 00032CH * RFP Remote Frame Pending Register 00032EH * CEC CAN Error Counter Register 000330H TSP Time Stamp Counter Prescaler Register 000332H * TSC Time Stamp Counter Register Note: * Read-modify-write prohibited.

3.12.2 Mailboxes

The mailbox is configured with Register to store identifiers and transmit/receive data, which can be accessed by the CAN controller and the CPU. The CPU controls the CAN controller by modifying the contents of the mailboxes and contro l registers. The contents of the mailboxes and control registers are used to perform the functions of the acceptance filtering, transmit message and interrupt handling. In order to initiate a transfer, the transmission request bit has to be written to the corresponding register. The entire transmissi on procedure is done then without any CPU involvement. If a mailbox has been configured as receive messages the CPU easily reads its data registers using CPU read instructions. The mailbox may be configured to interrupt the CPU after every successful message transmission or reception. The mailbox module provides 16 mailboxes, each of which has 8 bytes long data, 29-bit identifier and several control bits. Each mailbox, except the last one, can be set for either transmit or receive operation. Mailbox 15 is a receive-only mailbox with a special acceptance mask designed to allow groups of different messag e identifiers to be received. Each mailbox is 16 bytes in size. Address Mailboxes 0200H to 020FH MB0 (Used for transmit/receive) 0210H to 021FH MB1 (Used for transmit/receive) : : : : 02E0H to 02EFH MB14 (Used for transmit/receive) 02F0H to 02FFH MB15 (Used for receive-only) Each mailbox is configures as shown below. (Mailbox “n”) b15 b0 MBn + 00H MI0 (Message identifier field 0) 02H MI1 (Message identifier field 1) 04H MCF (Message control field) 06H D1 D0 (Data field 0,1) 08H D3 D2 (Data field 2,3) 0AH D5 D4 (Data field 4,5) 0CH D7 D6 (Data field 6,7) 0EH TSV (Time stamp value) Note: MBn = 0200H + n×10H, n = 0, 1, 2, …, 15 The components of each mailbox are explained in the next pages.

Message Identifier Field 0 (MI0) Message Identifier Field 0 Low MBnMI0L 7 6 5 4 3 2 1 0 (MBn+00H) bit Symbol ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 Read/Write R/W After reset - - - - - - - - Message Identifier Field 0 High MBnMI0H 15 14 13 12 11 10 9 8 (MBn+01H) bit Symbol IDE GAME RFH ID28 ID27 ID26 ID25 ID24 Read/Write R/W After reset - - - - - - - - Remote frame processing bit 0 For transmit mailbox, remote frame are not responded to. 1 For transmit mailbox, remote frame are responded to. (The <TRS> bit is set.) 0/1 For receive mailbox, they are processed as data frames. (The <RMP> and <RFP> bits are set.) Global (local) acceptance mask enable 0 Acceptance mask is not used for acceptance filtering. 1 Acceptance mask is used for acceptance filtering. For mailbox 15, it functions as local acceptance mask enable bit <LAME>. Identifier extension bit

0 Standard format (11-bit identifier)

Identifiers <ID28> to <ID18> are used.

1 Extended format (29-bit identifier)

Identifiers <ID28> to <ID0> are used. The priority of a message ID becomes so high that 0 continues from the MSB (<ID28> bit) of ID. Note: When ID of the received remote frame is corresponding to ID of the transmission mailbox <RFH>=1 and <GAME>=1, ID of remote frame is overwritten to this mailbox. Afterward, it responds applying overwritten ID automatically. Identifiers <ID23> to <ID16> are stored. Identifiers <ID28> to <ID24> are stored. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Message Identifier Field 1 (MI1) Message Identifier Field 1 Low MBnMI1L 7 6 5 4 3 2 1 0 (MBn+02H) bit Symbol ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Read/Write R/W After reset - - - - - - - - Message Identifier Field 1 High MBnMI1H 15 14 13 12 11 10 9 8 (MBn+03H) bit Symbol ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Read/Write R/W After reset - - - - - - - - Note1: For standard format, identifiers <ID17> to <ID0> are indeterminate. Note2 : Set the mailbox ID at initial configuration. When rewriting to MI0 or MI1 field of the mailbox which is permitted, after forbidding a mailbox by resetting the <MC> bit, and then carry out. However, reception is stopped, when it resets to <MC> =0, while a mailbox is receiving. When a mailbox is transmitting (<TRS>=1), after transmission is completed (<TRS>=0), please rewrite the MI0 or MI1 field. Identifiers <ID7> to <ID0> are stored. Identifiers <ID15> to <ID8> are stored. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Message Control Field (MCF) Message Control Field Low MBnMCFL 7 6 5 4 3 2 1 0 (MBn+04H) bit Symbol RTR DLC3 DLC2 DLC1 DLC0 Read/Write R/W After reset - - - - - Remote transmit request bit

0 Data frame

1 Remote fame

<DLC3:0> Data Bytes Corresponding Mailbox Data 0000 0 byte None 0001 1 byte D0 0010 2 bytes D1, D0 0011 3 bytes D2, D0, D0 0100 4 bytes D3, D2, D1, D0 0101 5 bytes D4, D3, D2, D1, D0 0110 6 bytes D5, D4, D3, D2, D1, D0 0111 7 bytes D6, D5, D4, D3, D2, D1, D0 1000 8 bytes D7, D6, D5, D4, D3, D2, D1, D0 Note: Do not use data length codes other than those listed above. Message Control Field High MBnMCFH 15 14 13 12 11 10 9 8 (MBn+05H) bit Symbol Read/Write After reset In the case of a receiving mailbox, there is no necessity for an initial configuration. RTR and DLC of the received message are stored in the MCF register. In the case of a transmitting mailbox, please set at the initial configuration. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Data field (D0 to D7) This is a read/write register that stores up to 8 by tes of transmit/receive data. However, in the case of receive mailboxes, the write access to the data field is disabled. For transmit, data in a length of bytes set by the mailbox’s data length code is transmitted. For receive, the data length code in the receive message is copied to the mailbox’s data length code, so that the byte in a length equal to this data length code is receives as valid data. Data Field 0 MBnD0 7 6 5 4 3 2 1 0 (MBn+06H) bit Symbol D07 D06 D05 D04 D03 D02 D01 D00 Read/Write R/W After reset - - - - - - - - Data Field 1 MBnD1 15 14 13 12 11 10 9 8 (MBn+07H) bit Symbol D17 D16 D15 D14 D13 D12 D11 D10 Read/Write R/W After reset - - - - - - - - Data Field 2 MBnD2 7 6 5 4 3 2 1 0 (MBn+08H) bit Symbol D27 D26 D25 D24 D23 D22 D21 D20 Read/Write R/W After reset - - - - - - - - Data Field 3 MBnD3 15 14 13 12 11 10 9 8 (MBn+09H) bit Symbol D37 D36 D35 D34 D33 D32 D31 D30 Read/Write R/W After reset - - - - - - - - Data Field 4 MBnD4 7 6 5 4 3 2 1 0 (MBn+0AH) bit Symbol D47 D46 D45 D44 D43 D42 D41 D40 Read/Write R/W After reset - - - - - - - - Data Field 5 MBnD5 15 14 13 12 11 10 9 8 (MBn+0BH) bit Symbol D57 D56 D55 D54 D53 D52 D51 D50 Read/Write R/W After reset - - - - - - - - Data Field 6 MBnD6 7 6 5 4 3 2 1 0 (MBn+0CH) bit Symbol D67 D66 D65 D64 D63 D62 D61 D60 Read/Write R/W After reset - - - - - - - - Data Field 7 MBnD7 15 14 13 12 11 10 9 8 (MBn+0DH) bit Symbol D77 D76 D75 D74 D73 D72 D71 D70 Read/Write R/W After reset - - - - - - - - Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Time Stamp Value (TSV) Time Stamp Value Low MBnTSVL 7 6 5 4 3 2 1 0 (MBn+0EH) bit Symbol TSV7 TSV6 TSV5 TSV4 TSV3 TSV2 TSV1 TSV0 Read/Write R After reset - - - - - - - - Time Stamp Value High MBnTSVH 15 14 13 12 11 10 9 8 (MBn+0FH) bit Symbol TSV15 TSV14 TSV13 TSV12 TSV11 TSV10 TSV9 TSV8 Read/Write R After reset - - - - - - - - This is a 16-bit read only register into which the value of the time stamp counter is loaded when data is successfully transmitted or received. The counter value is not loaded this register when transmit or receive operation failed.

3.12.3 Control registers

Mailbox configuration register (MC) Mailbox Configuration Register Low MCL 7 6 5 4 3 2 1 0 (0300H) bit Symbol MC7 MC6 MC5 MC4 MC3 MC2 MC1 MC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Mailbox Configuration Register High MCH 15 14 13 12 11 10 9 8 (0301H) bit Symbol MC15 MC14 MC13 MC12 MC11 MC10 MC9 MC8 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Each bit corresponds to mailbox 0 through 15. Each mailbox can be enabled or disabled. When <MCn> = 0, access to mailbox “n” is disabled. When <MCn> = 1, access to mailbox “n” is enabled. Set the mailbox ID at the initial configuration. Before rewriting the mailbox’s MI0 or MI1 field, be sure to clear the <MC> bit to disable the corresponding mailbox. However, when <MC> bit is cleared to 0 during reception, the reception is stopped immediately. When a mailbox is transmitting (<TRS>=1), please rewrite the MI0 or MI1 field after transmission is completed (<TRS>=0). The transmit mailbox data and control fields can be accessed for write at any time. However, in the case of transmit mailboxes with the <RFH> bit is set to 1, the write access to the message control field is enabled during the <MC> bit is cleared to 0. Mailbox direction register (MD) Mailbox Direction Register Low MDL 7 6 5 4 3 2 1 0 (0302H) bit Symbol MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Mailbox Direction Register High MDH 15 14 13 12 11 10 9 8 (0303H) bit Symbol MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 Read/Write R R/W After reset 1 0 0 0 0 0 0 0 Each bit corresponds to mailbox 0 through 15. Each mailbox except mailbox 15 can be directed for transmit or receive. When <MDn> = 0, the mailbox MBn is directed for transmit. When <MDn> = 1, the mailbox MBn is directed for receive. Mailbox 15 is a receive-only mailbox, so that <MD15> bit is fixed to “1”. This bit can only be read; you cannot write to it. Set the MD register at initial configuration. When changing MD register, please carry out after clearing <MCn> bit of a corresponding mailbox.

(1) Transmit control registers Transmission request set register (TRS) Transmission Request Set Register Low TRSL 7 6 5 4 3 2 1 0 (0304H) bit Symbol TRS7 TRS6 TRS5 TRS4 TRS3 TRS2 TRS1 TRS0 Read/Write R/S After reset 0 0 0 0 0 0 0 0 Transmission Request Set Register High TRSH 15 14 13 12 11 10 9 8 (0305H) bit Symbol TRS14 TRS13 TRS12 TRS11 TRS10 TRS9 TRS8 Read/Write R/S After reset 0 0 0 0 0 0 0 Each bit corresponds to mailboxes 0 through 15. Since mailbox 15 is a receive-only mailbox, bit 15 is nonexistent. If after writing data and identifier to mailbox “n” that has directed for transmit (<MDn> = 0) the <TRSn> bit is set to 1 when the said mailbox is enabled (<MCn> = 1), a message is transmitted from mailbox “n”. If there are multiple transmit requests, messages are transmitted sequentially. The order in which messages are transmitted depends on the master control register MCR bit 3 <MTOS>. If <MTOS> bit is clear to 0, the mailbox with the lower number has the higher priority. For example: if the mailboxes MB0, MB2 and MB5 are configured for transmission and the corresponding TRS bits are set to 1, then the messages will be transmitted in the following order: MB0, MB2 and MB5. If a new transmission request is set for MB0 during the processing of MB2 then in the next internal arbitration-run MB0 will be selected for the next transmission. This will also happen, when the CAN controller loses arbitration while transmitting MB2. In this case, MB0 will be sent at the next opportunity instead of MB2. If <MTOS> bit is set to “1”, the priority of the identifier stored in the mailbox will determine the sending order. The mailbox with the higher priority identifier will be sent first. In case of a lost arbitration on the CAN bus line a new internal arbitration run will be started and the message with the highest priority will be sent at next possible time. The <TRSn> bit is reset when transmit has succeeded or when the transmission request concerned is cleared by setting the <TRRn> bit to 1. If transmit has failed, transmit is retried repeat edly until it succeeds or the transmission request concerned is cleared by setting the <TRRn> bit to 1. When the <TRSn> bit is “1”, the write access to the corresponding mailbox is denied. The <TRSn> bit cannot be set from the CPU if mailbox “n” is directed for receive. When mailbox “n” is directed for transmit, the <TRSn> bit is set by writing a “1” from the CPU and is cleared to 0 by the internal logic. Writing a “0” from the CPU has no effect. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Transmission request reset register (TRR) Transmission Request Reset Register Low TRRL 7 6 5 4 3 2 1 0 (0306H) bit Symbol TRR7 TRR6 TRR5 TRR4 TRR3 TRR2 TRR1 TRR0 Read/Write R/S After reset 0 0 0 0 0 0 0 0 Transmission Request Reset Register High TRRH 15 14 13 12 11 10 9 8 (0307H) bit Symbol TRR14 TRR13 TRR12 TRR11 TRR10 TRR9 TRR8 Read/Write R/S After reset 0 0 0 0 0 0 0 Each bit corresponds to mailboxes 0 through 15. Since mailbox 15 is a receive-only mailbox, bit 15 is nonexistent. If the <TRRn> bit is set to “1”, the transmit request that has been asserted by setting the corresponding <TRSn> bit is canceled. This cancellation takes place in one of the following three ways: ① If a message has not been transmitted yet, the message transmit request is canceled. (<TRSn> = 0, <TRRn> = 0, <AAn> = 1) ② If a message is currently being transmitted but a lost arbitration or an error occurs, the message transmit request is cleared and transmit operation is aborted. (<TRSn> = 0, <TRRn> = 0, <AAn> = 1) ③ If a message is currently being transmitted and no lost arbitration or error occurs, transmit operation is completed without ever clearing the message transmit request. (<TRSn> = 0, <TRRn> = 0, <TAn> = 1) When the <TRRn> bit is “1”, the write access to the corresponding mailbox is denied. The <TRRn> bit cannot be set from the CPU if mailbox “n” is directed for receive. When mailbox “n” is directed for transmit the <TRRn> bit is set by writing a “1” from the CPU and is cleared to 0 by the internal logic in case of a successful transmission or an aborted transmission. Writing a “0” from the CPU has no effect. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Transmission acknowledge register (TA) Transmission Acknowledge Register Low TAL 7 6 5 4 3 2 1 0 (0308H) bit Symbol TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Transmission Acknowledge Register High TAH 15 14 13 12 11 10 9 8 (0309H) bit Symbol TA14 TA13 TA12 TA11 TA10 TA9 TA8 Read/Write R/C After reset 0 0 0 0 0 0 0 Each bit corresponds to mailboxes 0 through 15. Since mailbox 15 is a receive-only mailbox, bit 15 is nonexistent. The <TAn> bit is set when the message of mailbox “n” has been transmitted successfully. In this case, a transmission successful interrupt is generated if it has been enabled. The <TAn> bit is cleared to 0 by writing a “1” to the <TAn> bit or the <TRSn> bit from the CPU. Writing a “0” from the CPU has no effect. Abort acknowledge register (AA) Abort Acknowledge Register Low AAL 7 6 5 4 3 2 1 0 (030AH) bit Symbol AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Abort Acknowledge Register High AAH 15 14 13 12 11 10 9 8 (030BH) bit Symbol AA14 AA13 AA12 AA11 AA10 AA9 AA8 Read/Write R/C After reset 0 0 0 0 0 0 0 Each bit corresponds to mailboxes 0 through 15. Since mailbox 15 is a receive-only mailbox, bit 15 is nonexistent. The <AAn> bit is set when the transmission of the message of mailbox “n” has been aborted. In this case, a global interrupt (transmit abort) is generated if it has been enabled. The <AAn> bit is cleared to 0 by writing a “1” to the <AAn> bit or the <TRSn> bit from the CPU. Writing a “0” from the CPU has no effect. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Change data request register (CDR) Change Data Request Register Low CDRL 7 6 5 4 3 2 1 0 (032AH) bit Symbol CDR7 CDR6 CDR5 CDR4 CDR3 CDR2 CDR1 CDR0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Change Data Request Register High CDRH 15 14 13 12 11 10 9 8 (032BH) bit Symbol CDR14 CDR13 CDR12 CDR11 CDR10 CDR9 CDR8 Read/Write R/W After reset 0 0 0 0 0 0 0 Each bit corresponds to mailboxes 0 through 15. Since mailbox 15 is a receive-only mailbox, bit 15 is nonexistent. If the <CDRn> bit is 1, a transmission request for mailbox “n” will be ignored. That means, that a mailbox “n” with the <TRSn> and <CDRn> bit is set to 1, it will not be considered in the internal arbitration-run: the mailbox “n” is locked for transmission. The processing of mailbox “n” in the arbitration-run will be considered again after clearing the <CDRn> bit. The <CDR> bit is useful for dealing with remote frames. It is intended for updating the data field of a transmit mailbox, which is configured for automatic reply to remote frames (the <RFH> bit is set). By using the <CDR> bit, the user can update the data field without a need of taking additional care of the data consistency.

(2) Receive control registers The identifier of each incoming message is compared with the identifiers held in the mailboxes that have been directed for receive operation. The comparison of the identifiers depends on the value of the global/local acceptance mask enable bits <GAME>/<LAME> in the mailbox and the data held in the global/local acceptance mask registers GAM/LAM. When a matching identifier is detected, the received identifier, control bits, and data bytes are written to the mailbox that has matched. At this time, the corresponding receive message pending bit <RMPn> is set and receive successful interrupt is generated if it has been enabled. Once a matching identifier is found, no other identifiers are compared. If not match is detected, the message is rejected. The CPU must reset the <RMPn> bit after reading the data. If a second message is received for this mailbox when the <RMPn> bit has already been set to 1, the corresponding receive message lost bit <RMLn> is set to 1. In this case, the data stored in mailbox “n” is overwritten with the new data. In this case, a global interrupt (receive message lost) is generated if it has been enabled. Receive-only mailbox Only if the identifier of a received message does not match any identifiers of the mailboxes 0 through 14, the identifier is compared with the identifier of the receive-only mailbox 15. When a matching identifier is detected, the contents of the received message are written to the mailbox 15. Receive message pending register (RMP) Receive Message Pending Register Low RMPL 7 6 5 4 3 2 1 0 (030CH) bit Symbol RMP7 RMP6 RMP5 RMP4 RMP3 RMP2 RMP1 RMP0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Receive Message Pending Register High RMPH 15 14 13 12 11 10 9 8 (030DH) bit Symbol RMP15 RMP14 RMP13 RMP12 RMP11 RMP10 RMP9 RMP8 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Each bit corresponds to mailbox 0 through 15. When a message is received and its content is stored in mailbox “n”, the <RMPn> bit is set to 1. If a second message is received by mailbox “n” for which the <RMPn> bit has been set to 1, mailbox “n” is overwritten with the new data. In this case, the corresponding <RMLn> bit is set. The <RMPn> bit is set to 1 by the internal logic and is cleared by writing a “1” to the <RMPn> bit from the CPU. The CPU cannot write a 0 to <RMPn> bit. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Receive message lost register (RML) Receive Message Lost Register Low RMLL 7 6 5 4 3 2 1 0 (030EH) bit Symbol RML7 RML6 RML5 RML4 RML3 RML2 RML1 RML0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Receive Message Lost Register High RMLH 15 14 13 12 11 10 9 8 (030FH) bit Symbol RML15 RML14 RML13 RML12 RML11 RML10 RML9 RML8 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Each bit corresponds to mailbox 0 through 15. If a second message is received by mailbox “n” for which the <RMPn> bit has been set to 1, mailbox “n” is overwritten with the new data and the <RMLn> bit is set to 1. The <RMLn> bit is set by the internal logic and is cleared to 0 by writing a “1” to the <RMPn> bit from the CPU. Writing a “0” to <RMPn> bit and writing a “1” or “0” to <RMLn> bit from the CPU have no effect. Table 3.12.2 Operation when message is received Before After ID Unmatched Don’t care No change No change The data in receive buffer hasn’t been transferred to any mailbox. 0 1 No change The data in receive buffer is transferred to a mailbox which matched the identifier of incoming message. (Old data in the mailbox was read out, and cleared <RMP> to 0. Then, the mailbox is written with new data; RECEIVE MESSAGE PENDING BIT is set.) Matched 1 1 1 The data in receive buffer is transferred to a mailbox which matched the identifier of incoming message (Old data is in the mailbox. Then, the mailbox is overwritten with new data; RECEIVE MESSAGE LOST BIT and RECEIVE MESSAGE PENDING BIT are set). Read modify-write instructions prohibited. Read modify-write instructions prohibited.

(3) Handling of remote frames If a r em o t e f ram e is re ce ive d, it is co m pa re d wit h the identifiers of all mailboxes. The comparison of identifiers depends on the value of the global/local acceptance mask enable bits <GAME>/<LAME> in the mailbox and the data held in the global/local acceptance mask registers GAM/LAM. If a received remo te frame matches the identifier of a mailbox that is directed for transmit and the <RFH> bit for that mailbox is set to 1, the <TRSn> bit is set to 1 in order to send a message in response to the remote frame. Even when there is a matching identifier, if the <RFH> bit for that mailbox is reset (even though it may be a transmit mailbox), the remote frame is not responded to. If there is a matching identifier and this mailbox is directed for receive, the remote frame is processed as data frame, in which case the <RMP> and <RFP> bits are set. Once a matching identifier is found, no other identifiers are compared. Table 3.12.3 Operation when Remote Frame is Received ID Mailbox <RFH> bit Handling of Remote Frame Matched Transmit 0 Not responded to. 1 Responded to. (<TRS> bit is set) *Note Receive 1/0 Not responded to. Processed as data frame. (<RMP> and <RFP> bits are set.) Unmatched Transmit/Receive 1/0 Not responded to. Note : When <GAME> = 1 of this mail box, ID of remote frame is overwritten to this mailbox. and carries out an automatic response by new ID. Remote frame pending register (RFP) Remote Frame Pending Register Low RFPL 7 6 5 4 3 2 1 0 (032CH) bit Symbol RFP7 RFP6 RF P5 RFP4 RFP3 RFP2 RFP1 RFP0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Remote Frame Pending Register High RFPH 15 14 13 12 11 10 9 8 (032DH) bit Symbol RFP15 RFP14 RFP13 RFP12 RFP11 RFP10 RFP9 RFP8 Read/Write R/C After reset 0 0 0 0 0 0 0 0 When a remote frame is received by mailbox “n” directed for receive the corresponding <RFPn> and <RMPn> bits are set. The <RFPn> bit is cleared to 0 by writing a “1” to the <RMPn> bit. Writing a “0” has no effect. Also, the <RFPn> bit is reset automatically when the remote frame received in mailbox “n” is overwritten by a newly received data frame. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

(4) Acceptance filter The global acceptance mask registers GAM0 and GAM1 are used for filtering messages when the <GAME> bit for mailboxes 0 through 14 is set to “1”. An incoming message is stored in the first mailbox with a matching identifier. Only if there is no matching identifier in the mailboxes 0 to 14, the incoming message is compared with the mailbox 15, a receive-only mailbox. The local acceptance mask registers LAM0, LAM1 are used for filtering messages when the <LAME> bit for mailbox 15 is set. Mailbox identifier Acceptance mask register Receive reques t Received message identifier Figure 3.12.2 Acceptance Filter

Local acceptance mask registers (LAM0, LAM1) Local Acceptance Mask Register 0 Low LAM0L 7 6 5 4 3 2 1 0 (0310H) bit Symbol LAM23 LAM22 LAM21 LAM20 LAM19 LAM18 LAM17 LAM16 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Local Acceptance Mask Register 0 High LAM0H 15 14 13 12 11 10 9 8 (0311H) bit Symbol LAMI LAM28 LAM27 LAM26 LAM25 LAM24 Read/Write R/W R/W After reset 0 0 0 0 0 0 Local Acceptance Mask Register 1 Low LAM1L 7 6 5 4 3 2 1 0 (0312H) bit Symbol LAM7 LAM6 LAM5 LAM4 LAM3 LAM2 LAM1 LAM0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Local Acceptance Mask Register 1 High LAM1H 15 14 13 12 11 10 9 8 (0313H) bit Symbol LAM15 LAM14 LAM13 LAM12 LAM11 LAM10 LAM9 LAM8 Read/Write R/W After reset 0 0 0 0 0 0 0 0 The LAM0 and LAM1 registers are used for only filtering messages for mailbox 15. This feature allows the user to choose whether or not to locally mask any identifier bit of the incoming message for mailbox 15. Incoming messages are first checked to see if they match mailboxes 0 to 14 before being forwarded to mailbox 15. If the <LAMn> bit is “0”, messages are received only when the corresponding bit of the incoming message identifier matches that of the mailbox identifier. If the <LAMn> bit is “1”, messages are received regardless of whether the corresponding bit of the incoming message identifier is “0” or “1”. The GAM0 and GAM1 registers do not affect mailbox 15. For messages in extended format, the identifier extension <IDE> bit and the whole 29bits of the identifier are compared. For messages in standard form at, only the <IDE> bit and the first 11bits of the identifier (<ID28> to <ID18>) are compared. The <LAMI> bit (local acceptance mask identifier extension bit) is used to mask the <IDE> bit of mailbox 15. If the <LAMI> bit is “0”, messages in extended or standard format are received according to the <IDE> bit of mailbox 15. If the <LAMI> bit is “1”, messages in both extend ed and standard formats are received regardless of whether the <IDE> bit of mailbox 15 is “0” or “1”. For messages in extended format, the whole 29bits of the mailbox identifier and the whole 29 mask bits of the LAM register are used for filtering. For messages in standard format, only the first 11bits of the mailbox identifier (<ID28> to <ID18>) and the first 11 bits of the LAM register (<LAM28> to <LAM18>) are used for filtering. Please perform the setup of LAM0 and LAM1 at initial configuration. Please do not change a setup during operation. When setting change is performed during reception, receiving message ID is compared for the receiving mask information in the middle of setting change.

Global acceptance mask registers (GAM0, GAM1) Global Acceptance Mask Register 0 Low GAM0L 7 6 5 4 3 2 1 0 (0314H) bit Symbol GAM23 GAM22 GAM21 GAM20 GAM19 GAM18 GAM17 GAM16 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Global Acceptance Mask Register 0 High GAM0H 15 14 13 12 11 10 9 8 (0315H) bit Symbol GAMI GAM28 GAM27 GAM26 GAM25 GAM24 Read/Write R/W R/W After reset 0 0 0 0 0 0 Global Acceptance Mask Register 1 Low GAM1L 7 6 5 4 3 2 1 0 (0316H) bit Symbol GAM7 GAM6 GAM5 GAM4 GAM3 GAM2 GAM1 GAM0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Global Acceptance Mask Register 1 High GAM1H 15 14 13 12 11 10 9 8 (0317H) bit Symbol GAM15 GAM14 GAM13 GAM12 GAM11 GAM10 GAM9 GAM8 Read/Write R/W After reset 0 0 0 0 0 0 0 0 The GAM0 and GAM1 registers are used for filtering messages for mailbox 0 to 14. If the <GAME> bit for mailboxes 0 to 14 is set to 1 the GAM0 and GAM1 registers are used for incoming messages. A received message is stored in only the first mailbox with a matching identifier. If the <GAMn> bit is “0”, messages are received only when the corresponding bit of the incoming message identifier matches that of the mailbox identifier. If the <GAMn> bit is “1”, messages are received regardless of whether the corresponding bit of the incoming message identifier is “0” or “1”. For messages in extended format, the identifier extension <IDE> bit and the whole 29bits of the identifier are compared. For messages in standard form at, only the <IDE> bit and the first 11bits of the identifier (<ID28> to <ID18>) are compared. The <GAMI> bit (global acceptance mask identifier extension bit) is used to mask the <IDE> bits of mailbox 0 to 14. If the <GAMI> bit is “0”, messages in extended or standard format are received according to the <IDE> bits of mailbox 0 to 14. If the <GAMI> bit is “1”, messages in both extended and standard formats are received regardless of whether the <IDE> bits of mailbox 0 to 14 are “0” or “1”. For messages in extended format, the whole 29bits of the mailbox identifier and the whole 29 mask bits of the GAM register are used for filtering. For messages in standard format, only the first 11bits of the mailbox identifier (<ID28> to <ID18>) and the first 11 bits of the GAM register (<GAM28> to <GAM18>) are used for filtering. Please perform the setup of GAM0 and GAM1 at initial configuration. Please do not change a setup during operation. When setting change is performed during reception, receiving message ID is compared for the receiving mask information in the middle of setting change.

(5) Control registers Master control register (MCR) Master Control Register Low MCRL 7 6 5 4 3 2 1 0 (0318H) bit Symbol CCR SMR HMR WUBA MTOS TSCC SRES Read/Write R/W W After reset 1 0 0 0 0 0 0 Master Control Register High MCRH 15 14 13 12 11 10 9 8 (0319H) bit Symbol TSTLB TSTERR Read/Write R/W After reset 0 0 TSTLB: Test Loop Back 0: Cancels the test loop back mode. (Normal operation) 1: Requests the test loop back mode. This mode supports stand-alone operation. TSTERR: Test Error 0: Cancels the test error mode. (Normal operation) 1: Requests the test error mode. In this mode it is possible to write the error counter register CEC. CCR: Change Configuration Request 0: Cancels the configuration mode. (Normal operation) 1: Request the configuration mode. This mode allows for writing to the bit configuration registers BCR1, BCR2. SMR: Sleep Mode Request 0: The sleep mode is not requested. (Normal operation) 1: Requests the sleep mode. When this mode is entered, the CAN controller clock stops oscillating and the error counter and transmit requests are cleared. HMR: Halt Mode Request 0: Cancels the halt mode. (Normal operation) 1: Requests the halt mode. When this mode entered, the CAN controller does no longer transmit and receive messages. It only sends error and acknowledge flags. WUBA: Wake Up on Bus Activity 0: Wakes up the module only by detecting a write access to the MCR register. 1: Wakes up the module when active bus state is detected or by detecting a write access to the MCR register. MTOS: Mailbox Transmission Order Select 0: Mailbox transmission order by mailbox number. The mailbox with the lower number will be sent first. 1: Mailbox transmission order by identifier priority. The mailbox with the higher priority identifier will be sent first.

TSCC: Time Stamp Counter Clear 0: No effect 1: The time stamp counter will be cleared to 0. Note 1: This is a write-only bit; it is always “0” when read. Note 2: The time stamp counter is also cleared to 0 by a write to the TSP register, or writing a “0” to the TSC register. SRES: Software Reset 0: No effect 1: Resets the CAN controller in software. All internal registers are initialized. Note: This is a write-only bit; it is always “0” when read. Bit configuration register 1 (BCR1) Bit Configuration Register 1 Low BCR1L 7 6 5 4 3 2 1 0 (031CH) bit Symbol BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 <BRP7:0> is the baud rate prescaler value. It can be set in the range of 0 to 255. Bit Configuration Register 1 High BCR1H 15 14 13 12 11 10 9 8 (031DH) bit Symbol Read/Write A f t e r r e s e t

Bit configuration register 2 (BCR2) Bit Configuration Register 2 Low BCR2L 7 6 5 4 3 2 1 0 (031EH) bit Symbol SAM TSEG22 TSEG 21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Setting of SAM Setting of TSEG2 Setting of TSEG1 <SAM> Sampling Time <TSEG22:20> Unit Time of TSCL <TSEG13:10> Unit Time of TSCL 0 1 000 Not available 0000 Not available 1 3 001 2×TSCL 0001 2×TSCL 010 3×TSCL 0010 3×TSCL 011 4×TSCL 0011 4×TSCL 100 5×TSCL 0100 5×TSCL 101 6×TSCL 0101 6×TSCL 110 7×TSCL 0110 7×TSCL 111 8×TSCL 0111 8×TSCL 1000 9×TSCL 1001 10×TSCL 1010 11×TSCL 1011 12×TSCL 1100 13×TSCL 1101 14×TSCL 1110 15×TSCL 1111 16×TSCL Bit Configuration Register 2 High BCR2H 15 14 13 12 11 10 9 8 (031FH) bit Symbol SJW1 SJW0 Read/Write R/W After reset 0 0 Setting of SJW <SJW1:0> Adjust Time 00 1×TSCL 01 2×TSCL 10 3×TSCL 11 4×TSCL The bit length is determined by parameters TSEG1, TSEG2, and BRP. All CAN controllers on the CAN bus must operate at the same baud rate. If individual CAN controllers operate with different frequencies the baud rate has to be adjusted by the mentioned parameters. In the bit timing logic, the conversion of the parameters to the required bit timing is materialized. The configuration registers BCR1 and BCR2 contains the data about the bit timing.

Figure 3.12.3 Bit Timing The length of TSCL is defined by: TSCL = (<BRP7:0>+1) / f IO ( f IO = fc divided by 2) fIO is used to the CAN controller system clock frequency (input clock of the CAN controller). The length of one bit is determined by the equation below:

1 Bit Time = SYNCSEG+TSEG1+TSEG2

1 bit time is equal or greater than 10÷fIO. The synchronization segment SYNCSEG has always the length of 1×TSCL. The length of TSEG1 should be equal or greater than the length of TSEG2. TSEG1 ≧ TSEG2. The baud rate is defined by: Baud rate = f IO÷[(<BRP7:0>+1)×((<TSEG13:10>+1)+(<TSEG22:20>+1)+1)] IPT (information processing time) is the time segment starting with the sample point reserved for processing of the sampled bit level. IPT is equal to 3 fIO clock cycles. The parameter SJW (2bit) indicates by how many units of TSCL is allowed to be lengthened or to be shortened when re-synchronizing. Values between 1 (SJW = 00b) and 4 (SJW = 11b) are adjustable. The bus line is re-synchronized at each falling edge. Th e maximum length of SJW is equal to the length of TSEG2. SJW ≦ TSEG2 With the corresponding bit timing, it is possible to reach a multiple sampling of the bus line at the sample point by setting <SAM> bit. The level determined by the CAN bus then corresponds to the result from the majority decision of the last three values. The three-time sampling is not allowed for <BRP7:0> < 4. For <BRP7:0> < 4 always a one-time sampling will be performed regardless of the value of <SAM> bit. There is a restriction as follows: <BRP7:0> TSCL length (CAN clock cycles : fIO) IPT length (CAN clock cycles : fIO) TSEG2 minimum length (TSCL) 0 1 3 3 1 2 3 2 > 1 <BRP7:0>+1 3 2 SYNCSEG SJW SJW TSEG1 TSEG2

1 Bit Time

Example1: A transmission rate of 1Mbps will be adjusted, i.e. a bit has a length of 1 μs. The CAN input clock frequency f IO is 10MHz. The baud rate prescaler is set to “0”. That means a bit for this data transmission rate has to be programmed with a length of 10 ×TSCL. Since SYNCSEG is 1 ×TSCL, it is set as 9×TSCL by TSEG1+TSEG2. E.g. <BRP7:0> = 00H <TSEG13:10> = 0100B (5 ×TSCL) <TSEG22:20> = 011B (4 ×TSCL) In this case, sampling point is 60%. With this setting a threefold sampling of the bus is not possible (<BRP7:0> < 4), thus SAM = 0 should be set. SJW is not allowed to be greater than TSEG2, so the maximum value could be set to <SJW1:0> = 11B (4×TSCL) Example2: Baud rate : 500kbps ( 1 bit time = 2 μs ) Sampling point : 80% f IO : 10MHz (a) In case of <BRP7:0> = 00H TSCL = (<BRP7:0>+1) / fIO = 1 / 10MHz = 100ns 1 bit time = 2μs / 100ns = 20×TSCL <TSEG13:10> = 1110B (15×TSCL) <TSEG22:20> = 011B (4×TSCL) (b) In case of <BRP7:0> = 01H TSCL = (<BRP7:0>+1) / fIO = 2 / 10MHz = 200ns 1 bit time = 2μs / 200ns = 10×TSCL <TSEG13:10> = 0110B (7×TSCL) <TSEG22:20> = 001B (2×TSCL) Example3: Baud rate : 500kbps ( 1 bit time = 2 μs ) Sampling point : 85% f IO : 10MHz (a) In case of <BRP7:0> = 00H TSCL = (<BRP7:0>+1) / fIO = 1 / 10MHz = 100ns 1 bit time = 2μs / 100ns = 20×TSCL <TSEG13:10> = 1111B (16×TSCL) <TSEG22:20> = 010B (3×TSCL) (b) In case of <BRP BRP7:0> = 01H TSCL = (<BRP7:0>+1) / fIO = 2 / 10MHz = 200ns 1 bit time = 2μs / 200ns = 10×TSCL In this case, 85% sampling point cannot be set up.

There is a free-running 16-bit time stamp counter TSC implemented in the CAN controller to get an indication of the time of reception or transmission of messages. The content of the TSC is written into the time stamp value TSV of the corresponding mailbox when a received message has been stored or a message has been transmitted. The TSC is driven from the bit cl ock of the CAN bus line. When the CAN controller is in configuration mode or sleep mode, the TSC will be stopped. After a reset, the TSC can be cleared to 0 by writing a value to the time stamp counter prescaler TSP. The TSC can be written and read by CPU in configuration mode and in normal operation mode. Time stamp counter register (TSC) Time Stamp Counter Register Low TSCL 7 6 5 4 3 2 1 0 (0332H) bit Symbol TSC7 TSC6 TSC5 TSC4 TSC3 TSC2 TSC1 TSC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Time Stamp Counter Register High TSCH 15 14 13 12 11 10 9 8 (0333H) bit Symbol TSC15 TSC14 TSC13 TSC12 TSC11 TSC10 TSC9 TSC8 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Overflow of the TSC can be detected by the time stamp counter overflow flag <TSO> of the global status register GSR and the time stamp counter overflow interrupt flag <TSOIF> of the global interrupt flag register GIF. Both flags are cleared to 0 by writing a “1” to the corresponding bit location in GIF. There is a 4-bit prescaler for the TSC. It is the time stamp counter prescaler register TSP that stores the value to be reloaded into this prescaler. After reset, the TSP register is cleared to “0”, so a value “0” is loaded into the prescaler. The TSC counter’s count-up period, TTSC, is shown below: TTSC = TBIT×(<TSP3:0>+1) (TBIT : bit cycle) Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Time stamp counter prescaler register (TSP) Time Stamp Counter Prescaler Register Low TSPL 7 6 5 4 3 2 1 0 (0330H) bit Symbol TSP3 TSP2 TSP1 TSP0 Read/Write R/W After reset 0 0 0 0 Time Stamp Counter Prescaler Register High TSPH 15 14 13 12 11 10 9 8 (0331H) bit Symbol Read/Write A f t e r r e s e t To be sure, that the value of the TSC will not change during the write cycle to the mailbox, there is a hold register implemented. The value of the TSC will be copied to this register if a message has been received or transmitted successfully. The reception is successful for the receiver, if there is no error until the last but one bit of End-of-frame. The transmission is successful for the transmitter, if there is no error until the last bit of End-of-frame. (Refer to the CAN version 2.0B) Figure 3.10.4 Time Stamp Counter The free running time stamp counter and the time stamp hold register will be cleared in the following cases: z After reset (hardware reset or software reset) z When the module enters configuration mode z When the module enters sleep mode z When a write access to the time stamp prescaler register is performed CPU read/write Mailbox Time Stamp Counter Hold Register (16bit) Transmission successful Time Stamp Counter Register <TSC15:0> Count-up clock Hardware reset (4bit) Prescaler Re-load value Time Stamp Counter Prescaler Register <TSP3:0> CPU read/write CAN bus bit clock Reception successful Software reset Hardware reset Software reset Entering sleep mode Entering configuration mode Write to TSP register clear clear clear load

(6) Status registers Global status register (GSR) Global Status Register Low GSRL 7 6 5 4 3 2 1 0 (031AH) bit Symbol CCE SMA HMA TSO BO EP EW Read/Write R R After reset 1 0 0 0 0 0 0 Global Status Register High GSRH 15 14 13 12 11 10 9 8 (031BH) bit Symbol MsgInSlot<3:0> RM TM Read/Write R After reset 1 1 1 1 0 0 MsgInSlot: Message In Slot Indicates a message in the transmission slot. 0000: Message of mailbox 0 0001: Message of mailbox 1 1110: Message of mailbox 14 1111: No transmission message RM: Receive Mode 0: The CAN controller is not receiving a message. 1: The CAN controller is receiving a message. That means the CAN controller is not the transmission of the message and the bus is not idle. TM: Transmit Mode 0: The CAN controller is not transmitting a message. 1: The CAN controller is transmitting a message. That means the CAN controller stays transmitter until the bus is idle or it loses arbitration. CCE: Change Configuration Enable 0: The CAN controller is not in the configuration mode. (Normal operation) 1: The CAN controller has entered the configuration mode. SMA: Sleep Mode Acknowledge 0: The CAN controller is not in the sleep mode. (Normal operation) 1: The CAN controller has entered the sleep mode. HMA: Halt Mode Acknowledge 0: The CAN controller is not in the halt mode. (Normal operation) 1: The CAN controller has entered the halt mode. TSO: Time Stamp Overflow Flag 0: There was no overflow of the time stamp counter. 1: There was at least one overflow of the time stamp counter since this bit has been cleared to 0. To clear this bit, clear the <TSOIF> bit to 0 in the GIF register.

BO: Bus Off Status 0: The CAN controller is in the bus on status. (Normal operation) 1: The CAN controller is in the bus off status. There is an abnormal rate of occurrences of errors on the CAN bus. This condition occurs when the transmit error counter TEC has reached the limit of 256. During bus off no messages can be received or transmitted. The CAN controller will go to bus on automatically after the bus off recovery sequence. After entering bus off, the error counters are undefined. EP: Error Passive Status 0: The CAN controller is in the error active mode. Both values of the error counters TEC and REC are less than 128. 1: The CAN controller is in the error passive mode. At least one of the error counters has reached the error passive status of 128. EW: Warning Status 0: Both values of the error counters TEC and REC are less than or equal to 96. 1: At least one of the error counters is greater than 96 and reached the warning level. CAN error counter register (CEC) CAN Error Counter Register Low CECL 7 6 5 4 3 2 1 0 (032EH) bit Symbol REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 CAN Error Counter Register High CECH 15 14 13 12 11 10 9 8 (032FH) bit Symbol TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 The CAN controller contains two error counters: receive error counter REC and transmit error counter TEC. The values of both counters can be read by the CPU. A write access to the error counters is only in the test error mode possible at the same time with the same value of lower 8bit. (<TSTERR> bit in MCR register is set). These error counters are incremented or decremented according to the CAN version 2.0B. A controller takes the following three states according to the value of REC and TEC. (1) Error active state (TEC < 128 and REC < 128) The state where the error has hardly occurred CAN controller is in an error active state after reset release. When an error is detected, an active error flag is transmitted. (2) Error passive state (TEC >= 128 or REC >=128) The state where many errors have occurred When an error is detected, a passive error flag is transmitted. (3) Bus off state (TEC >=256) CAN controller cannot perform the message transmission and reception to CAN bus. Receive error counter REC is not incremented after exceeding the error passive limit (128). After the correct reception of a message when REC = 128, the counter is set to a value between 119 and 127. After reaching the bus off status, the counts are undefined. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

CAN controller which changed to the bus off state will be in an error active state automatically, if the 11 continuous recessive bits on the CAN bus is detected 128 times. All internal flags are reset, and the error counters are cleared. The configuration registers keep the programmed values. The values of the error counters are undefined during bus off status. When CAN controller enters configuration mode (see 3.12.4(1) Configuration mode) the error counters will be cleared to 0. (7) Interrupt control registers The CAN controller has the following interrupt sources: z Transmit interrupt When a message has been transmitted successfully z Receive interrupt When a message has been received successfully z Remote frame pending interrupt When a remote frame is received z Wake-up interrupt When the CAN controller is awakened from sleep mode z Receive message lost interrupt When a receive message is lost z Transmission abort interrupt When at least one of the bits in the AA register is set to 1 z Time stamp counter overflow interrupt When the time stamp counter has overflowed z Bus off interrupt When the CAN controller enters the bus off mode z Error passive interrupt When the CAN controller enters the error passive mode z Warning level interrupt When at least one of the two error counters is greater than 96 and reached the warning level These interrupt sources are divided in three groups: z Transmit interrupt (INTCT) z Receive interrupt (INTCR) z Global interrupt (INTCG) There is one interrupt output line for each group. INTCR is dedicated for receive interrupts, INTCT is dedicated for transmit interrupts and INTCG for the global interrupts.

Global interrupt flag register (GIF) Global Interrupt Flag Register Low GIFL 7 6 5 4 3 2 1 0 (0320H) bit Symbol RFPF WUIF RMLIF TRMABF TSOIF BOIF EPIF WLIF Read/Write R/C After reset 0 0 0 0 0 0 0 0 Global Interrupt Flag Register High GIFH 15 14 13 12 11 10 9 8 (0321H) bit Symbol Read/Write After reset The interrupt flag bits will be set to 1 if the co rresponding interrupt condition has occurred. If the corresponding interrupt mask bit is set to 1 in the GIM register, an interrupt pulse on the global interrupt line INTCG will be generated. As long as an interrupt flag in the GIF register is set to 1, if the corresponding interrupt source generates a new interrupt event, a new interrupt pulse on INTCG will not be generated. If an interrupt flag in the GIF re gister is set and another interrupt source generates an interrupt event, then a new interrupt pulse on INTCG will be generated. If one or more interrupt flags have been cleared to 0 and one or more interrupt flags are still set to 1, a new global interrupt pulse INTCG will be generated. The interrupt flags will be cleared to 0 by writing a “1” to the corresponding bit location. RFPF: Remote Frame Pending Flag 0: No remote frame has been received. 1: A remote frame has been received (in a receive-mailbox). This bit will not be set if the identifier of the remote frame matches to a transmit-mailbox with <RFH> set to 1. WUIF: Wake-Up Interrupt Flag 0: The CAN controller is in the sleep mode or the normal operation mode. 1: The CAN controller has left the sleep mode. RMLIF: Receive Message Lost Interrupt Flag 0: No receive message has been lost. 1: At least one of the receive-mailboxes, receive message lost has been occurred. At least one of the bits in the RML register is set to 1. TRMABF: Transmission Abort Flag 0: No transmission has been aborted. 1: Transmission has been aborted. At least one of the bits in the AA register is set to 1. TSOIF: Time Stamp Counter Overflow Interrupt Flag 0: There was no overflows of the time stamp counter since this bit has been cleared. 1: There was at least one overflow of the time stamp counter since this bit has been cleared. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

BOIF: Bus Off Interrupt Flag 0: The CAN controller is still in the bus on mode. 1: The CAN controller has entered the bus off mode. EPIF: Error Passive Interrupt Flag 0: The CAN controller is still in error active mode. 1: The CAN controller has entered the error passive mode. WLIF: Warning Level Interrupt Flag 0: none of the error counters has reached the warning level. 1: At least one of the error counters has reached the warning level. Global interrupt mask register (GIM) Global Interrupt Mask Register Low GIML 7 6 5 4 3 2 1 0 (0322H) bit Symbol RFPM WUIM RMLIM TRMABM TSOIM BOIM EPIM WLIM Read/Write R/W After reset 0 0 0 0 0 0 0 0 Global Interrupt Mask Register High GIMH 15 14 13 12 11 10 9 8 (0323H) bit Symbol Read/Write After reset Each interrupt flag bits in GIF register is masked by the corresponding mask bit in GIM register. If a bit in GIM register is 0, the interrupt generation for the corresponding global interrupt event is disabled and if it is 1, the interrupt generation is enabled. After reset, all bits in GIM register are cleared to 0, there by disabling global interrupt.

Separare interrupt outputs are provided for mailbox interrupts independently of global interrupts. These include mailbox transmit interrupt INTCT and mailbox receive interrupt INTCR that depend on mailbox settings. A mailbox transmit interrupt flag register MBTIF is provided for mailbox transmit interrupts, and a mailbox receive interrupt flag register MBRIF is provided for mailbox receive interrupts. In addition, there is a mailbox interrupt mask register MBIM that enables or disables each mailbox interrupt. Mailbox interrupt mask register (MBIM) Mailbox Interrupt Mask Register Low MBIML 7 6 5 4 3 2 1 0 (0328H) bit Symbol MBIM7 MBIM6 MBIM5 MBIM4 MBIM3 MBIM2 MBIM1 MBIM0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Mailbox Interrupt Mask Register High MBIMH 15 14 13 12 11 10 9 8 (0329H) bit Symbol MBIM15 MBIM14 MBIM13 MBIM12 MBIM11 MBIM10 MBIM9 MBIM8 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Each bit corresponds to mailboxes 0 through 15. The MBIM register settings determine to enable or disable each mailbox interrupt. If a bit in MBIM register is “0”, the interrupt generation for the corresponding mailbox is disabled. If a bit in MBIM register is “1”, the interrupt generation for the corresponding mailbox is enabled.

Mailbox transmit interrupt flag register (MBTIF) Mailbox Transmit Interrupt Flag Register Low MBTIFL 7 6 5 4 3 2 1 0 (0324H) bit Symbol MBTIF7 MBTIF6 MBTIF5 MBTIF4 MBTIF3 MBTIF2 MBTIF1 MBTIF0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Mailbox Transmit Interrupt Flag Register High MBTIFH 15 14 13 12 11 10 9 8 (0325H) bit Symbol MBTIF14 MBTIF13 MBTIF12 MBTIF11 MBTIF10 MBTIF9 MBTIF8 Read/Write R/C After reset 0 0 0 0 0 0 0 This register is provided for mailbox transmit interrupts. Each bit in this register corresponds to mailboxes 0 through 15. The interrupt flag for mailbox 15, the <MBTIF15> flag, is nonexistent because mailbox 15 is the receive-only mailbox. If mailbox “n” is directed for receive, the corresponding interrupt flag in this register, the <MBTIFn> flag, will always be read as “0”. If a message in mailbox “n” has been transmitted successfully and the mask bit <MBIMn> is set to “1”, the corresponding transmit interrupt flag <MBTIFn> will be set. If no other bit was set before in MBTIF register, transmit interrupt pulse INTCT will be generated. If for a mailbox the mask bit in MBIM register is “0”, the transmit interrupt flag in MBTIF register will not be set and no transmit interrupt pulse INTCT will be generated. The information about a successful transmission could be read from the TA register respectively. If one or more transmit interrupt flags have been set in MBTIF register and another interrupt condition has been occurred no interrupt will be generated, but the corresponding flag in MBTIF register will be set. If there is one or more transmit interrupt flags set after clearing one or more transmit interrupt flags, another mailbox transmit interrupt pulse INTCT will be generated. The interrupt flags in MBTIF register will be cleared by writing a “1” from the CPU to MBTIF register. Writing a “0” has no effect. Note that the interrupt flags in MBTIF register is checked to be 1 (active), before doing a clear-access. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

Mailbox receive interrupt flag register (MBRIF) Mailbox Receive Interrupt Flag Register Low MBRIFL 7 6 5 4 3 2 1 0 (0326H) bit Symbol MBRIF7 MBRIF6 MBRIF5 MBRIF4 MBRIF3 MBRIF2 MBRIF1 MBRIF0 Read/Write R/C After reset 0 0 0 0 0 0 0 0 Mailbox Receive Interrupt Flag Register High MBRIFH 15 14 13 12 11 10 9 8 (0327H) bit Symbol MBRIF15 MBRIF14 MBRIF13 MBRIF12 MBRIF11 MBRIF10 MBRIF9 MBRIF8 Read/Write R/C After reset 0 0 0 0 0 0 0 0 This register is provided for mailbox receive interrupts. Each bit in this register corresponds to mailboxes 0 through 15. If mailbox “n” is directed for transmit, the corresponding interrupt flag in this register, the <MBRIFn> flag, will always be read as “0”. If a message in mailbox “n” has been received successfully and the mask bit <MBIMn> is set to “1”, the corresponding receive interrupt flag <MBRIFn> will be set. If no other bit was set before in MBRIF register, receive interrupt pulse INTCR will be generated. If for a mailbox the mask bit in MBIM register is 0, the receive interrupt flag in MBRIF register will not be set and no receive interrupt pulse INTCR will be generated. The information about a successful reception could be read from the RMP register respectively. If one or more receive interrupt flags have been set in MBRIF register and another interrupt condition has been occurred no interrupt will be generated, but the corresponding flag in MBRIF register will be set. If there is one or more receive interrupt flags set after clearing one or more receive interrupt flags, another mailbox receive interrupt pulse INTCR will be generated. The interrupt flags in MBRIF register will be cleared by writing a “1” from the CPU to MBRIF register. Writing a “0” has no effect. Note that the interrupt flags in MBRIF register is checked to be 1 (active), before doing a clear-access. Read modify-write instructions prohibited. Read modify-write instructions prohibited.

3.12.4 Description of Mode

(1) Configuration mode The CAN controller has to be initialized (set th e bit configuration registers BCR1 and BDR2) before the activation. The BCR1 and BCR2 registers can only be modified when the module is in the configuration mode. After reset, th e configuration mode is active and the <CCR> bit of MCR register and the <CCE> bit of GSR register are set to “1”. The CAN controller can be set to the normal operation mode by writing a “0” to <CCR> bit. After leaving the configuration mode, the <CCE> bit will be set to “0” and the power-up sequence will start. The power-up sequence consists of detecting eleven consecutive recessive bits on the CAN bus line. Afte r the power-up sequence, the CAN controller is bus on and ready for operation. When the <CCR> bit is set to “1”, the CAN controller will be entered to the configuration mode from the normal operation mode. After the CAN controll er has entered the configuration mode, the <CCE> bit will be set to “1”. See also the flowchart in Figure 3.12.5 Flowchart of CAN Initialization. When at the configuration mode, the error counter CEC, the time stamp counter TSC and the time stamp hold register will be cleared. Reset Switch to configuration mode from normal operation mode Configuration mode <CCR> = 1, <CCE> = 1 Normal operation mode <CCR> = 0, <CCE> = 0 Set bit timing parameters in BCR1 & BCR2 Configuration mode no requested? Normal operation mode no yes requested? Set <CCR> to 1 y e s Set <CCR> to 0 <CCE> = 1? no y e s <CCE> = 0? no y e s Normal operation mode <CCR> = 0, <CCE> = 0 Starts power-up sequence 11 consecutive recessive no bits detected? y e s Bus on Figure 3.12.5 Flowchart of CAN Initialization

(2) Sleep mode The sleep mode will be requested by writing 1 to the <SMR> bit of the MCR register. When the CAN controller enters the sleep mode, the status bit <SMA> of the GSR register will be set to 1. During the sleep mode the clock of the CAN controller is switched off. Only the wake up logic will be active. The read value of the GSR register will be F040H, this means, there is no message in transmit buffer and the sleep mode is active (<SMA> bit is set to 1). Read accesses to all other registers will deliver the value 0000H. Write accesses to all registers but the MCR register will be denied. The CAN controller leaves the sleep mode if a write access to the MCR register has been detected or there is any bus activity detected on the CAN bus line (with <WUBA> = 1), the CAN controller begins its power up sequence. The CAN controller waits until detecting 11 consecutive recessive bits on the RX input line and goes to bus active after them. The first message that initiates the bus activity can not be received. In sleep mode the CAN error counters and all ‘transmission request set bits <TRSn>’ and ‘transmission request reset bits <TRRn> will be cleared to 0. After leaving the sleep mode, <SMR> bit in the MCR register and <SMA> bit in the GSR register will be cleared to 0. If the CAN controller is transmitting a message when the <SMR> bit is set to 1, the CAN controller will not switch to the sleep mode immediately. It will continue until a successful transmission or after losing the arbitration, until a successful reception or until an error condition occurs on the CAN bus line. By this means the CAN controller will initiates no error condition on the CAN bus line. (3) Halt mode The halt mode will be requested by writing 1 to the <HMR> bit of the MCR register. When the CAN controller enters the halt mode, the <HMA> bit of the GSR register will be set. During the halt mode the CAN controller does not send or receive any messages. The CAN controller is still active on the CAN bus line. Error Flags and Acknowledge Flags will be sent. The CAN controller leaves the halt mode if the <HMR> bit is reset to 0. If the CAN controller is transmitting a message when the <HMR> bit is set, the transmission will be continued until a successful transmission or detect a lost arbitration. So the CAN controller initiates no error condition on the CAN bus line. (4) Test loop back mode In this mode, the CAN controller can receive its own transmitted message and will generate its own acknowledge bit. No other CAN controller is necessar y for the operation. The on ly supposition is that the RX and TX lines must be connected to a CAN bus transceiver or directly together. In the test loop back mode, the CAN controller ca n transmit a message from one mailbox and receive it in another mailbox. The set-up for the mailboxes is the same as in the normal operation mode. The test loop back mode shall only be enabled or disabled in the configuration mode. Figure 3.12(6) shows the flowchart of the test loop back mode / the test error mode set-up.

(5) Test error mode The error counters can only be written when the CAN controller is in the test error mode. When the CAN controller is in the test error mode, both error counters will be written at the same time with the same value (lower 8 bit). The maximum value that can be written into the error counters is 255. Thus, the error counter value of 256 which forces the CAN controller into the bus off mode can not be written into the error counters. The test error mode shall only be enabled or disabled in the configuration mode. Figure 3.12(6) shows the flowchart of the test loop back mode / the test error mode set-up. Enable / disable test loop back mode / test error mode Normal operation mode <CCR> = 0, <CCE> = 0 Configuration mode request Set <CCR> to 1 <CCE> = 1? No y e s Set-up <TSTLB>/<TSTERR> 0: disable 1: enable Normal operation mode request Set <CCR> to 0 <CCE> = 0? No y e s End of set-up Normal operation mode Figure 3.12.6 Flowchart of the test loop back mode / the test error mode set-up

3.12.5 Functional description

(1) Transmit mode Figure 3.12.7 shows one example of the flowchar t of message transmit by using the transmit interrupt INTCT. It is also possible to use polling instead of interrupt. In this case, “Transmit interrupt generated?” is replaced by “<TAn> = 1?”. “Set <MBIMn> to 1” and “Clear <MBTIFn>” must be removed from the flow. Set-up message Transmitting message transmission yes New setup? S e t < M C n > t o 0 n o no Set <MDn> to 0 Update mailbox data? S e t u p I D , < I D E > y e s to mailbox “n” Write new data Setup <MTOS> no Transmission request? Set <MBIMn> to 1 y e s Set <MCn> to 1 Set <TRSn> to 1 End of setup no Transmit interrupt generated? y e s Check <TAn> Special user tasks (update mailbox data) Clear <TAn>,<MBTIFn> RETI Figure 3.12.7 Flowchart of message transmission (Example)

(2) Receive mode If the CAN controller has received a message from the CAN bus line, this message will be located in the receive buffer. The message stored in the received buffer will be compared to the identifier of mailbox. If <GAME>/<LAME> bit is set, the global/local acceptance mask register GAM/LAM will be used. If there is one of the following conditions found, no further compare will be done. z Data fame and a matching identifier in a mailbox configured as receive z Remote frame and a matching identifier in a mailbox configured as receive z Remote frame and a matching identifier in a mailbox configured as transmit and <RFH> bit is set The minimum time to save a next received message after the <RMP> bit set depends on the configured bit timing. In case of the data length code = 0, the minimal time is as follows. z Standard format: 47 bit times – 16 f IO z Extended format: 67 bit times – 16 f IO

3.13 Analog/Digital Converter

TMP92CD54I incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 12-channel analog input. Figure 3.13.1 is a block diagram of the AD converter. The 12-channel analog input pins (AN0 to AN11) are shared with the input-only port Port G and Port L, so they can be used as an input port. Note: When IDLE1, IDLE2, IDLE3 or STOP Mode is selected, as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled. Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed. INTAD interrupt AN11 (PL3) AN10 (PL2) AN9 (PL1) AN8 (PL0) AN7 (PG7) AN6 (PG6) AN5 (PG5) AN4 (PG4) AN3 (PG3) AN2 (PG2) AN1 (PG1) AN0 (PG0) Comparator VREFH VREFL Multiplexer Sample and Hold AD mode control register 1 ADMOD1 <ADCH3:0> <VREFON> Scan Repeat Interrupt Busy End Start Internal data bus Decoder AD mode control register 0 ADMOD0 AD Conversion Result Register ADREG0L to ADREGBL ADREG0H to ADREGBH DA converter AD Converter Control Circuit Channel select Analog input R C Note: R: internal resistance = 7k ohm (reference data) C: internal capacitance = 10pF+4pF (reference data) Figure 3.13.1 Block diagram of AD converter

3.13.1 Analog/Digital converter registers

The AD converter is controlled by the two AD Mode Control Registers: ADMOD0 and ADMOD1. The twelve AD Conversion Data Result Registers (ADREG0H/L, ADREGBH/L) store the results of AD conversion. Figure 3.13.2 shows the registers related to the AD converter. AD Mode Control Register 0 7 6 5 4 3 2 1 0 Bit symbol EOCF ADBF − − ITM0 REPEAT SCAN ADS Read/Write R R/W After Reset 0 0 0 0 0 0 0 0 Function AD Conversion End flag 0: conversion in progress 1: conversion complete A D Conversion Busy flag 0: conversion stopped 1: Conversion in progress Note: Always fixed to 0 Note: Always fixed to 0 Interrupt specification in conversion channel fixed repeat mode 0: every conversion 1: every fourth conversion Repeat mode specification 0: Single Conversion 1: Repeat Conversion Mode Scan mode specification 0: Conversion Channel Fixed Mode 1: Conversion Channel Scan Mode AD conversion start 0: Don’t care 1: start conversion Always 0 when read AD conversion start 0D o n ’ t c a r e

1 Start AD conversion

Note: Always read as 0. AD scan mode setting

0 AD Conversion Channel Fixed Mode

1 AD Conversion Channel Scan Mode

0 AD Single Conversion Mode

1 AD Repeat Conversion Mode

Specify AD conversion interrupt for Channel Fixed Repeat Conversion Mode Channel Fixed Repeat Conversion Mode 0 Generates interrupt every conversion. 1 Generates interrupt every fourth conversion. AD Conversion Busy flag

0 AD conversion stopped

1 AD conversion in progress

0 Before or during AD conversion

1 AD conversion complete

(0138H) Figure 3.13.2 AD Converter Related Register

AD Mode Control Register 1 7 6 5 4 3 2 1 0 Bit symbol VREFON I2AD － － ADCH3 ADCH2 ADCH1 ADCH0 Read/Write R/W R/W R/W After Reset 0 0 0 0 0 0 0 0 Function VREF application control 0: OFF 1: ON IDLE2 0: Stop 1: Operate Note: Always fixed to 0 Note: Always fixed to 0 Analog input channel selection Analog input channel selection <SCAN> <ADCH3:0> channel fixed channel scanned

0000 AN0 AN0

0001 AN1 AN0 → AN1

0010 AN2 AN0 → AN1 → AN2

0011 AN3 AN0 → AN1 → AN2 → AN3

0100 AN4 AN0 → AN1 → AN2 → AN3

→ AN4

0101 AN5 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5

0110 AN6 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5 → AN6

0111 AN7 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5 → AN6 → AN7

1000 AN8 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5 → AN6 → AN7 → AN8

1001 AN9 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5 → AN6 → AN7 → AN8 → AN9

1010 AN10 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5 → AN6 → AN7 → AN8 → AN9 → AN10

1011 AN11 AN0 → AN1 → AN2 → AN3

→ AN4 → AN5 → AN6 → AN7 → AN8 → AN9 → AN10 → AN11 IDLE2 control

0 Stopped

1 In operation

Control of application of reference voltage to AD converter 0O F F 1O N Before starting conversion (before writing 1 to ADMOD0 <ADS>), set the <VREFON> bit to ADMOD1 (0139H) Figure 3.13.3 AD Converter Related Register

AD Conversion Result Register 0 Low 7 6 5 4 3 2 1 0 Bit symbol ADR01 ADR00 ADR0RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result AD Conversion Data Storage flag 1: Conversion result stored AD Conversion Result Register 0 High 7 6 5 4 3 2 1 0 Bit symbol ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 Read/Write R After Reset Undefined Function Stores upper eight bits AD conversion result. AD Conversion Result Register 1 Low 7 6 5 4 3 2 1 0 Bit symbol ADR11 ADR10 ADR1RF Read/Write R R After Reset Undefined - - - - - 0 Function stores lower 2 bits of AD conversion result AD Conversion Result flag 1: Conversion result stored AD Conversion Result Register 1 High 7 6 5 4 3 2 1 0 Bit symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADREG0L (0120H) ADREG0H (0121H) ADREG1L (0122H) ADREG1H (0123H) ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit 0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.4 AD Converter Related Registers

AD Conversion Result Register 2 Low 7 6 5 4 3 2 1 0 Bit symbol ADR21 ADR20 ADR2RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. A/D conversion data storage flag 1: Conversion result stored AD Conversion Result Register 2 High 7 6 5 4 3 2 1 0 Bit symbol ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. AD Conversion Result Register 3 Low 7 6 5 4 3 2 1 0 Bit symbol ADR31 ADR30 ADR3RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. AD Conversion Data Storage flag 1: conversion result stored AD Conversion Result Register 3 High 7 6 5 4 3 2 1 0 Bit symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADREG2L (0124H) ADREG2H (0125H) ADREG3L (0126H) ADREG3H (0127H) ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit 0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.5 AD Converter Related Registers

AD Conversion Result Register 4 Low 7 6 5 4 3 2 1 0 Bit symbol ADR41 ADR40 ADR4RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. A/D conversion data storage flag 1: Conversion result stored AD Conversion Result Register 4 High 7 6 5 4 3 2 1 0 Bit symbol ADR49 ADR48 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. AD Conversion Result Register 5 Low 7 6 5 4 3 2 1 0 Bit symbol ADR51 ADR50 ADR5RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. AD Conversion Data Storage flag 1: conversion result stored AD Conversion Result Register 5 High 7 6 5 4 3 2 1 0 Bit symbol ADR59 ADR58 ADR57 ADR56 ADR55 ADR54 ADR53 ADR52 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADREG4L (0128H) ADREG4H (0129H) ADREG5L (012AH) ADREG5H (012BH) ADREGxH ADREGxL

• Bits 5 to1 are always read as 1.
• Bit 0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.6 AD Converter Related Registers

AD Conversion Result Register 6 Low 7 6 5 4 3 2 1 0 Bit symbol ADR61 ADR60 ADR6RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. A/D conversion data storage flag 1: Conversion result stored AD Conversion Result Register 6 High 7 6 5 4 3 2 1 0 Bit symbol ADR69 ADR68 ADR67 ADR66 ADR65 ADR64 ADR63 ADR62 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. AD Conversion Result Register 7 Low 7 6 5 4 3 2 1 0 Bit symbol ADR71 ADR70 ADR7RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. AD Conversion Data Storage flag 1: conversion result stored AD Conversion Result Register 7 High 7 6 5 4 3 2 1 0 Bit symbol ADR79 ADR78 ADR77 ADR76 ADR75 ADR74 ADR73 ADR72 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADREG6L (012CH) ADREG6H (012DH) ADREG7L (012EH) ADREG7H (012FH) ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit 0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.7 AD Converter Related Registers

AD Conversion Result Register 8 Low 7 6 5 4 3 2 1 0 Bit symbol ADR81 ADR80 ADR8RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. A/D conversion data storage flag 1: Conversion result stored AD Conversion Result Register 8 High 7 6 5 4 3 2 1 0 Bit symbol ADR89 ADR88 ADR87 ADR86 ADR85 ADR84 ADR83 ADR82 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. AD Conversion Data Register 9 Low 7 6 5 4 3 2 1 0 Bit symbol ADR91 ADR90 ADR9RF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. AD Conversion Data Storage flag 1: conversion result stored AD Conversion Result Register 9 High 7 6 5 4 3 2 1 0 Bit symbol ADR99 ADR98 ADR97 ADR96 ADR95 ADR94 ADR93 ADR92 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADREG8L (0130H) ADREG8H (0131H) ADREG9L (0132H) ADREG9H (0133H) ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit 0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.8 AD Converter Related Registers

AD Conversion Result Register A Low 7 6 5 4 3 2 1 0 Bit symbol ADRA1 ADRA0 ADRARF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. A/D conversion data storage flag 1: Conversion result stored AD Conversion Result Register A High 7 6 5 4 3 2 1 0 Bit symbol ADRA9 ADRA8 ADRA7 ADRA6 ADRA5 ADRA4 ADRA3 ADRA2 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. AD Conversion Result Register B Low 7 6 5 4 3 2 1 0 Bit symbol ADRB1 ADRB0 ADRBRF Read/Write R R After Reset Undefined - - - - - 0 Function Stores lower 2 bits of AD conversion result. AD Conversion Data Storage flag 1: conversion result stored AD Conversion Result Register B High 7 6 5 4 3 2 1 0 Bit symbol ADRB9 ADRB8 ADRB7 ADRB6 ADRB5 ADRB4 ADRB3 ADRB2 Read/Write R After Reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ADREGAL (0134H) ADREGAH (0135H) ADREGBL (0136H) ADREGBH (0137H) ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit 0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.9 AD Converter Related Registers

3.13.2 Description of operation

(1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance. The result of the division is then compared with the analog input voltage. To turn off the switch between VREFH and VREFL, write a 0 to ADMOD1<VREFON> in AD Mode Control Register 1. To start AD conversion in the OFF state, first write a 1 to ADMOD1<VREFON>, wait 3 μs until the internal reference voltage stabilizes (this is not related to fc), then set ADMOD0<ADS> to 1. (2) Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter.

• In Analog Input Channel Fixed Mode (ADMOD0<SCAN> = 0) Setting ADMOD1<ADCH3:0> selects one of the input pins AN0~AN11 as the input channel.
• In Analog Input Channel Scan Mode (ADMOD0<SCAN> = 1) Setting ADMOD1<ADCH3:0> selects one of the twelve scan modes. Table 3.13.1 illustrates analog input channel selection in each operation mode. On a Reset, ADMOD0<SCAN> is set to 0 and ADMOD1<ADCH3~ADCH0> is initialized to 0000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input channels can be used as standard input port pins. Table 3.13.1 Analog input channel selection <ADCH3:0> Channel fixed <SCAN> = “0” Channel scan <SCAN> = “1”

0100 AN4 AN0 → AN1 → AN2 → AN3 → AN4

0101 AN5 AN0 → AN1 → AN2 → AN3 → AN4 → AN5

0110 AN6 AN0 → AN1 → AN2 → AN3 → AN4 → AN5 → AN6

0111 AN7 AN0 → AN1 → AN2 → AN3 → AN4 → AN5 → AN6 → AN7

1000 AN8 AN0 → AN1 → AN2 → AN3 → AN4 → AN5 → AN6 → AN7 → AN8

1001 AN9 AN0 → AN1 → AN2 → AN3 → AN4 → AN5 → AN6 → AN7 → AN8 → AN9

1010 AN10 AN0 → AN1 → AN2 → AN3 → AN4 → AN5 → AN6 → AN7 → AN8 → AN9 → AN10

1011 AN11 AN0 → AN1 → AN2 → AN3 → AN4 → AN5 → AN6 → AN7 → AN8 → AN9 → AN10 → AN11

(3) Starting AD Conversion To start AD conversion, write a 1 to ADMOD0<ADS> in AD Mode Control Register 0 .When AD conversion starts, the AD Conversion Busy flag ADMOD0<ADBF> will be set to 1, indicating that AD conversion is in progress. (4) AD conversion modes and the AD Conversion End interrupt The four AD conversion modes are:

• Channel Fixed Single Conversion Mode
• Channel Scan Single Conversion Mode
• Channel Fixed Repeat Conversion Mode
• Channel Scan Repeat Conversion Mode The ADMOD0<REPET> and ADMOD0<SCAN> settings in AD Mode Control Register 0 determine the AD mode setting. Completion of AD conversion triggers an INTAD AD Conversion End interrupt request. Also, ADMOD0<EOCF> will be set to 1 to indicate that AD conversion has been completed. ① Channel Fixed Single Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> to 00 selects Conversion Channel Fixed Single Conversion Mode. In this mode data on one specified channel is converted once only. When the c o n v e r s i o n h a s b e e n c o m p l e t e d , t h e A D M O D 0 < E O C F > f l a g i s s e t t o 1 , ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated. ② Channel Scan Single Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> to 01 selects Conversion Channel Scan Single Conversion Mode. In this mode data on the specified scan ch annels is converted once only. When scan conversion has been completed, ADMOD0<EOCF> is set to 1, ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated. ③ Channel Fixed Repeat Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> to 10 selects Conversion Channel Fixed Repeat Conversion Mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0<EOCF> is set to 1 and ADMOD0<ADBF> is not cleared to 0 but held at 1. INTAD interrupt request generation timing is determined by the setting of ADMOD0<ITM0>. Setting <ITM0> to 0 generates an interrupt request every time an AD conversion is completed. Setting <ITM0> to 1 generates an interrupt request on completion of every fourth conversion.

④ Channel Scan Repeat Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> to 11 selects Conversion Channel Scan Repeat Conversion Mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is set to 1 and an INTAD interrupt request is generated. ADMOD0<ADBF> is not cleared to 0 but held at 1. To stop conversion in a repeat conversion mode (i.e. in cases ③ and ④), write a 0 to ADMOD0<REPET>. After the current conversion has been completed, the repeat conversion mode terminates and ADMOD0<ADBF> is cleared to 0. Switching to a halt state (IDLE2 Mode with ADMOD1<I2AD> cleared to 0, IDLE1 Mode or STOP Mode) immediately stops operation of the AD converter even when AD conversion is still in progress. In repeat conversion modes (i.e. in cases ③ and ④), when the halt is released, conversion restarts from the beginning. In single conversion modes (i.e. in cases ① and ②), conversion does not restart when the halt is released (the converter remains stopped). Table 3.13.2 shows the relationship between the AD conversion modes and interrupt requests. Table 3.13.2 Relationship Between AD Conversion Modes and Interrupt Requests ADMOD0 Mode Interrupt Request Generation <ITM0> <REPET> <SCAN> Channel Fixed Single Conversion Mode After completion of conversion X 0 0 Channel Scan Single Conversion Mode After completion of scan conversion X 0 1 Every conversion 0 Channel Fixed Repeat Conversion Mode Every forth conversion 1 1 0 Channel Scan Repeat Conversion Mode After completion of every scan conversion X 1 1 X: Don’t care

(5) AD conversion time 160/fc (8 µs @ fc = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD Conversion Data Upper and Lower Registers (ADREG0H/L to ADREGBH/L) store the results of AD co nversion. (ADREG0H/L to ADREGBH/L are read-only registers.) In Channel Fixed Repeat Conversion Mode, the conversion results are stored successively in registers ADREG0H/L to ADREG3H/L. In other modes the AN0, AN1, AN2, AN3, AN4, AN5, AN6, AN7 conversion results are stored in ADREG0H/L, ADREG1H/L, ADREG2H/L, ADREG3H/L, ADREG4H/L, ADREG5H/L, ADREG6H/L, ADREG7H/L, ADREG8H/L, ADREG9H/L, ADREGAH/L, ADREGBH/L respectively. Table 3.13.3 shows the correspondence between the analog input channels and the registers which are used to hold the results of AD conversion. Table 3.13.3 Correspondence Between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog input channel (Port G/Port L) Conversion modes other than at right Channel fixed repeat conversion mode (every 4 th conversion) AN0 ADREG0H/L AN1 ADREG1H/L AN2 ADREG2H/L AN3 ADREG3H/L AN4 ADREG4H/L AN5 ADREG5H/L AN6 ADREG6H/L AN7 ADREG7H/L AN8 ADREG8H/L AN9 ADREG9H/L AN10 ADREGAH/L AN11 ADREGBH/L ADREG0H/L ADREG1H/L ADREG2H/L ADREG3H/L <ADRxRF>, bit 0 of the AD conversion da ta lower register, is used as the AD conversion data storage flag. The storage flag indicates whether the AD conversion result register has been read or not. When a conversion result is stored in the AD conversion result register, the flag is set to 1. When either of the AD conversion result registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0. Reading the AD conversion result also clears the AD Conversion End flag ADMOD0<EOCF> to 0.

Setting example: ① Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Main routine: 7 6 5 4 3 2 1 0 INTE0AD ← 1 1 0 0 - - - - Enable INTAD and set it to Interrupt Level 4. ADMOD1 ← 1 1 0 0 0 0 1 1 Set pin AN3 to be the analog input channel. ADMOD0 ← X X 0 0 0 0 0 1 Start conversion in Channel Fixed Single Conversion Mode. Interrupt routine processing example: WA ← ADREG3 Read value of ADREG3L and ADREG3H into 16-bit general-purpose register WA. WA > > 6 Shift contents read into WA six times to right and zero-fill uppe r bits. (0800H) ← WA Write contents of WA to memory address 0800H. ② This example repeatedly converts the anal og input voltages on the three pins AN0, AN1 and AN2, using Channel Scan Repeat Conversion Mode. INTE0AD ← 1 0 0 0 - - - - Disable INTAD. ADMOD1 ← 1 1 0 0 0 0 1 0 Set pins AN0~AN2 to be the analog input channels. ADMOD0 ← X X 0 0 0 1 1 1 Start conversion in Channel Scan Repeat Conversion Mode. Note: X = Don’t care; “−” = No change

3.14 Watchdog Timer (Runaway Detection Timer)

TMP92CD54I contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset.

3.14.1 Configuration

Figure 3.14.1 is a block diagram of the watchdog timer (WDT). Internal Reset WDMOD <WDTP1:0> Reset WDT Control register WDCR Binary Counter (22 Stage) Internal Reset WDMOD <RESCR> INTWD interrupt φ(2 / fc) Selector 216/fc WDMOD <WDTE> Internal data bus Write B1H RESET Reset Control 218/fc 2 20/fc 2 22/fc Write 4EH HALT instruction executing (STOP, IDLE3 or IDLE1 mode ) Q R S Figure 3.14.1 Block Diagram of Watchdog Timer

3.14.2 Control registers

The watchdog timer WDT is controlled by three control registers WDMOD, WDCR and CLKMOD. (1) Watchdog Timer Mode Register (WDMOD) i) Setting the detection time for the watchdog timer in <WDTP1,WDTP0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a Reset this register is initialized to WDMOD<WDTP1,WDTP0> = 00. The detection times for WDT is 2 16/fc [s]. (The number of system clocks is approximately 65,536.) ii) Watchdog timer enable/disable control register <WDTE> At reset, the WDMOD<WDTE> is initialized to 1, enabling the watchdog timer. To disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (B1H) to the Watchdog Timer Control Register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting <WDTE> to 1. iii) Watchdog timer out reset connection <RESCR> This register is used to connect the output of the watchdog timer with the RESET terminal internally. Since WDMOD<RESCR>is initialized to 0 at reset, a reset by the watchdog timer will not be performed. (2) Watchdog Timer Control Register (WDCR) This register is used to disable and clear the binary counter for the watchdog timer.

• Disable control The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then writing the disable code (B1H) to the WDCR register. WDMOD ← 0 - - - - - - - Clear WDMOD<WDTE> to 0. WDCR ← 1 0 1 1 0 0 0 1 Write the disable code (B1H).
• Enable control Set WDMOD<WDTE>to 1.
• Watchdog timer clear control To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR register. In the case of using watchdog timer after INTWD request generated, the clear code (4EH) should be written to the WDCR register in other to clear the binary counter. WDCR ← 0 1 0 0 1 1 1 0 Write the clear code (4EH). (3) Clock Mode Register (CLKMOD) This register is used to set the warming up time after the stop mode ends. The output of CLK pin is chosen from fc and 2/5fc by the setup of CLKMOD <CLKM1,CLKM0>. Moreover, CLK pin output can be stopped by writing “0” in CLKMOD <CLKOE>. By the setup of CLKMOD <HALTM1,HALTM0>, it becomes the HALT mode of IDLE1, IDLE2, IDLE3 or STOP.

bit symbol WDTE WDTP1 WDTP0 - DRVE I2WDT RESCR - Read/Write R/W R/W After reset 1 0 0 - 0 0 0 0 Function WDT control 1: enable Select detecting time 00: 2 16/fC 01: 218/fC 10: 220/fC 11: 222/fC 1: Drives pins in STOP mode IDLE2 0: Stop 1: Operate 1: Internally connects WDT out to the reset pin Always write 0 Watchdog timer out control

1 Connects WDT out to a reset

1 Operation

Watchdog timer detection time 00 2 16/fC (approximately 3.28ms @ fc = 20MHz) 01 2 18/fC (approximately 13.1ms @ fc = 20MHz) 10 2 20/fC (approximately 52.4ms @ fc = 20MHz) 11 2 22/fC (approximately 210ms @ fc = 20MHz) Watchdog timer enable/disable control Figure 3.14.4 Watchdog Timer Mode Register 7 6 5 4 3 2 1 0 Bit symbol − Read/Write W After reset − Function B1H: WDT disable code 4EH: WDT clear code WDT disable/clear control B1H Disable code 4EH Clear code Others Don’t care Figure 3.14.5 Watchdog Timer Control Register WDCR (0111H) WDMOD (0110H)

bit Symbol HALTM1 HALTM0 - - - CLKOE CLKM1 CLKM0 Read/Write R/W R/W R/W After reset 1 1 - 0 - 0 0 0 Function Standby mode 00: IDLE3 01: STOP 10: IDLE1 11: IDLE2 Fixed to “0” CLKoutput enable 0: not output 1: output CLK output select 00: fc 01: Reserved 10: 2/5 fc 11: Reserved CLK output clock select 00 fc Selects standby mode by HALT instruction Figure 3.14.6 Clock Mode Register CLKMOD (010AH)

3.14.3 Operation

The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1,WDTP0> has elapsed. The watchdog timer must be zero-cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti-mulfunction program. The watchdog timer begins operating immediately on release of the watchdog timer reset. The watchdog timer is reset and halted in IDLE1, IDLE3 or STOP Modes. When the device is in IDLE2 mode, the operation of WDT depends on the WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters IDLE2 Mode. Example: i) Clear the binary counter. WDCR ← 0 1 0 0 1 1 1 0 Write the clear code (4EH). ii) Set the watchdog timer detection time to 2 18/ fC. iii) Disable the watchdog timer. WDMOD ← 0 - - X - - - - Clear <WDTE> bit to 0. WDCR ← 1 0 1 1 0 0 0 1 Write the disable code (B1H).

3.15 RAM control

RAM control register (RAMCR) has <RAMWI>bit for inhibition to write data to internal RAM and <RAMSTB> bit to detect lower voltage under VSTB level. VSTB level is the voltage level impossible to keep the data of Internal RAM. Only data “1” can be written to RAMCR<RAMSTB>, and data “0” can’t be written. When RAMCR<RAMSTB> is set to “1” by software, in the case of voltage drop under VSTB level RAMCR<RAMSTB> is reset to “0”. After power on RAMCR<RAMSTB> is reset to “0”. RAMCR<RAMSTB> is not changed by standby operation and reset operation. The detection of reset operation (Warm reset / Power-on reset) and the condition of RAM data (kept / lost) is enable, to read RAMCR<RAMSTB>. RAM Write Inhibit<RAMWI> bit is used for inhibition to write data to internal RAM. After reset RAMCR<RAMWI> is set to “1”, writing data to internal RAM is accepted. When RAMCR<RAMWI> is set to “0”, writing data to internal RAM is inhibited. 7 6 5 4 3 2 1 0 Bit Symbol RAMSTB RAMWI - - - - - - Read/Write R/W After reset 0 *Note1 1 - - - - - - RAMCR (016DH) Function 0:lost data or Power on reset 1:kept data Internal RAM write 0:Inhibit 1:accept W r i t e c o n t r o l t o I n t e r n a l R A M

0 Inhibit to write to Internal RAM

1 Accept to write to Internal RAM

0 After “1” is set by software, this bit is reset to “0” at VCC3 ≦VSTB. After power on reset. 1 After “1” is set by software, this data isn’t changed at VCC3＞VSTB. Note1: After power-on reset, initialized to 0. No change by warm reset. Use after setting to 1 by software. 0 cannot be written by software. Note2: When changed to STOP or Idle3 in HALT mode with RAMCR<RAMSTB> set to 1, current flows. Note3: Emulator doesn’t support RAM control functions. Note4: To set to RAMCR<RAMSTB> bit to “1”, need 8 state (@ fc = 20MHz; For that time, do not set Idle2, 3 or STOP mode.). After that, the power-supply detection circuit runs. Note5: VCC3 means internal voltage. (Note) There are restrictions at un-use of Voltage regulator (see section “4.2 DC Electrical Characteristics”). RAM standby flag

3.16 Timer for Real Time Clock (RTC)

TMP92CD54I features a timer which is used for real time count. An interrupt (INTRTC) can be clock. A clock function can be easily used. Timer for Real Time Clock can operate in all mode in which a low frequency oscillation is operated. (except STOP mode) In addition, INTRTC can return the device from every standby mode except STOP mode to the NORMAL mode.

3.16.1 Block diagram

3.16.2 SFRs

RTC has 2 registers. Timer for Real Time Clock is controlled by Timer for Real-Time Clock Control Register (RTCCR). The period of interrupt request INTRTC is selected from 6 types by setting <RTCSEL2 to 0>. To start/stop the counter is controlled by <RTCRUN>. The low frequency oscillator is controlled by Timer for Real Time Function Register(RTCFC). If it is released from STOP mode, without RESET input, RTCFC will be initialized. 14-stage binary counter 211 212 213 214 215 216 INTRTC interrupt RTCCR<RTCSEL2:0> RTCCR<RTCRUN> RUN /CLEAR Selector fs (32.768 kHz) XT2 XT1 Low Frequency OSC RTCFC<XTEN> Figure 3.16.1 Block diagram for timer for real-time clock RTCFC<XTSEL>

Timer for Real Time Clock Control Register 7 6 5 4 3 2 1 0 Bit symbol - - - - RTCSEL2 RTCSEL1 RTCSEL0 RTCRUN Read/Write R/W R/W R/W After Reset 0 - - - 0 0 0 0 Function Write 0 1x0:216/fs (2s) 1x1:215/fs (1s) x:Don’t care 000:2 14/fs(0.50s) 001:213/fs(0.25s) 010:212/fs(0.125s) 0: Stop& Clear 1: Run 000 0.50s 001 0.25s 010 0.125s 011 0.0625s 1x0 2s 1x1 1s Figure 3.16.1 Timer for Real Time Clock Control Register Timer for Real Time Clock Function Register 7 6 5 4 3 2 1 0 Bit symbol XTSEL - - - - - - XTEN Read/Write R/W R/W After Reset 0 - - - - - - 0 Function Type of low frequency oscillator(fs) 0: Crystal 1: CR Low Frequency oscillator (fs) 0:Stop 1:Oscillation Stop

1 Oscillation

Note1: Please consider the stability-time for the oscillator. Note2: If it released from STOP mode, RTCFC register will be initiallized without a RESET input. Therefore, it is necessary to set up RTCFC register again after releaseing from STOP mode. Figure 3.16.2 Timer for Real Time Clock Function Register Example of register setting: LD (RTCFC),01h ; L-OSC start : ; (Wait for the stability-time) LD (RTCCR),03h ; Run at 2 13/fs RTCCR (118H) Counting operation Interrupt generation cycle (fs = 32.768 kHz) RTCFC (119H) Low frequency oscillator (fs=32.768 kHz)

3.16.3 CR oscillation

RTC can also work by using CR oscillator within. And oscillation type is controlled by the RTCFC. If XTSEL bit is set, CR oscillation is available. And when CR oscillation is used in the application, it is necessary to supplement external resistor and capacitor to XT1, XT2 pins. A shows CR oscillation frequency related to the combination of resistor and capacitor, provided that measurement environment is the typical condition described below. XT2 XT1 Low Frequency OSC R C TMP92CD54I Figure 3.16.3 A external circuit for CR oscillation (Note) Please adjust the value R and C for the application set. For example, we confirmed as follows, 1) R = 40kOhm and C = 470pF 2) R = 82kOhm and C = 220pF at condition of 32.768kHz and room temperature.

I 2006-01-27 92CD54I-279 TMP92CD54I

3.17 Voltage Regulator

3V output regulator for the internal logic power supply is installed in TMP92CD54I. The power supply is supplied to internal logic by connecting each DVCC3 terminal with regulator output terminal REGOUT. This regulator can control use/nonuse with the terminal REGEN. Table3.17.1 REGOUT output by REGEN setting REGEN input REGOUT output ”H” 3V output for internal logic ”OPEN” Note) 3V output for internal logic ”L” 0V output (Do not connect GND) Note) As for REGEN, use with OPEN is also possible because of an internal pull-up. When the regulator is not used, it is necessary to supply the power supply to internal logic separately.

3.17.1 Block diagram

Diagram 3.17.1 Regulator block

3.17.2 External connecting

For the oscillation prevention of the output voltage, connect stabilization capacitor (Cs) with the place between REGOUT and DVSS as near the terminal as possible. It is necessary to add resistance (ESR) to Cs serially according to the substrate capacity as shown in Figure 3.17.2. Because the change in internal resistance by the temperature might become the destabilizing factor of the regulator output about the selection of the capacitor, we will recommend the use of the capacitor with a good temperature characteristic. Moreover, recommend bypass capacitor (Cb) to be connected as a noise tolerance improvement of the REGOUT output between DVCC3-DVSS. PASS Tr BGR REGOUT FEEDBACK LOOP DVCC5 REGEN DVSS

I 2006-01-27 92CD54I-280 TMP92CD54I diagram 3.17.2 Regulator connection

3.17.3 Directions

・ Application This regulator is designed for TMP92CD54I. Do not connect the output from REGOUT except the terminal DVCC3 of TMP92CD54I. ・ Timing of when power supply is turned on and REGEN input signal When the power supply is turning on, keep the REGEN terminal OPEN or input the enable signal (H level) to the terminal REGEN after at least 1us passes from the power supply turning on. ・ The number of wires of Cs, Cb and ESR Depending on modular composition, its stray capacitance and parasitic capacitance might influence the regulator characteristic. Investigating the characteristic about the static characteristic and the transient characteristic along actual use conditions, the number of wires should be decided according to the margin of Cin, Cs, Cb and ESR. TMP92CD54I Cin REGEN REGOUT DVCC5 DVSS DVCC3 Cs ESR Cb OPEN VDD5 REGEN 90% 90% 1us min

1. Electrical Characteristics

4.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Power Supply Voltage VCC5 -0.5 to 6.0 V Input Voltage VIN -0.5 to VCC5+0.5 V Output Current(total) ΣIOL 100 mA Output Current(total) ΣIOH -100 mA Power Dissipation(Ta=85degree C) PD 600 mW Soldering Temperature(10s) TSOLDER 260 degree C Storage Temperature TSTG -65 to 150 degree C Operation Temperature TOPR -40 to 85 degree C Note: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products that include this device, ensure that no absolute maximum rating value will ever be exceeded.

4.2 DC Electrical Characteristics

Vcc5 =4.5V to 5.25V / fc = 16 to 20MHz / Ta = -40 to 85 degree C Parameter Symbol Condition Min Max Unit Supply Voltage VCC5 4.5 5.25 V Input Low Voltage P00 to P07(D0 to 7) PG0 to PG7 PL0 to PL3 V IL0 -0.3 0.8 V Input Low Voltage P00 to P07(PORT) P40 to P47 VIL1 -0.3 0.3*VCC5 V Input Low Voltage INT0 N M I R E S E T P70, P71, P73 to P75 PC0 to PC5 PD0 to PD7 PF0 to PF7 PM0 to PM4 V IL2 -0.3 0.25*VCC5 V P72, PN0 to PN6 VIL6 -0.3 0.3*VCC5 V Input Low Voltage AM0 to AM1 TEST0 to TEST1 VIL3 -0.3 0.3 V Input Low Voltage X1, XT1 (Crystal) VIL4 * Vcc3 = 3.3V -0.3 0.2*VCC3 V Input Low Voltage XT1 (CR) VIL5 * Vcc3 = 3.3V -0.3 0.2*VCC3 V Input High Voltage P00 to P07(D0 to 7) PG0 to PG7 PL0 to PL3 V IH0 2.2 VCC5+0.3 V Input High Voltage P00 to P07 P40 to P47 VIH1 0.7*VCC5 VCC5+0.3 V Input High Voltage INT0 N M I R E S E T P70, P71, P73 to P75 PC0 to PC5 PD0 to PD7 PF0 to PF7 PM0 to PM4 V IH2 0.75*VCC5 VCC5+0.3 V P72, PN0 to PN6 VIH6 0.7*VCC5 VCC5+0.3 V Input High Voltage AM0 to AM1 TEST0 to TEST1 VIH3 VCC5-0.3 VCC5+0.3 V Input High Voltage X1, XT1 (Crystal) VIH4 * Vcc3 = 3.3V 0.8*VCC3 VCC3+0.3 V Input High Voltage XT1 (CR) VIH5 * Vcc3 = 3.3V 0.7*VCC3 VCC3+0.3 V

Parameter Symbol Condition Min Max Unit Output Low Voltage VOL I OL = 3.0mA 0.4 V VOH0 I OH = -400uA 2.4 VOH1 I OH = -100uA 0.75*VCC5 VOH2 I OH = -20uA 0.9*VCC5 Output High Voltage VOHn I OH = -200uA, PF6(TX) pin 0.82*VCC5 V Input Leakage Current ILI 0.0 ≦ Vin ≦ VCC5 0.02(typ.) +/- 5 uA Output Leakage Current ILO 0.2 ≦ Vin ≦ VCC5-0.2 0.05(typ.) +/- 10 uA Operating Current (Single Chip)* ICC5 V CC5=5.25V , X1=10MHz(Internal 20MHz) 70(typ) 100 mA ICC5IDLE2 IDLE2 Mode VCC5=5.25V, X1=10MHz(Internal 20MHz) 9 0 ICC5IDLE1 IDLE1 Mode VCC5=5.25V, X1=10MHz(Internal 20MHz) 30 mA ICC5IDLE3 IDLE3 Mode VCC5=5.25V, Ta = -40 to 85 degree C VCC5=5.25V, Ta = -10 to 55 degree C 220 140 uA Operating Current (Stand-by) ICC5STOP STOP Mode VCC5=5.25V, Ta = -40 to 85 degree C VCC5=5.25V, Ta = -10 to 55 degree C 200 120 uA Stand-by Voltage VSTB5 VCC3 < VCC5 , VIH1<VCC5 , VIH2<VCC5 , VIH3<VCC5 3.0 5.25 V RRST RESET RCLK CLK Pull-up Resistor RREGEN REGEN 60 220 K ohm Schmitt Width VTH INT0, NMI, RESET, P70 to P75, PC0 to PC5, PD0 to PD7, PF0 to PF7, PM0 to PM4, PN0 to PN6 0.4 1.0(typ.) V *: On condition that external bus don’t operate

4.3 AC Characteristics

Read cycle VCC5=4.5 to 5.25V±5%, TA=--40 to 85 degree C No. Parameter Symbol Min Max ＠20MHz ＠16MHz Unit

1 OSC period (X1/X2) t OSC 100 125 100 125 ns

2 System Clock period (=T) t CYC 50 62.5 50 62.5 ns 3 CLK Low Width t CL 0.5×T-15 10 16 ns 4 CLK High Width t CH 0.5×T-15 10 16 ns 5-1 A0 to A23 Valid → D0 to D7 Input ＠0WAIT tAD 2.0×T-50 50 75 ns 5-2 A0 to A23 Valid → D0 to D7 Input ＠1WAIT tAD3 3.0×T-50 100 138 ns 6-1 R D F a l l → D0 to D7 Input ＠0WAIT tRD 1.5×T-45 30 49 ns 6-2 RD Fall → D0 to D7 Input ＠1WAIT t RD3 2.5 ×T-45 80 111 ns 7-1 R D L o w Wi d t h ＠0WAIT tRR 1.5×T-20 55 74 ns 7-2 R D L o w Wi d t h ＠1WAIT tRR3 2.5×T-20 105 136 ns 8 A0 to A23 Valid → RD Fall tAR 0.5×T-20 5 11 ns 9 R D F a l l → CLK Fall tRK 0.5×T-20 5 11 ns

10 A0 to A23 Valid → D0 to D7 Hold tHA 0 0 0 ns

11 R D R i s e → D0 to D7 Hold tHR 0 0 0 ns

12 A0 to A23 Valid → PORT Input tAPR 2.0×T-120 -20 5 ns 13 A0 to A23 Valid → PORT Hold tAPH 2.0×T 100 125 ns

14 WAIT Set-up Time t TK 15 15 15 ns

15 WAIT Hold Time t KT 5 5 5 ns

Write cycle VCC5=5.0V±5%, TA=--40 to 85 degree C No. Parameter Symbol Min Max ＠20MHz ＠16MHz Unit 2 System Clock period (=T) t CYC 50 62.5 50 62.5 ns 3 CLK Low Width t CL 0.5×T-15 10 16 ns 4 CLK High Width t CH 0.5×T-15 10 16 ns 5-1 D0 to D7 Valid → WR R i s e ＠0WAIT tDW 1.25×T-35 28 43 ns 5-2 D0 to D7 Valid → WR R i s e ＠1WAIT tDW3 2.25×T-35 78 106 ns 6-1 WR L o w Wi d t h ＠0WAIT tWW 1.25×T-30 33 48 ns 6-2 WR L o w Wi d t h ＠1WAIT tWW3 2.25×T-30 83 111 ns 7 A0 to A23 Valid → WR Fall tAW 0.5×T-20 5 11 ns 8 WR F a l l → CLK Fall t WK 0.5 ×T-20 5 11 ns 9 WR F a l l → A0 to A23 Hold tWA 0.25×T-5 8 11 ns 10 WR F a l l → D0 to D7 Hold tWD 0.25×T-5 8 11 ns 11 A0 to A23 Valid → PORT Output tAPW 2.0×T+70 170 195 ns

12 WAIT Set-up Time t TK 15 15 15 ns

13 WAIT Hold Time t KT 5 5 5 ns

14 R D R i s e → D0 to D7 Output tRDO 1.25×T-35 20 26 ns AC Condition ・Output : D0 to D7, A0 to A7, A8 to A15, A16 to A23, RD, WR High 2.0V, Low 0.8V, CL=50pF Others High 2.0V, Low 0.8V, CL=50pF ・Input : D0 to D7 High 2.4V, Low 0.45V, CL=50pF Others H i g h 0 . 8 ×VCC5, Low 0.2×VCC5

(1) Read cycle (0 wait) Note : The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example . CLK (fc) WAIT A0 to A23 CS RD D0 to D7 Port input tOSC tCYC tCL tCH tTK tKT tAD tAR tRK tRR tRD Data Input Port Input tAPR tAPH tHR tHA

(2) Write cycle (0 wait) Note : The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. CLK (fc) WAIT A0 to A23 CS WR D0 to D7 Port output tOSC tCYC tCL tCH tTK tKT tAW tWK tWW tDW Data Output tAPW tWA RD tWD tRDO

(3) Read cycle (1 wait) (4) Write cycle (1 wait) CL K (fc) WAIT A0 to A23 CS RD D0 to D7 tAD3 tRR3 tRD3 Data Input CLK (fc) WAIT A0 to A23 CS WR D0 to D7 tWW3 tDW3 Data Output RD tRDO

4.4 AD Conversion Characteristics

Symbol Parameter Min Typ MAX Unit VREFH Analog reference voltage(＋) VCC5-0.2 VCC5 VCC5 VREFL Analog reference voltage(－) VSS5 VSS5 VSS5 AVCC AD Converter Power Supply Voltage VCC5-0.2 VCC5 VCC5 AVSS AD Converter Ground VSS5 VSS5 VSS5 AVIN Analog Input Voltage VREFL VREFH V Analog Current for analog reference voltage <VREFON>=1 0.8 1.2 mA IREF <VREFON>=0 0.02 5 uA ET Total error (excluding quantize error) ±3.0 LSB Note) “LSB” is the UNIT which means the resolution of AD CONVERTER. (+/- 3 LSB = 3 * VCC/1024 = +/-15mV)

4.5 Event Counter (TI0, TI4, TI8, TI9, TIA, TIB)

Variable 20MHz 16MHz Parameter Symbol Min Max Min Max Min Max Unit Clock Cycle tVCK 8T+100 500 600 ns Clock Low Width tVCKL 4T+40 240 290 ns Clock High Width tVCKH 4T+40 240 290 ns

4.6 Serial Channel Timing

(1) SCLK Input mode (I/O Interface mode) Variable 20MHz 16MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK Cycle tSCY 16T 0.8 1.0 us Output Data → SCLK Rise tOSS tSCY/2-4T -110 90 140 SCLK Rise → Output Data Hold tOHS t SCY/2+2T 500 625 SCLK Rise → Input Data Hold tHSR 3T+10 160 197.5 SCLK Rise → Input Data Valid tSRD tSCY 800 1000 ns (2) SCLK Output mode (I/O Interface mode) Variable 20MHz 16MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK Cycle (programmable) tSCY 16T 8192T 0.8 409.6 1.0 512 us Output Data → SCLK Rise tOSS t SCY/2-40 360 460 SCLK Rise → Output Data Hold tOHS t SCY/2-40 360 460 SCLK Rise → Input Data Hold tHSR 0 0 0 SCLK Rise → Input Data Valid tSRD tSCY/2-T -180 570 757.5 ns

(3) SCLK Input mode (UART mode) (Preliminary) Variable 20MHz 16MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK Cycle TSCY 4T + 20 220 270 SCLK Low level Pulse width TSCYL 2T + 5 105 130 SCLK High level Pulse width TSCYH 2T + 5 105 130 ns

4.7 Interrupt Operation

Variable 20MHz 16MHz Parameter Symbol Min Max Min Max Min Max Unit NMI,INT0 Low Width TINTAL 4T 200 250 NMI,INT0 High Width TINTAH 4T 200 250 WUINT0 to WUINT7, INT1 to INT7 Low Width TINTBL 8T+100 500 600 WUINT0 to WUINT7, INT1 to INT7 High Width TINTBH 8T+100 500 600 ns SCL OUTPUT DATA TxD tHSR VALIDVALID tSRD tOHS tSCY tOSS INPUT DATA RxD

4.8 Serial bus interface

1 SCL clock frequency ｆｓｃｌ KHz 0 400 0 100 0 fc/(2n+8)

Hold time (repeated) START condition. After this period, the first clock pulse is generated.ｔHD；STA ns 650 - 4500 - 2 n-1/fc -

3 LOW period of the SCL clock ｔLOW ns 1300 - 4700 - 2 n-1/fc -

4 HIGH period of the SCL clock ｔHIGH ns 600 - 4000 - (2 n-1+8)/fc -

5 Set-up time for a repeated START condition ｔSU；STA ns

Data hold time: for CBUS compatible masters for I2C-bus devicesｔHD；DAT ns 0 900 0 3450 0 6/fc

7 Data set-up time ｔSU；DAT ns 100 - 250 - (2 n-1-6)/fc -

(The case in the first bit after transfer ) ｔSU；1stDAT ↑ ↑↑↑↑ (2n-1-12)/fc -

8 Rise time of both SDA and ACL signals (*1) ｔr ns -

(receive) - 1000 (receive) -

9 Fall time of both SDA and ACL signals ｔｆ ns - 300 - 300 -

10 Set-up time for STOP condition ｔSU；STO ns 950 - 4200 - (2n-1+12)/fc -

11 Bus free time between a STOP and START

condition ｔBUF ns

12 Capacitive load for each cus line Cb pF 400 400 400

Noise margin at the LOW level for each connected device (including hysteresis) VnL v 0.2VDD5 -0 . 2 V DD5 -0 . 2 V DD5 - Noise margin at the HIGH level for each connected device (including hysteresis) VnH v 0.2VDD5 -0 . 2 V DD5 - 0.2VDD5 - Pulse width of spikes which must be suppressed by the input filter tsp ns 0 50 n/a n/a n/a n/a Note 1 All values referred to VIHmin and VILmax levels. (fc=２０ＭＨｚ) No PARAMETER SYMBOL UNIT (fc=System clock) by software by software ４００KHｚ 100KHz Existing rate by software by software by software by software SDA SCL LOW ｔ f ｔ HD:STA ｔ HD:DAT ｔ r ｔ SU:DATｔ f ｔ HIGH ｔ SU:STAｔ HD:STAｔ SP ｔ SU:STO ｔ r ｔ BUF ｔ S Sr P S S:S t a r tP: S t o p Sr : ReStart SU:1stDAT ｔ I2BUS CLK AC SPEC : Tr (Transmitter selection ) Vih SCLK T-Low Tr T-High SCK(1111) :100KHz 100/fc 100/fc SCK(1000) :400KHz 32/fc 18/fc Tr 0 to 2/fc 2/fc to 4/fc 4/fc to 6/fc 6/fc to 8/fc 8/fc to 10/fc …. SCK(0001 - 0110) T-R 0 4/fc 8/fc …. SCK(1111) :100KHz T-R 0 4/fc 8/fc …. SCK(1000) :400KHz T-R 0 2/fc 4/fc 6/fc 8/fc …. T-period = T-Low + T-R + T-High Example: in the case of fc=20MHz, SCK3,2,1,0=(0001), Tr=200ns 1) Tr=200ns so T-R=4/fc 2) T-period = 2*(n-1)/fc + 4/fc + (2*(n-1)+8)/fc =76/fc =3.8us *1)

4.9 Serial Expansion Interface

Variable 20MHz Symbol Parameter Min Max Min Max Unit t SECLK SECLK Cycle 5T 40T 250 2000 ns t LEAD SS fall Æ SECLK 4T 200 ns t LAG SECLK Æ SS rise 4T 200 ns t SCKH SECLK High Pulse Width t SECLK /2-9 116 ns t SCKL SECLK Low Pulse Width t SECLK /2-9 116 ns t SU Input Data Set-up t SECLK /4-10 52 ns t H Input Data Hold t SECLK /4 62 ns t V Output Data Valid t SECLK /4 62 ns t HO Output Data Hold 0 0 ns a) SEI Master (CPHA=0) SS SECLK SECLK M I S O M O S I b) SEI Master (CPHA=1) SS SECLK SECLK M I S O M O S I LSB Input bit 6 to 1 MSB Input LSB Output bit 6 to 1 MSB Output tV tHO tHtSU tSECLK LSB Output bit6 to 1 MSB Output LSB Input bit6 to 1 MSB Input tV tHO tSECLK tSCKH tSCKL tHtSU

c) SEI Slave (CPHA=0) SS S E C L K SECLK M I S O MOSI d) SEI Slave (CPHA=1) SS SECLK SECLK M I S O M O S I

4.10 Controller Area Network (CAN)

Variable 20MHz Symbol Parameter Min Max Min Max Unit tcclk CAN Clock period 2T 100 ns tp Tx edge ÆRx Input 2tcclk-20 180 ns LSB Input bit 6 to 1 MSB Input LSB Output bit 6 to 1 MSB Output tH tHO tV tHO tSCKL tSCKH tLAG tLEAD LSB Input bit 6 to 1 MSB Input LSB Output bit 6 to 1 MSB Output tHtSU tV tSU tLEAD tLAG tSCKL tSCKH tp Tx tp Rx

4.11 Voltage regulator

Voltage Regurator Vcc5 =4.5V to 5.25V / fc = 16 to 20MHz / Ta = -40 to 85 degree C / Iload =10uA Parameter Symbol Condition Min. Typ. Max. Unit. Output Voltage REGOUT 3.0 ― 3.6 V Output Current Iro Vin-REGOUT=1.0V 0 ― 150 mA Iq Iro≦10 uA 30 50 100 μA Iq1 10 uA＜Iro＜100mA (Ta=25 ℃) 15 250 800 μA Quiescent Current Iop Iro=150mA 6 8 10 mA Standby Current Is REGEN=0 (Regulator Only) ― 0.1 0.2 μA 0.5[Ohm] ≦ESR≦5.0[Ohm] Parameter Symbol Condition Min. Typ. Max. Unit. Stabilization capactor Cs Cb=10uF, ESR=4.7Ω 0.1 ― 10 μF Bypass capactor Cb Cs=10uF, ESR=4.7Ω (Cs>=Cb) 0.1 ― 10 μF Input capactor Cin (Note) Cs=10uF, ESR=4.7Ω 4.7 ― 22 μF Equivalent Series Resistor ESR Cs=10uF Cb=0.1uF 0.5 ― 5 Ω 0.5[Ohm] ≦ESR≦50[Ohm] Parameter Symbol Condition Min. Typ. Max. Unit. Stabilization capactor Cs Cb=0.6uF, ESR=47Ω 0.1 ― 10 μF Bypass capactor Cb Cs=10uF, ESR=47Ω (Cs>=Cb) 0.6 ― 10 μF Input capactor Cin (Note) Cs=10uF, ESR=47Ω 4.7 ― 22 μF Equivalent Series Resistor ESR Cs=10uF Cb=0.6uF 0.5 ― 50 Ω 0.5[Ohm] ≦ESR≦100[Ohm] Parameter Symbol Condition Min. Typ. Max. Unit. Stabilization capactor Cs Cb=1.0uF, ESR=100Ω 0.1 ― 10 μF Bypass capactor Cb Cs=10uF, ESR=100Ω (Cs>=Cb) 1.0 ― 10 μF Input capactor Cin (Note) Cs=10uF, ESR=100Ω 4.7 ― 22 μF Equivalent Series Resistor ESR Cs=10uF Cb=1.0uF 0.5 ― 100 Ω Note: Recommend Tantalum Capacitor. TMP92CD54I DVCC5 REGOU T REGENDVSS DVCC3 OPEN Cin Cs ESR Cb

1. Table of special function registers (SFRs) (SFR ; Special Function Register) The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 1024 byte addresses from 000000H to 0003FFH. (1) I/O port (2) 8-bit Timer control (3) 16-bit Timer control (4) Serial Channel control (5) Serial Expansion Interface control (6) Interrupt control (7) DMA controller (8) Control register (9) A/D converter control (10)Memory controller (11)Serial Bus Interface control (12)CAN control (13)RTC control Configuration of the table Symbol Name Address 7 6 5 4 3 2 1 0 → bit Symbol → Read/Write → Initial value after reset → Remarks Explanations of symbols R / W ：Either read or write is possible R ：Only read is possible W ：Only write is possible no RMW：Prohibit Read Modify Write (Prohibit RES / SET / TSET / CHG / STCF / ANDCF / ORCF / XORCF etc.)

Table 6 I/O register address map [1] Port : ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0000H (Reserved) P0CR P0FC 0010H 11H 12H 13H (Reserved) P4CR P4FC 0020H 21H 22H 23H (Reserved) (Reserved) (Reserved) (Reserved) 0030H 31H 32H 33H PC (Reserved) PCCR PCFC (Reserved) (Reserved) (Reserved) (Reserved) 14H 15H 16H 17H (Reserved) (Reserved) (Reserved) (Reserved) 24H 25H 26H 27H (Reserved) (Reserved) (Reserved) (Reserved) 34H 35H 36H 37H PD (Reserved) PDCR PDFC AH BH (Reserved) (Reserved) (Reserved) (Reserved) 18H 19H 1AH 1BH (Reserved) (Reserved) (Reserved) (Reserved) 28H 29H 2AH 2BH (Reserved) (Reserved) (Reserved) (Reserved) 38H 39H 3AH 3BH (Reserved) (Reserved) (Reserved) (Reserved) CH DH EH FH (Reserved) (Reserved) (Reserved) (Reserved) 1CH 1DH 1EH 1FH (Reserved) P7CR P7FC 2CH 2DH 2EH 2FH (Reserved) (Reserved) (Reserved) (Reserved) 3CH 3DH 3EH 3FH PF (Reserved) PFCR PFFC ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0040H 41H 42H 43H PG (Reserved) (Reserved) (Reserved) 0050H 51H 52H 53H (Reserved) (Reserved) (Reserved) (Reserved) 0060H 61H 62H 63H SECR0 SESR0 SEDR0 (Reserved) 0070H 71H 72H 73H (Reserved) (Reserved) (Reserved) (Reserved) 44H 45H 46H 47H (Reserved) (Reserved) (Reserved) (Reserved) 54H 55H 56H 57H PL (Reserved) (Reserved) (Reserved) 64H 65H 66H 67H (Reserved) (Reserved) (Reserved) (Reserved) 74H 75H 76H 77H (Reserved) (Reserved) (Reserved) (Reserved) 48H 49H 4AH 4BH (Reserved) (Reserved) (Reserved) (Reserved) 58H 59H 5AH 5BH PM PMODE PMCR PMFC 68H 69H 6AH 6BH (Reserved) (Reserved) (Reserved) (Reserved) 78H 79H 7AH 7BH (Reserved) (Reserved) (Reserved) (Reserved) 4CH 4DH 4EH 4FH (Reserved) (Reserved) (Reserved) (Reserved) 5CH 5DH 5EH 5FH PN PNODE PNCR PNFC 6CH 6DH 6EH 6FH (Reserved) (Reserved) (Reserved) (Reserved) 7CH 7DH 7EH 7FH (Reserved) (Reserved) (Reserved) (Reserved) Note: Do not access the without allocated names. [2] SEI :

[3] 8-bit Timer : ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0080H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH TRUN01 (Reserved) TREG0 TREG1 TMOD01 TFFCR1 (Reserved) (Reserved) TRUN23 (Reserved) TREG2 TREG3 TMOD23 TFFCR3 (Reserved) (Reserved) 0090H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH TRUN45 (Reserved) TREG4 TREG5 TMOD45 TFFCR5 (Reserved) (Reserved) TRUN67 (Reserved) TREG6 TREG7 TMOD67 TFFCR7 (Reserved) (Reserved) 00A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH TRUN8 (Reserved) TMOD8 TFFCR8 (Reserved) (Reserved) (Reserved) (Reserved) TREG8L TREG8H TREG9L TREG9H CAP8L CAP8H CAP9L CAP9H 00B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH TRUNA (Reserved) TMODA TFFCRA (Reserved) (Reserved) (Reserved) (Reserved) TREGAL TREGAH TREGBL TREGBH CAPAL CAPAH CAPBL CAPBH [5] SIO : ADDRESS NAME 00C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH SC0BUF SC0CR SC0MOD0 BR0CR BR0ADD SC0MOD1 (Reserved) (Reserved) SC1BUF SC1CR SC1MOD0 BR1CR BR1ADD SC1MOD1 (Reserved) (Reserved) [4] 16-bit Timer :

[6] INTC : ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 00D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH INTE12 INTE34 INTE56 INTE7 INTET01 INTET23 INTET45 INTET67 INTET89 INTETAB INTETO8A INTES0 INTES1 INTECRT INTECG INTESEE0 00E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH INTESED0 INTERTC INTESB2 INTESB0 INTESB1 INTMK0 INTMK1 INTMK2 INTMK3 INTMK4 INTMK5 (Reserved) WUPFLAG WUPMOD WUPEDGE WUPMASK 00F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH INTE0AD INTETC01 INTETC23 INTETC45 INTETC67 (Reserved) IIMC INTNMWDT INTCLR (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0100H 101H 102H 103H 104H 105H 106H 107H 108H 109H 10AH 10BH 10CH 10DH 10EH 10FH DMA0V DMA1V DMA2V DMA3V DMA4V DMA5V DMA6V DMA7V DMAB DMAR CLKMOD (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) [7] WDT, RTC : [8] 10-bit ADC : ADDRESS NAME ADDRESS NAME ADDRESS NAME 0110H 111H 112H 113H 114H 115H 116H 117H 118H 119H 11AH 11BH 11CH 11DH 11EH 11FH WDMOD WDCR (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) RTCCR RTCFC (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0120H 121H 122H 123H 124H 125H 126H 127H 128H 129H 12AH 12BH 12CH 12DH 12EH 12FH ADREG0L ADREG0H ADREG1L ADREG1H ADREG2L ADREG2H ADREG3L ADREG3H ADREG4L ADREG4H ADREG5L ADREG5H ADREG6L ADREG6H ADREG7L ADREG7H 0130H 131H 132H 133H 134H 135H 136H 137H 138H 139H 13AH 13BH 13CH 13DH 13EH 13FH ADREG8L ADREG8H ADREG9L ADREG9H ADREGAL ADREGAH ADREGBL ADREGBH ADMOD0 ADMOD1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)

[9]MEMC : ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0140H 1 41 H 1 42 H 1 43 H 1 44 H 1 45 H 1 46 H 1 47 H 1 48 H 1 49 H 14AH 14BH 14CH 14DH 14E H 14 FH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) BCSL BCSH MAMR MSAR (Reserved) (Reserved) (Reserved) (Reserved) 0150H 151H 152H 153H 154H 155H 156H 157H 158H 159H 15 AH 15 BH 15CH 15DH 15EH 15FH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0160H 161H 162H 163H 164H 165H 166H 167H 168H 169H 16AH 16BH 16CH 16DH 16E H 16FH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) FSWE ( Note ) (Reserved) RAMCR FLSR ( Note ) (Reserved) 0170H 171H 172H 173H 174H 175H 176H 177H 178H 179H 17AH 17BH 17CH 17DH 17EH 17FH SBI0CR1 SBI0DBR I2C0AR SBI0CR2/SBI0SR SBI0BR0 SBI0BR1 (Reserved) (Reserved) SBI1CR1 SBI1DBR I2C1AR SBI1CR2/SBI1SR SBI1BR0 SBI1BR1 (Reserved) (Reserved) (Note) Only TMP92FD54AI. ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0180H 1 81 H 1 82 H 1 83 H 1 84 H 1 85 H 1 86 H 1 87 H 1 88 H 1 89 H 18AH 18BH 18CH 18DH 18E H 18 FH SBI2CR1 SBI2DBR I2C2AR SBI2CR2/SBI2SR SBI2BR0 SBI2BR1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0190H 191H 192H 193H 194H 195H 196H 197H 198H 199H 19 AH 19 BH 19CH 19DH 19EH 19FH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 01A0H 1A1H 1A2H 1A3H 1A4H 1A5H 1A6H 1A7H 1A8H 1A9H 1AAH 1ABH 1ACH 1ADH 1AEH 1AFH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 01B0H 1B1H 1B2H 1B3H 1B4H 1B5H 1B6H 1B7H 1B8H 1B9H 1BAH 1BBH 1BCH 1BDH 1BEH 1BFH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) [10] SBI :

ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 01C0H 1C1H 1C2H 1C3H 1C4H 1C5H 1C6H 1C7H 1C8H 1C9H 1CAH 1CBH 1CCH 1CDH 1CEH 1CFH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 01D0H 1D1H 1D2H 1D3H 1D4H 1D5H 1D6H 1D7H 1D8H 1D9H 1DAH 1DBH 1DCH 1DDH 1DEH 1DFH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 01E0H 1E1H 1E2H 1E3H 1E4H 1E5H 1E6H 1E7H 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 01F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) [11] CAN: ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0200H 201H 202H 203H 204H 205H 206H 207H 208H 209H 20AH 20BH 20CH 20DH 20E H 20 FH MB0MI0L MB0MI0H MB0MI1L MB0MI1H MB0MCFL MB0MCFH MB0D0 MB0D1 MB0D2 MB0D3 MB0D4 MB0D5 MB0D6 MB0D7 MB0TSVL MB0TSVH 0210H 211H 212H 213H 214H 215H 216H 217H 218H 219H 21 AH 21 BH 21CH 21DH 21EH 21FH MB1MI0L MB1MI0H MB1MI1L MB1MI1H MB1MCFL MB1MCFH MB1D0 MB1D1 MB1D2 MB1D3 MB1D4 MB1D5 MB1D6 MB1D7 MB1TSVL MB1TSVH 0220H 22 1H 22 2H 22 3H 224H 22 5H 22 6H 22 7H 22 8H 22 9H 22AH 22BH 22CH 22DH 22E H 22FH MB2MI0L MB2MI0H MB2MI1L MB2MI1H MB2MCFL MB2MCFH MB2D0 MB2D1 MB2D2 MB2D3 MB2D4 MB2D5 MB2D6 MB2D7 MB2TSVL MB2TSVH 0230H 231H 232H 233H 234H 235H 236H 237H 238H 239H 23AH 23BH 23CH 23DH 23EH 23FH MB3MI0L MB3MI0H MB3MI1L MB3MI1H MB3MCFL MB3MCFH MB3D0 MB3D1 MB3D2 MB3D3 MB3D4 MB3D5 MB3D6 MB3D7 MB3TSVL MB3TSVH

[11] CAN: ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0240H 241H 242H 243H 244H 245H 246H 247H 248H 249H 24AH 24BH 24CH 24DH 24E H 24 FH MB4MI0L MB4MI0H MB4MI1L MB4MI1H MB4MCFL MB4MCFH MB4D0 MB4D1 MB4D2 MB4D3 MB4D4 MB4D5 MB4D6 MB4D7 MB4TSVL MB4TSVH 0250H 251H 252H 253H 254H 255H 256H 257H 258H 259H 25 AH 25 BH 25CH 25DH 25EH 25FH MB5MI0L MB5MI0H MB5MI1L MB5MI1H MB5MCFL MB5MCFH MB5D0 MB5D1 MB5D2 MB5D3 MB5D4 MB5D5 MB5D6 MB5D7 MB5TSVL MB5TSVH 0260H 26 1H 26 2H 26 3H 264H 26 5H 26 6H 26 7H 26 8H 26 9H 26AH 26BH 26CH 26DH 26E H 26FH MB6MI0L MB6MI0H MB6MI1L MB6MI1H MB6MCFL MB6MCFH MB6D0 MB6D1 MB6D2 MB6D3 MB6D4 MB6D5 MB6D6 MB6D7 MB6TSVL MB6TSVH 0270H 271H 272H 273H 274H 275H 276H 277H 278H 279H 27AH 27BH 27CH 27DH 27EH 27FH MB7MI0L MB7MI0H MB7MI1L MB7MI1H MB7MCFL MB7MCFH MB7D0 MB7D1 MB7D2 MB7D3 MB7D4 MB7D5 MB7D6 MB7D7 MB7TSVL MB7TSVH ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0280H 281H 282H 283H 284H 285H 286H 287H 288H 289H 28AH 28BH 28CH 28DH 28E H 28 FH MB8MI0L MB8MI0H MB8MI1L MB8MI1H MB8MCFL MB8MCFH MB8D0 MB8D1 MB8D2 MB8D3 MB8D4 MB8D5 MB8D6 MB8D7 MB8TSVL MB8TSVH 0290H 291H 292H 293H 294H 295H 296H 297H 298H 299H 29 AH 29 BH 29CH 29DH 29EH 29FH MB9MI0L MB9MI0H MB9MI1L MB9MI1H MB9MCFL MB9MCFH MB9D0 MB9D1 MB9D2 MB9D3 MB9D4 MB9D5 MB9D6 MB9D7 MB9TSVL MB9TSVH 02A0H 2A 1H 2A 2H 2A 3H 2A4H 2A 5H 2A 6H 2A 7H 2A 8H 2A 9H 2A AH 2A BH 2A CH 2A DH 2A E H 2AFH MB10MI0L MB10MI0H MB10MI1L MB10MI1H MB10MCFL MB10MCFH MB10D0 MB10D1 MB10D2 MB10D3 MB10D4 MB10D5 MB10D6 MB10D7 MB10TSVL MB10TSVH

02 B0H

2 B1H

2 B2H

2 B3H

2 B4H

2 B5H

2 B6H

2 B8H

2 B9H

[11] CAN: ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0 2C 0 H 2C1H 2C2H 2C3H 2C4H 2C5H 2C6H 2C7H 2C8H 2C9H 2CA H 2CBH 2CCH 2CDH 2CEH

2 C FH

2 DAH

2 DBH

2 DCH

2 DD H

02 F0H

2 F1H

2 F2H

2 F3H

2 F4H

2 F5H

2 F6H

2 F7H

2 F8H

2 F9H

ADDRESS NAME ADDRESS NAME ADDRESS NAME ADDRESS NAME 0300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30E H 30 FH MCL MCH MDL MDH TRSL TRSH TRRL TRRH TAL TAH AAL AAH RMPL RMPH RMLL RMLH 0310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31 AH 31 BH 31CH 31DH 31EH 31FH LAM0L LAM0H LAM1L LAM1H GAM0L GAM0H GAM1L GAM1H MCRL MCRH GSRL GSRH BCR1L BCR1H BCR2L BCR2H 0320H 32 1H 32 2H 32 3H 324H 32 5H 32 6H 32 7H 32 8H 32 9H 32AH 32BH 32CH 32DH 32E H 32FH GIFL GIFH GIML GIMH MBTIFL MBTIFH MBRIFL MBRIFH MBIML MBIMH CDRL CDRH RFPL RFPH CECL CECH 0330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH TSPL TSPH TSCL TSCH (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ADDRESS NAME 340H 3FFH (Reser ved)

(1) I/O Port Port0 Symbol Name ADDRESS 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 R/W 0 0 0 0 0 0 0 0 P0 PORT0 Register 00H Input/Output P07C P06C P05C P04C P03C P02C P01C P00C W 0 0 0 0 0 0 0 0 P0CR PORT0 Control Register 02H (no RMW) 0:Input 1:Output - - - - - - - P0F W PORT0 Function Register 03H (no RMW) 0:PORT 1:Data Bus(D7 to D0) Port4 Symbol Name ADDRESS 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 R/W 0 0 0 0 0 0 0 0 P4 PORT4 Register 10H Input/Output P47C P46C P45C P44C P43C P42C P41C P40C W 0 0 0 0 0 0 0 0 P4CR PORT4 Control Register 12H (no RMW) 0:Input 1:Output P47F P46F P45F P44F P43F P42F P41F P40F W 0 0 0 0 0 0 0 0 P4FC PORT4 Function Register 13H (no RMW) 0:PORT 1:A7 0:PORT 1:A6 0:PORT 1:A5 0:PORT 1:A4 0:PORT 1:A3 0:PORT 1:A2 0:PORT 1:A1 0:PORT 1:A0 P4CR P4FC P47 P46 P45 P44 P43 P42 P41 P40 0 0 Input Port 1 0 Output Port 1 1 (Reserved) 0 1 A7 to A0

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - - P75 P74 P73 P72 P71 P70 R/W - - 0 1 1 1 1 1 P7 PORT7 Register 1CH Input/Output - - P75C P74C P73C P72C P71C P70C W - - 0 1 1 0 1 1 P7CR PORT7 Control Register 1EH (no RMW) 0:Input 1:Output - - P75F P74F P73F P72F P71F P70F W - - 0 0 0 0 0 0 P7FC PORT7 Function Register 1FH (no RMW) 0:PORT 1:WAIT 0:PORT 0:PORT 1:CS 0:PORT 1:SI2 SCL2 Note1 0:PORT 1:WR 0:PORT 1:RD Note1: P72 SCL2, clock input/output at I2C mode, can be open-drain output by setting 1 to PNODE<ODE72>. PortC Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - - PC5 PC4 PC3 PC2 PC1 PC0 R/W - - 0 0 0 0 0 0 PC PORTC Register 30H Input/Output - - PC5C PC4C PC3C PC2C PC1C PC0C W - - 0 0 0 0 0 0 PCCR PORTC Control Register 32H (no RMW) 0:Input 1:Output - - PC5F PC4F PC3F PC2F PC1F PC0F W - - 0 0 0 0 0 0 PCFC PORTC Function Register 33H (no RMW) 0:PORT INT4 1:TO7 0:PORT 1:TO5 0:PORT INT3 TI4 0:PORT INT2 1:TO3 0:PORT 1:TO1 0:PORT INT1 TI0

SYMBOL NAME Address 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 R/W 0 0 0 0 0 0 0 0 PD PORTD 34H Input/Output PD7C PD6C PD5C PD4C PD3C PD2C PD1C PD0C W 0 0 0 0 0 0 0 0 PDCR PORTD Control Register 36H (no RMW) 0:Input 1:Output PD7F PD6F PD5F PD4F PD3F PD2F PD1F PD0F W 0 0 0 0 0 0 0 0 PDFC PORTD Function Register 37H (no RMW) 0:PORT WUINT7 1:TOB A23 0:PORT WUINT6 1:TOA A22 0:PORT TIB WUINT5 1:A21 0:PORT INT7 TIA WUINT4 1:A20 0:PORT WUINT3 1:TO9 A19 0:PORT WUINT2 1:TO8 A18 0:PORT INT6 TI9 WUINT1 1:A17 0:PORT INT5 TI8 WUINT0 1:A16 PDCR PDFC PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 Input Port, WUINT7 Input Port, WUINT6 Input Port, TIB, WUINT5 Input Port, INT7, TIA, WUINT4 Input Port, WUINT3 Input Port, WUINT2 Input Port, INT6, TI9, WUINT1 Input Port, INT5, TI8, WUINT0 1 0 Output Port 1 1 TOB TOA TIB, WUINT5 TIA, INT7, WUINT4 TO9 TO8 TI9, INT6, WUINT1 TI8, INT5, WUINT0 0 1 A23 A22 A21 A20 A19 A18 A17 A16

SYMBOL NAME Address 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 R/W 0 0 0 0 0 0 0 0 PF PORTF 3CH Input/Output PF7C PF6C PF5C PF4C PF3C PF2C PF1C PF0C W 0 0 0 0 0 0 0 0 PFCR PORTF Control Register 3EH (no RMW) 0:Input 1:Output PF7F PF6F PF5F PF4F PF3F PF2F PF1F PF0F W 0 0 0 0 0 0 0 0 PFFC PORTF Function Register 3FH (no RMW) 0:PORT 1:RX 0:PORT 1:TX 0:PORT CTS1 1:SCLK1 0:PORT 1:RXD1 0:PORT 1:TXD1 0:PORT CTS0 1:SCLK0 0:PORT 1:RXD0 0:PORT 1:TXD0 PFCR PFFC PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 0 0 Input Port, RX Input Port Input Port, SCLK1 (Input), CTS1 Input Port, RXD1 Input Port Input Port, SCLK0 (Input), CTS0 Input Port, RXD0 Input Port 1 0 Output Port 1 1 RX TX SCLK1 (Output) RXD1 TXD1 SCLK0 (Output) RXD0 TXD0 0 1 RX TX Don’t use this setting RXD1 TXD1 (Open -Drain) Don’t use this setting RXD0 TXD0 (Open -Drain) PortG Symbol Name ADDRESS 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 R PG PORTG Register 40H Input PortL Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - - - - PL3 PL2 PL1 PL0 R PL PORTL Register 54H - - - - Input

SYMBOL NAME Address 7 6 5 4 3 2 1 0 - - - PM4 PM3 PM2 PM1 PM0 R / W - - - 0 0 0 0 0 PM PORTM 58H Input/Output - - - - ODEM3 ODEM2 ODEM1 - R/W - - - - 0 0 0 - PMODE PORTM Open Drain Enable Register 59H PM3 Output 0:CMOS 1:Open Drain PM2 Output 0:CMOS 1:Open Drain PM1 Output 0:CMOS 1:Open Drain - - - PM4C PM3C PM2C PM1C PM0C W - - - 0 0 0 0 0 PMCR PORTM Control Register 5AH (no RMW) 0:Input 1:Output - - - PM4F PM3F PM2F PM1F PM0F W - - - 0 0 0 0 0 PMFC PORTM Function Register 5BH (no RMW) 0:PORT 1:SCK2 0:PORT 1:SECLK A11 0:PORT 1:MISO A10 0:PORT 1:MOSI 0:PORT 1:SS PMCR PMFC - - - PM4 PM3 PM2 PM1 PM0 0 0 - - - Input Port, SCK2 (Input) Input Port Input Port Input Port Input Port, SS 1 0 - Output Port 1 1 - - - SCK2 (Output) SECLK MISO MOSI SS 0 1 - - - Don’t use this setting A11 A10 A9 A8

SYMBOL NAME Address 7 6 5 4 3 2 1 0 - PN6 PN5 PN4 PN3 PN2 PN1 PN0 R/W - 0 0 0 0 0 0 0 PN PORTN 5CH Input/Output ODE72 ODEN6 ODEN5 ODEN4 - ODEN2 ODEN1 - R/W R/W 0 0 0 0 - 0 0 - PNODE PORTN Open Drain Enable Register 5DH P72 Output 0:CMOS 1:Open Drain PN6 Output 0:CMOS 1:Open Drain PN5 Output 0:CMOS 1:Open Drain PN4 Output 0:CMOS 1:Open Drain PN2 Output 0:CMOS 1:Open Drain PN1 Output 0:CMOS 1:Open Drain - PN6C PN5C PN4C PN3C PN2C PN1C PN0C W - 0 0 0 0 0 0 0 PNCR PORTN Control Register 5EH (no RMW) 0:Input 1:Output - PN6F PN5F PN4F PN3F PN2F PN1F PN0F W W - 0 0 0 0 0 0 0 PNFC PORTN Function Register 5FH (no RMW) 0:PORT 1:SO2 SDA2 A15 0:PORT SI1 1:SCL1 A14 0:PORT 1:SO1 SDA1 A13 0:PORT 1:SCK1 A12 0:PORT SI0 1:SCL0 0:PORT 1:SO0 SDA0 0:PORT 1:SCK0 PNCR PNFC - PN6 PN5 PN4 PN3 PN2 PN1 PN0 0 0 - Input Port Input Port, SI1 Input Port Input Port, SCK1 (Input) Input Port, SI0 Input Port Input Port, SCK0 (Input) 1 0 - Output Port 1 1 - SO2/SDA2 SCL1 SO1/SDA1 SCK1 (Output) SCL0 SO0/SDA0 SCK0 (Output) 0 1 - A15 A14 A13 A12 Don ’t use this setting. *To switch P72-output from push-pull type to Open-drain type, set 1 to PNODE<ODE72>.

(2) 8-bit Timer 8-Bit Timer 01,23,45,67 Symbol Name ADDRESS 7 6 5 4 3 2 1 0 T0RDE - - - I2T01 T01PRUN T1RUN T0RUN R/W R/W R/W 0 - - - 0 0 0 0 TRUN01 8bit Timer01 Run Register 80H Double Buffer 0:Disable 1:Enable IDLE2 0:Stop Operate 8bit Timer Run/Stop Control 0:Stop & Clear 1:Run (Count up) W TREG0 8Bit Timer Register 0 82H (no RMW) Undefined W TREG1 8Bit Timer Register 1 83H (no RMW) Undefined T01M1 T01M0 PWM01 PWM00 T1CLK1 T1CLK0 T0CLK1 T0CLK0 R/W 0 0 0 0 0 0 0 0 TMOD01 8Bit Timer0,1 Source CLK & MODE Register 84H Operate mode 00:8bit Timer 01:16bit Timer 10:8bit PPG 11:8bit PWM PWM cycle 00:reserved 01:2 10:27 11:28 Timer1 source clock 00:T0TRG 01:φT1 10:φT16 11:φT256 Timer0 source clock 00:TI0 01:φT1 10:φT4 11:φT16 - - - - TFF1C1 TFF1C0 TFF1IE TFF1IS R/W R/W - - - - 1 1 0 0 TFFCR1 Timer1 Flip-Flop Control Register 85H (no RMW) 00:Invert TFF1 01:Set TFF1 10:Clear TFF1 11:Don’t care TFF1 Invert 0:Disable 1:Enable TFF1 Invert 0:Timer0 1:Timer1 T2RDE - - - I2T23 T23PRUN T3RUN T2RUN R/W R/W R/W 0 - - - 0 0 0 0 TRUN23 8bit Timer23 Run Register 88H Double Buffer 0:Disable 1:Enable IDLE2 0:Stop 1:Operate 8bit Timer Run/Stop Control 0:Stop & Clear 1:Run (Count up) W TREG2 8Bit Timer Register 2 8AH (no RMW) Undefined W TREG3 8Bit Timer Register 3 8BH (no RMW) Undefined T23M1 T23M0 PWM21 PWM20 T3CLK1 T3CLK0 T2CLK1 T2CLK0 R/W 0 0 0 0 0 0 0 0 TMOD23 8Bit Timer2,3 Source CLK & MODE Register 8CH Operate mode 00:8bit Timer 01:16bit Timer 10:8bit PPG 11:8bit PWM PWM cycle 00:reserved 01:2 10:27 11:28 Timer3 source clock 00:T2TRG 01:φT1 10:φT16 11:φT256 Timer2 source clock 00:reserved 01:φT1 10:φT4 11:φT16

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - - - - TFF3C1 TFF3C0 TFF3IE TFF3IS R/W R/W - - - - 1 1 0 0 TFFCR3 Timer3 Flip-Flop Control Register 8DH (no RMW) 00:Invert TFF3 01:Set TFF3 10:Clear TFF3 11:Don’t Care TFF3 Invert 0:Disable 1:Enable TFF3 Invert 0:Timer2 1:Timer3 T4RDE - - - I2T45 T45PRUN T5RUN T4RUN R/W R/W R/W 0 - - - 0 0 0 0 TRUN45 8bit Timer45 Run Register 90H Double Buffer 0:Disable 1:Enable IDLE2 0:Stop 1:Operate 8bit Timer Run/Stop Control 0:Stop & Clear 1:Run (Count up) W TREG4 8Bit Timer Register 4 92H (no RMW) Undefined W TREG5 8Bit Timer Register 5 93H (no RMW) Undefined T45M1 T45M0 PWM41 PWM40 T5CLK1 T5CLK0 T4CLK1 T4CLK0 R/W 0 0 0 0 0 0 0 0 TMOD45 8Bit Timer4,5 Source CLK & MODE Register 94H Operate mode 00:8bit Timer 01:16bit Timer 10:8bit PPG 11:8bit PWM PWM cycle 00:reserved 01:26 10:27 11:28 Timer5 source clock 00:T4TRG 01:φT1 10:φT16 11:φT256 Timer4 source clock 00:TI4 01:φT1 10:φT4 11:φT16 - - - - TFF5C1 TFF5C0 TFF5IE TFF5IS R/W R/W - - - - 1 1 0 0 TFFCR5 Timer5 Flip-Flop Control Register 95H (no RMW) 00:Invert TFF5 01:Set TFF5 10:Clear TFF5 11:Don’t care TFF5 Invert Disable 1:Enable TFF5 Invert 0:Timer4 1:Timer5 T6RDE - - - I2T67 T67PRUN T7RUN T6RUN R/W R/W R/W 0 - - - 0 0 0 0 TRUN67 8bit Timer67 Run Register 98H Double Buffer Disable 1:Enable IDLE2 0:Stop 1:Operate 8bit Timer Run/Stop Control 0:Stop & Clear 1:Run (Count up) W TREG6 8Bit Timer Register 6 9AH (no RMW) Undefined W TREG7 8Bit Timer Register 7 9BH (no RMW) Undefined

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 T67M1 T67M0 PWM61 PWM60 T7CLK1 T7CLK0 T6CLK1 T6CLK0 R/W 0 0 0 0 0 0 0 0 TMOD67 8Bit Timer6,7 Source CLK & MODE Register 9CH Operate mode 00:8bit Timer 01:16bit Timer 10:8bit PPG 11:8bit PWM PWM cycle 00:reserved 01:2 10:27 11:28 Timer7 source clock 00:T6TRG 01:φT1 10:φT16 11:φT256 Timer6 source clock 00:reserved 01:φT1 10:φT4 11:φT16 - - - - TFF7C1 TFF7C0 TFF7IE TFF7IS R/W R/W - - - - 1 1 0 0 TFFCR7 Timer7 Flip-Flop Control Register 9DH (no RMW) 00:Invert TFF7 01:Set TFF7 10:Clear TFF7 11:Don’t Care TFF7 Invert Disable 1:Enable TFF7 Invert 0:Timer6 1:Timer7

(3)16-bit Timer 16-Bit Timer 8,A Symbol Name ADDRESS 7 6 5 4 3 2 1 0 T8RDE - - - I2T8 T8PRUN - T8RUN R/W R/W R/W R/W R/W 0 0 - - 0 0 - 0 TRUN8 16bit Timer8 Run Register A0H Double Buffer Disable 1:Enable Fix to “0” IDLE2 0:Stop Operate 16bit Timer Run/Stop Control 0:Stop & Clear 1:Run (Count up) CAP9T9 EQ9T9 CAP8IN CAP89M1 CAP89M0 T8CLE T8CLK1 T8CLK0 R/W W R/W 0 0 1 0 0 0 0 0 TMOD8 16bit Timer8 Source CLK & Mode Register A2H TFF9 invert trigger 0: Disable 1: Enable 0:Soft Capture 1:Don’t care Capture Timing 00:disable 01:TI8↑ TI9↑ 10:TI8↑ TI8↓ 11:TFF1↑ TFF1↓ 1:UC8 Clear Enable Source Clock 00:TI8 01:φT1 10:φT4 11:φT16 TFF9C1 TFF9C0 CAP9T8 CAP8T8 EQ9T8 EQ8T8 TFF8C1 TFF8C0 W R/W W 1 1 0 0 0 0 1 1 TFFCR8 16Bit Timer8 Flip-Flop Control Register A3H 00:Invert TFF9 01:Set TFF9 10:Clear TFF9 11:Don’t Care TFF8 invert trigger 0: Disable 1: Enable 00:Invert TFF8 01:Set TFF8 10:Clear TFF8 11:Don’t Care W TREG8L 16Bit Timer Register 8 Low A8H (no RMW) Undefined W TREG8H 16Bit Timer Register 8 High A9H (no RMW) Undefined W TREG9L 16Bit Timer Register 9 Low AAH (no RMW) Undefined W TREG9H 16Bit Timer Register 9 High ABH (no RMW) Undefined R CAP8L Capture Register 8 Low ACH Undefined R CAP8H Capture Register 8 High ADH Undefined R CAP9L Capture Register 9 Low AEH Undefined R CAP9H Capture Register 9 High AFH Undefined

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 TARDE - - - I2TA TAPRUN - TARUN R/W R/W R/W R/W R/W 0 0 - - 0 0 - 0 TRUNA 16bit TimerA Run Register B0H Double Buffer 0:Disable 1:Enable Fix to “0” IDLE2 0:Stop 1:Operate 16bit Timer Run/Stop Control 0:Stop & Clear 1:Run (Count up) CAPBTB EQBTB CAPAIN CAPABM1 CAPABM0 TACLE TACLK1 TACLK0 R/W W R/W 0 0 1 0 0 0 0 0 TMODA 16bit TimerA Source CLK & Mode Register B2H TFFB invert trigger 0: Disable 1: Enable 0:Soft Capture 1:Don’t care Capture Timing 00:disable 01:TIA↑ TIB↑ 10:TIA↑ TIA↓ 11:TFF1↑ TFF1↓ 1:UCA Clear Enable Source Clock 00:TIA 01:φT1 10:φT4 11:φT16 TFFBC1 TFFBC0 CAPBTA CAPATA EQBTA EQATA TFFAC1 TFFAC0 W R/W W 1 1 0 0 0 0 1 1 TFFCRA 16Bit TimerA Flip-Flop Control Register B3H 00:Invert TFFB 01:Set TFFB 10:Clear TFFB 11:Don’t Care TFFA invert trigger 0: Disable 1: Enable 00:Invert TFFA 01:Set TFFA 10:Clear TFFA 11:Don’t Care W TREGAL 16Bit Timer Register A Low B8H (no RMW) Undefined W TREGAH 16Bit Timer Register A High B9H (no RMW) Undefined W TREGBL 16Bit Timer Register B Low BAH (no RMW) Undefined W TREGBH 16Bit Timer Register B High BBH (no RMW) Undefined R CAPAL Capture Register A Low BCH Undefined R CAPAH Capture Register A High BDH Undefined R CAPBL Capture Register B Low BEH Undefined R CAPBH Capture Register B High BFH Undefined

(4) Serial Channels Symbol Name ADDRESS 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R(Receiving) / W(Transmission) SC0BUF Serial Channel 0 Buffer Register C0H (no RMW) Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Clear 0 after reading) R/W Undefined 0 0 0 0 0 0 0 1:Error SC0CR Serial Channel 0 Control Register C1H Receive data bit 8 Parity 0:Odd 1:Even Parity 0:Disable 1:Enable Overrun Parity Framing 0:SCLK0↑ 1:SCLK0↓ 0:Baud Rate Generator 1:SCLK0 Pin Input TB8 CTSE RXE WU SM1 SM0 SC1 SC0 R/W Undefined 0 0 0 0 0 0 0 SC0MOD0 Serial Channel 0 Mode 0 Register C2H Transmis sion Data bit 8 0:CTS Disable 1:CTS Enable Receive Disable 1:Receive Enable Wake up 0:Disable 1:Enable 00:I/O Interface Mode 01:7bit UART Mode 10:8bit UART Mode 11:9bit UART Mode 00:TimerTOTRG 01:Baud Rate Generator 10:Internal clock φ1 11:External clock (SCLK0 Input) - BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R/W 0 0 0 0 0 0 0 0 BR0CR Serial Channel 0 Baud Rate Control Register C3H Fix to “0” (16-K)/16 divided 0:Disable 1:Enable 00:φT0 01:φT2 10:φT8 11:φT32 Set the frequency divisor “N” 0 to F - - - - BR0K3 BR0K2 BR0K1 BR0K0 R/W - - - - 0 0 0 0 BR0ADD Serial Channel 0 K setting Register C4H Set the frequency divisor “K” (1 to F) I2S0 FDPX0 - - - - - - R/W R/W 0 0 - - - - - - SC0MOD1 Serial Channel 0 Mode 1 Register C5H IDLE2 0:Stop 1:Operate I/O Interface mode 1:Full duplex 0:Half duplex

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R(Receiving) / W(Transmission) SC1BUF Serial Channel 1 Buffer Register C8H (no RMW) Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Clear 0 after reading) R/W Undefined 0 0 0 0 0 0 0 1:Error SC1CR Serial Channel 1 Control Register C9H Receive Data bit 8 Parity 0:Odd 1:Even Parity Disable 1:Enable Overrun Parity Framing 0:SCLK1↑ 1:SCLK1↓ 0:Baud Rate Generator 1:SCLK1 Pin Input TB8 CTSE RXE WU SM1 SM0 SC1 SC0 R/W Undefined 0 0 0 0 0 0 0 SC1MOD0 Serial Channel 1 Mode 0 Register CAH Transmis sion data bit 8 0:CTS Disable 1:CTS Enable 0:Receive Disable 1:Receive Enable Wake up 0:Disable 1:Enable 00:I/O Interface Mode 01:7bit UART Mode 10:8bit UART Mode 11:9bit UART Mode 00:TimerTOTRG 01:Baud Rate Generator 10:Internal clock φ1 11:External clock (SCLK1 Input) - BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 R/W 0 0 0 0 0 0 0 0 BR1CR Serial Channel 1 Baud Rate Control Register CBH Fix to “0” (16-K) /16 divided Disable 1:Enable 00:φT0 01:φT2 10:φT8 11:φT32 Set the frequency divisor “N” 0 to F - - - - BR1K3 BR1K2 BR1K1 BR1K0 R/W - - - - 0 0 0 0 BR1ADD Serial Channel 1 K setting Register CCH Set the frequency divisor “K” (1 to F) I2S1 FDPX1 - - - - - - R/W R/W 0 0 - - - - - - SC1MOD1 Serial Channel 1 Mode 1 Register CDH IDLE2 0:Stop Operate I/O Interface mode 1:Full duplex 0:Half duplex

(5) Serial Expansion Interface (SEI) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 MODE SEE BOS MSTR CPOL CPHA SER1 SER0 W R/W 0 0 0 0 0 1 1 1 SECR SEI Control Register 60H SEI0 MODF Detection 0:Enable 1:Disable SEI System Enable 0:Stop 1:Run Bit Order Select bit 0:MSB 1:LSB Master Select bit 0:Slave 1:Master Clock polarity selection See figure 3.11.2, 3.11.3 Clock Phase Selection See figure 3.11.2, 3.11.3 SEI Transfer Rate Select 00:reserved 01:Divided by 2 10:Divided by 4 11:Divided by 16 SEF WCOL SOVF MODF - - - TMSE R R/W 0 0 0 0 - - - 0 SEI Transfer 0:busy or Stop 1:End WCOL Flag 1:Error SOVF Flag (Slave) 1:Error MODF Flag (Master) 1:Error SEI Mode Select 0:Compat ibility Mode 1:Micro DMA Mode - WCOL SOVF MODF TSRC TSTC TASM TMSE R R/W - 0 0 0 0 0 0 0 SESR SEI Status Register 61H WCOL Flag 1:Error SOVF Flag (Slave) 1:Error MODF Flag (Master) 1:Error SEI Receive 1:End SEI Transfer 1:End Auto Shift Enable (Master) INTSEE0 Mask (Slave) SEI Mode Select 0:Compat ibility Mode 1:Micro DMA Mode SED7 SED6 SED5 SED4 SED3 SED2 SED1 SED0 R/W 0 0 0 0 0 0 0 0 SEDR SEI Data Register 62H Transfer/Receive Data

(6) Interrupt controller Symbol Name ADDRESS 7 6 5 4 3 2 1 0 INTAD INT0 IADC IADM2 IADM1 IADM0 IOC IOM2 IOM1 IOM0 R R/W R R/W INTE0AD INT0 & INTAD Enable Register F0h 0 0 0 0 0 0 0 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W INTE12 INT1 & INT2 Enable Register D0h 0 0 0 0 0 0 0 0 INT4 INT3 I4C I4M2 I4M1 I4M0 I3C I3M2 I3M1 I3M0 R R/W R R/W INTE34 INT3 & INT4 Enable Register D1h 0 0 0 0 0 0 0 0 INT6(CAP9) INT5(CAP8) I6C I6M2 I6M1 I6M0 I5C I5M2 I5M1 I5M0 R R/W R R/W INTE56 INT5 & INT6 Enable Register D2h 0 0 0 0 0 0 0 0 INT7(CAPA) - - - - I7C I7M2 I7M1 I7M0 R R/W INTE7 INT7 Enable Register D3h - - - - 0 0 0 0 INTT1(Timer1) INTT0(Timer0) IT1C IT1M2 IT1M1 IT1M0 IT0C IT0M2 IT0M1 IT0M0 R R/W R R/W INTET01 INTT0 & INTT1 Enable Register D4h 0 0 0 0 0 0 0 0 INTT3(Timer3) INTT2(Timer2) IT3C IT3M2 IT3M1 IT3M0 IT2C IT2M2 IT2M1 IT2M0 R R/W R R/W INTET23 INTT2 & INTT3 Enable Register D5h 0 0 0 0 0 0 0 0 INTT5(Timer5) INTT4(Timer4) IT5C IT5M2 IT5M1 IT5M0 IT4C IT4M2 IT4M1 IT4M0 R R/W R R/W INTET45 INTT4 & INTT5 Enable Register D6h 0 0 0 0 0 0 0 0 INTT7(Timer7) INTT6(Timer6) IT7C IT7M2 IT7M1 IT7M0 IT6C IT6M2 IT6M1 IT6M0 R R/W R R/W INTET67 INTT6 & INTT7 Enable Register D7h 0 0 0 0 0 0 0 0 INTTR9(Timer8) INTTR8(Timer8) IT9C IT9M2 IT9M1 IT9M0 IT8C IT8M2 IT8M1 IT8M0 R R/W R R/W INTET89 INTTR8 & INTTR9 Enable Register D8h 0 0 0 0 0 0 0 0 INTTRB(TimerA) INTTRA(TimerA) ITBC ITBM2 ITBM1 ITBM0 ITAC ITAM2 ITAM1 ITAM0 R R/W R R/W INTETAB INTTRA & INTTRB Enable Register D9h 0 0 0 0 0 0 0 0 INTTOA INTTO8 ITOAC ITOAM2 ITOAM1 ITOAM0 ITO8C ITO8M2 ITO8M1 ITO8M0 R R/W R R/W INTETO8A INTTO8 & INTTOA (Overflow) Enable Register DAh 0 0 0 0 0 0 0 0

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 INTTX0 INTRX0 ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 R R/W R R/W INTES0 INTRX0 & INTTX0 Enable Register DBh 0 0 0 0 0 0 0 0 INTTX1 INTRX1 ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0 R R/W R R/W INTES1 INTRX1 & INTTX1 Enable Register DCh 0 0 0 0 0 0 0 0 INTCT INTCR ICTC ICTM2 ICTM1 ICTM0 ICRC ICRM2 ICRM1 ICRM0 R R/W R R/W INTECRT INTCR & INTCT Enable Register DDh 0 0 0 0 0 0 0 0 INTCG - - - - ICGC ICGM2 ICGM1 ICGM0 R R/W INTECG INTCG Enable Register Deh - - - - 0 0 0 0 INTSEE0 INTSEM0 ISEE0C ISEE0M2 ISEE0M1 ISEE0M0 ISEM0C ISEM0M2 ISEM0M1 ISEM0M0 R R/W R R/W INTESEE0 INTSEM0 & INTSEE0 Enable Register DFh 0 0 0 0 0 0 0 0 INTSET0 INTSER0 ISET0C ISET0M2 ISET0M1 ISET0M0 ISER0C ISER0M2 ISER0M1 ISER0M0 R R/W R R/W INTESED0 INTSER0 & INTSET0 Enable Register E0h 0 0 0 0 0 0 0 0 I N T R T C - - - - IRTCC IRTCM2 IRTCM1 IRTCM0 R R/W INTERTC INTRTC Enable E1h - - - - 0 0 0 0 INTSBS2 INTSBE2 ISBS0C ISBS0M2 ISBS0M1 ISBS0M0 ISBE0C ISBE0M2 ISBE0M1 ISBE0M0 R R/W R R/W INTESB2 INTSBE2 & INTSBS2 Enable Register E2h 0 0 0 0 0 0 0 0 INTSBS0 INTSBE0 ISBS0C ISBS0M2 ISBS0M1 ISBS0M0 ISBE0C ISBE0M2 ISBE0M1 ISBE0M0 R R/W R R/W INTESB0 INTSBE0 & INTSBS0 Enable Register E3h 0 0 0 0 0 0 0 0 INTSBS1 INTSBE1 ISBS1C ISBS1M2 ISBS1M1 ISBS1M0 ISBE1C ISBE1M2 ISBE1M1 ISBE1M0 R R/W R R/W INTESB1 INTSBE1 & INTSBS1 Enable Register E4h 0 0 0 0 0 0 0 0 MKI7 MKI6 MKI5 MKI4 MKI3 MKI2 MKI1 MKI0 R/W 1 1 1 1 1 1 1 1 INTMK0 Interrupt Mask Control 0 E5h 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable MKIT7 MKIT6 MKIT5 MKIT4 MKIT3 MKIT2 MKIT1 MKIT0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 INTMK1 Interrupt Mask Control 1 E6h 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - MKIRTC MKITDA MKITD MKITRB MKITRA MKITR9 MKITR8 R/W R/W R/W R/W R/W R/W R/W - 1 1 1 1 1 1 1 INTMK2 Interrupt Mask Control 2 E7h 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable - MKICG MKICT MKICR MKITX1 MKIRX1 MKITX0 MKIRX0 R/W R/W R/W R/W R/W R/W R/W - 1 1 1 1 1 1 1 INTMK3 Interrupt Mask Control 3 E8h 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable - - - - MKISET0 MKISER0 MKISEE0 MKISEM0 R/W R/W R/W R/W - - - - 1 1 1 1 INTMK4 Interrupt Mask Control 4 E9h 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable - MKISBS2 MKISBE2 MKIAD MKISBE1 MKISBE1 MKISBS 0 MKISBE 0 R/W R/W R/W R/W R/W R/W R/W - 1 1 1 1 1 1 1 INTMK5 Interrupt Mask Control 5 EAh 0 : Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable 0: Mask 1: Enable WFLG7 WFLG6 WFLG5 WFLG4 WFLG3 WFLG2 WFLG1 WFLG0 R 0 0 0 0 0 0 0 0 WUPFLAG Wake-up flag Control Register ECh WUINT7 0:No- request 1:request WUINT6 0:No- request 1:request WUINT5 0:No- request 1:request WUINT4 0:No- request 1:request WUINT3 0:No- request 1:request WUINT2 0:No- request 1:request WUINT1 0:No- request 1:request WUINT0 0:No- request 1:request WMD7 WMD6 WMD5 WMD4 WMD3 WMD2 WMD1 WMD0 R/W 0 0 0 0 0 0 0 0 WUPMOD Wake-up Mode Control Register EDh WUINT7 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT6 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT5 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT4 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT3 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT2 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT1 0:Falling & Rising Edge 1:Falling or Rising Edge WUINT0 0:Falling & Rising Edge 1:Falling or Rising Edge WED7 WED6 WED5 WED4 WED3 WED2 WED1 WED0 R/W 0 0 0 0 0 0 0 0 WUPEDGE Wake-up Edge select Register EEh WUINT7 0:Falling Edge 1:Rising Edge WUINT6 0:Falling Edge 1:Rising Edge WUINT5 0:Falling Edge 1:Rising Edge WUINT4 0:Falling Edge 1:Rising Edge WUINT3 0:Falling Edge 1:Rising Edge WUINT2 0:Falling Edge 1:Rising Edge WUINT1 0:Falling Edge 1:Rising Edge WUINT0 0:Falling Edge 1:Rising Edge WMK7 WMK6 WMK5 WMK4 WMK3 WMK2 WMK1 WMK0 R/W 0 0 0 0 0 0 0 0 WUPMASK Wake-up Mask Register EFh WUINT7 Disable 1:Enable WUINT6 0:Disable 1:Enable WUINT5 0:Disable 1:Enable WUINT4 0:Disable 1:Enable WUINT3 0:Disable 1:Enable WUINT2 0:Disable 1:Enable WUINT1 0:Disable 1:Enable WUINT0 0:Disable 1:Enable

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 INTTC1(DMA1) INTTC0(DMA0) ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R/W R R/W INTETC01 INTTC0 & INTTC1 Enable Register F1h 0 0 0 0 0 0 0 0 INTTC3(DMA3) INTTC2(DMA2) ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R/W R R/W INTETC23 INTTC2 & INTTC3 Enable Register F2h 0 0 0 0 0 0 0 0 INTTC5(DMA5) INTTC4(DMA4) ITC5C ITC5M2 ITC5M1 ITC5M0 ITC4C ITC4M2 ITC4M1 ITC4M0 R R/W R R/W INTETC45 INTTC4 & INTTC5 Enable Register F3h 0 0 0 0 0 0 0 0 INTTC7(DMA7) INTTC6(DMA6) ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R/W R R/W INTETC67 INTTC6 & INTTC7 Enable Register F4h 0 0 0 0 0 0 0 0 NMI INTWD INMIC - - - IWDC - - - R R INTNMWDT NMI & INTWD Enable Register F7h 0 - - - 0 - - - - - - - - - IOLE NMIREE R/W - - - - - - 0 0 IIMC Interrupt Input Mode Control Register F6h (no RMW) 0:INT0 edge mode 1:INT0 level mode 1:Operate even at NMI rise Edge - - - - - - - - W 0 0 0 0 0 0 0 0 INTCLR Interrupt Clear Control Register F8h (no RMW) Interrupt Vector

(7) DMA controller Symbol Name ADDRESS 7 6 5 4 3 2 1 0 DMA0 Start Vector - - DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W DMA0V DMA0 Start Vector Register 100h (no RMW) - - 0 0 0 0 0 0 DMA1 Start Vector - - DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W DMA1V DMA1 Start Vector Register 101h (no RMW) - - 0 0 0 0 0 0 DMA2 Start Vector - - DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 R/W DMA2V DMA2 Start Vector Register 102h (no RMW) - - 0 0 0 0 0 0 DMA3 Start Vector - - DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R/W DMA3V DMA3 Start Vector Register 103h (no RMW) - - 0 0 0 0 0 0 DMA4 Start Vector - - DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0 R/W DMA4V DMA4 Start Vector Register 104h (no RMW) - - 0 0 0 0 0 0 DMA5 Start Vector - - DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R/W DMA5V DMA5 Start Vector Register 105h (no RMW) - - 0 0 0 0 0 0 DMA6 Start Vector - - DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R/W DMA6V DMA6 Start Vector Register 106h (no RMW) - - 0 0 0 0 0 0 DMA7 Start Vector - - DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R/W DMA7V DMA7 Start Vector Register 107h (no RMW) - - 0 0 0 0 0 0 DMA Burst DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0 R/W DMAB DMA Burst Register 108h (no RMW) 0 0 0 0 0 0 0 0 DMA Request DREQ7 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQ0 R/W DMAR DMA Request Register 109h (no RMW) 0 0 0 0 0 0 0 0

(8) Control register Symbol Name ADDRESS 7 6 5 4 3 2 1 0 HALTM1 HALTM0 - - - CLKOE CLKM1 CLKM0 R/W R/W R/W 1 1 - 0 - 0 0 0 CLKMOD Clock Mode Register 10AH Stand by mode 00:IDLE3 mode 01:STOP mode 10:IDLE1 mode 11:IDLE2 mode Fixed to “0” CLK Output Enable 0：Not output 1：Output 00:fc output 01:(reserved) 10:2/5･fc output 11:(reserved) WDTE WDTP1 WDTP0 - DRVE I2WDT RESCR - R/W R/W 1 0 0 - 0 0 0 0 WDMOD Watchdog Timer Mode Register 110H 1:WDT Enable 00 : 216/fc 01 : 218/fc 10 : 220/fc 11 : 222/fc 1:Drive pin in STOP mode IDLE2 0:Stop 1:Operate 1:Reset connect internally WDT out to RESET pin Fix to “0” W - WDCR Watchdog Timer Control Register 111H B1H : WDT Disable 4EH : WDT Clear

(9) AD converter Symbol Name ADDRESS 7 6 5 4 3 2 1 0 EOCF ADBF - - ITM0 REPET SCAN ADS R R/W 0 0 0 0 0 0 0 0 ADMOD0 AD Mode Control Register 0 138H AD Conversion End Flag 1:END AD Conversion BUSY Flag 1:Busy Fix to “0” Fix to “0” 0: Every 1 time 1: Every 4 times Repeat mode 0:Single mode 1:Repeat mode Scan mode 0:Fixed channel mode 1:Channel scan mode AD Conversion start 1:Start Always read as ”0” VREFON I2AD - - ADCH3 ADCH2 ADCH1 ADCH0 R/W R/W R/W 0 0 0 0 0 0 0 0 ADMOD1 AD Mode Control Register 1 139H String resistance 0:OFF 1:ON IDLE2 0:Stop 1:Operate Fix to “0” Fix to “0” Input channel 0000: AN0 AN0 ： ： 1011: AN11 AN0→AN1→AN2→ … →AN11 1100, 1101, 1110, 1111 : reserved ADR01 ADR00 - - - - - ADR0RF R R R ADREG0L AD Result Register 0 Low 120H Undefined - - - - - 0 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 R ADREG0H AD Result Register 0 High 121H Undefined ADR11 ADR10 - - - - - ADR1RF R R ADREG1L AD Result Register 1 Low 122H Undefined - - - - - 0 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 R ADREG1H AD Result Register 1 High 123H Undefined ADR21 ADR20 - - - - - ADR2RF R R ADREG2L AD Result Register 2 Low 124H Undefined - - - - - 0 ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 R ADREG2H AD Result Register 2 High 125H Undefined ADR31 ADR30 - - - - - ADR3RF R R ADREG3L AD Result Register 3 Low 126H Undefined - - - - - 0 ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 R ADREG3H AD Result Register 3 High 127H Undefined

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 ADR41 ADR40 - - - - - ADR4RF R R ADREG4L AD Result Register 4 Low 128H Undefined - - - - - 0 ADR49 ADR48 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42 R ADREG4H AD Result Register 4 High 129H Undefined ADR51 ADR50 - - - - - ADR5RF R R ADREG5L AD Result Register 5 Low 12AH Undefined - - - - - 0 ADR59 ADR58 ADR57 ADR56 ADR55 ADR54 ADR53 ADR52 R ADREG5H AD Result Register 5 High 12BH Undefined ADR61 ADR60 - - - - - ADR6RF R R ADREG6L AD Result Register 6 Low 12CH Undefined - - - - - 0 ADR69 ADR68 ADR67 ADR66 ADR65 ADR64 ADR63 ADR62 R ADREG6H AD Result Register 6 High 12DH Undefined ADR71 ADR70 - - - - - ADR7RF R R ADREG7L AD Result Register 7 Low 12EH Undefined - - - - - 0 ADR79 ADR78 ADR77 ADR76 ADR75 ADR74 ADR73 ADR72 R ADREG7H AD Result Register 7 High 12FH Undefined ADR81 ADR80 - - - - - ADR8RF R R ADREG8L AD Result Register 8 Low 130H Undefined - - - - - 0 ADR89 ADR88 ADR87 ADR86 ADR85 ADR84 ADR83 ADR82 R ADREG8H AD Result Register 8 High 131H Undefined ADR91 ADR90 - - - - - ADR9RF R R ADREG9L AD Result Register 9 Low 132H Undefined - - - - - 0 ADR99 ADR98 ADR97 ADR96 ADR95 ADR94 ADR93 ADR92 R ADREG9H AD Result Register 9 High 133H Undefined ADRA1 ADRA0 - - - - - ADRARF R R ADREGAL AD Result Register A Low 134H Undefined - - - - - 0 ADRA9 ADRA8 ADRA7 ADRA6 ADRA5 ADRA4 ADRA3 ADRA2 R ADREGAH AD Result Register A High 135H Undefined ADRB1 ADRB0 - - - - - ADRBRF R R ADREGBL AD Result Register B Low 136H Undefined - - - - - 0 ADRB9 ADRB8 ADRB7 ADRB6 ADRB5 ADRB4 ADRB3 ADRB2 R ADREGBH AD Result Register B High 137H Undefined

(10) Memory controller Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - BWW2 BWW1 BWW0 - BWR2 BWR1 BWR0 W W - 0 1 0 - 0 1 0 BCSL BLOCK CS/WAIT Control Register Low 148H Number of write waits 001:0wait 010:1wait 011:Nwait 101:2wait 110:3wait others : reserved Number of read waits 001:0wait 010:1wait 011:Nwait 101:2wait 110:3wait others : reserved BE BM - - BOM1 BOM0 BBUS1 BBUS0 W W W W 1 0 0 0 0 0 0 0 BCSH BLOCK CS/WAIT Control Register High 149H CS select 0:Disable 1:Enable 0:16MB 1:Sets area Fix to “0” Fix to “0” 00:SRAM/ROM 01,10,11:Resetved 00:8bit 01,10,11:reserved MV22 MV21 MV20 MV19 MV18 MV17 MV16 MV15 R/W 1 1 1 1 1 1 1 1 MAMR Memory Address Mask Register 14AH 0:Compare enable 1:Compare disable MS23 MS22 MS21 MS20 MS19 MS18 MS17 MS16 R/W 1 1 1 1 1 1 1 1 MSAR Memory Start Address Register 14BH Set start address A23 to A16 - - - - - - - - R/W 0 0 0 0 0 0 0 0 *note2 FSWE Flash Security Write Enable Register 16BH C9H: Auto Chip Erase & Unprotect command Enable Code Others: Auto Chip Erase & Unprotect command Disable Code RAMSTB RAMWI - - - - - - R/W 0 *note1 1 - - - - - - RAMCR RAM Write Control Register 16DH 0:lost data or Power on reset 1:kept data RAM write 0:Disable 1:Enable R/W R/W R/W R/W R 0 0 0 0 - 1 - - *note2 FLSR Flash Status Register 16FH Note) Set to 0. Note) Set to 0. Note) Set to 0. Note) Set to 0. Ready /Busy flag 0:Busy (auto operation in progress) 1:Ready (auto operation finished) Note1: After power-on reset. Warm reset does not change this bit. Note2: Only TMP92FD54AI.

(11) Serial Bus Interface (SBI) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK SCK3 SCK2 SCK1 SWRMON/SCK0 W R/W W R/W 0 0 0 0 1 0 0 1/0 170H (no RMW) I2C mode Number of transfer bits 000:8 001:1 010:2 011:3 100:4 101:5 110:6 111:7 Acknowledge mode 0:Disable 1:Enable Setting of the divide value “n”/fast/standard 0001:− 0010: − 0011:8 0100:9 0101:10 0110:11 1000:fast 1111:standard other:reserved SIOS SIOINH SIOM1 SIOM0 - SCK2 SCK1 SCK0 W W W 0 0 0 0 1 0 0 0 SBI0CR1 SBI0 Control Register 1 170H (no RMW) SIO mode Transfer 0:Stop 1:Start Transfer 0:Continue 1:Abort Transfer mode 00:8bit transmit 10:8bit transmit/receive 11:8bit receive Note) Write 0 to this bit in SIO mode. Setting of the divide value “n” 000:4 001:5 010:6 011:7 100:8 101:9 110:10 111:external clock SCK0 RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 R(Receiving)/W(Transmission) SBI0DBR SBI0 Buffer Register 171H (no RMW) Undefine SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS W 0 0 0 0 0 0 0 0 I2C0AR I2CBUS0 Address Register 172H (no RMW) Setting Slave Address Address recognition 0:Enable 1:Disable MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 W 0 0 0 1 0 0 0 0 173H (no RMW) I2C mode 0:Slave 1:Master 0:Receive 1:Transmit Start/stop generation 0:Stop 1:Start INTSBE0 interrupt 0:Request 1:Cancel Operation mode selection 00:Port mode 10:I2C mode 01:SIO mode 11:reserved Software reset generate write “10” and “01”, then an internal reset signal is generated. - - - - SBIM1 SBIM0 - - W W W - - - - 0 0 0 0 SBI0CR2 SBI0 Control Register 2 173H (no RMW) SIO mode Operation mode selection 00:Port mode 10:I2C mode 01:SIO mode 11:reserved Fix to “00” MST TRX BB PIN AL AAS AD0 LRB R 0 0 0 1 0 0 0 0 173H (no RMW) I2C mode 0:Slave 1:Master 0:Receive 1:transmit Bus status Monitor 0:Free 1:Busy INTSBE0 interrupt 0:request 1:Cancel Arbitration lost detection monitor 1:Detect Slave address match detection monitor 1:Detect General call detection 1:Detect Last receive bit monitor 0: “0” 1: “1” - - - - SIOF SEF - - R - - - - 0 0 - - SBI0SR SBI0 Status Register 173H (no RMW) SIO mode Transfer status 0:Stopped 1:In progress Shift status 0:Stopped 1:In progress

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK SCK3 SCK2 SCK1 SWRMON/SCK0 W R/W W R/W 0 0 0 0 1 0 0 1/0 178H (no RMW) I2C mode Number of transfer bits 000:8 001:1 010:2 011:3 100:4 101:5 110:6 111:7 Acknowledge mode 0:Disable 1:Enable Setting of the divide value “n”/fast/standard 0001:- 0010:- 0011:8 0100:9 0101:10 0110:11 1000:fast 1111:standard other:reserved SIOS SIOINH SIOM1 SIOM0 - SCK2 SCK1 SCK0 W W W 0 0 0 0 1 0 0 0 SBI1CR1 SBI1 Control Register 1 178H (no RMW) SIO mode Transfer 0:Stop 1:Start Transfer 0:Continue 1:Abort Transfer mode 00:8bit transmit 10:8bit transmit/receive 11:8bit receive Note) Write 0 to this bit in SIO mode. Setting of the divide value “n” 000:4 001:5 010:6 011:7 100:8 101:9 110:10 111:external clock SCK1 RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 R(Receiving)/W(Transmission) SBI1DBR SBI1 Buffer Register 179H (no RMW) Undefine SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS W 0 0 0 0 0 0 0 0 I2C1AR I2CBUS1 Address Register 17AH (no RMW) Setting Slave Address Address recognition 0:Enable 1:Disable MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 W 0 0 0 1 0 0 0 0 17BH (no RMW) I2C mode 0:Slave 1:Master 0:Receive 1:Transmit Start/stop generation 0:Stop 1:Start INTSBE1 interrupt 0:Request 1:Cancel Operation mode selection 00:Port mode 10:I2C mode 01:SIO mode 11:reserved Software reset generate write “10” and “01”, then an internal reset signal is generated. - - - - SBIM1 SBIM0 - - W W W - - - - 0 0 0 0 SBI1CR2 SBI1 Control Register 2 17BH (no RMW) SIO mode Operation mode selection 00:Port mode 10:I2C mode 01:SIO mode 11:reserved Fix to “00” MST TRX BB PIN AL AAS AD0 LRB R 0 0 0 1 0 0 0 0 17BH (no RMW) I2C mode 0:Slave 1:Master 0:Receive 1:transmit Bus status monitor 0:Free 1:Busy INTSBE1 interrupt 0:request 1:Cancel Arbitration lost detection monitor 1:Detect Slave address match detection monitor 1:Detect General call detection 1:Detect Last receive bit monitor 0: “0” 1: “1” - - - - SIOF SEF - - R - - - - 0 0 - - SBI1SR SBI1 Status Register 17BH (no RMW) SIO mode Transfer status 0:Stopped 1:In progress Shift status 0:Stopped 1:In progress

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK SCK3 SCK2 SCK1 SWRMON/SCK0 W R/W W R/W 0 0 0 0 1 0 0 1/0 180H (no RMW) I2C mode Number of transfer bits 000:8 001:1 010:2 011:3 100:4 101:5 110:6 111:7 Acknowledge mode 0:Disable 1:Enable Setting of the divide value “n”/fast/standard 0001:- 0010:- 0011:8 0100:9 0101:10 0110:11 1000:fast 1111:standard other:reserved SIOS SIOINH SIOM1 SIOM0 - SCK2 SCK1 SCK0 W W W 0 0 0 0 1 0 0 0 SBI2CR1 SBI2 Control Register 1 180H (no RMW) SIO mode Transfer 0:Stop 1:Start Transfer 0:Continue 1:Abort Transfer mode 00:8bit transmit 10:8bit transmit/receive 11:8bit receive Note) Write 0 to this bit in SIO mode. Setting of the divide value “n” 000:4 001:5 010:6 011:7 100:8 101:9 110:10 111:external clock SCK2 RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 R(Receiving)/W(Transmission) SBI2DBR SBI2 Buffer Register 181H (no RMW) Undefine SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS W 0 0 0 0 0 0 0 0 I2C2AR I2CBUS2 Address Register 182H (no RMW) Setting Slave Address Address recognition 0:Enable 1:Disable MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 W 0 0 0 1 0 0 0 0 183H (no RMW) I2C mode 0:Slave 1:Master 0:Receive 1:Transmit Start/stop generation 0:Stop 1:Start INTSBE1 interrupt 0:Request 1:Cancel Operation mode selection 00:Port mode 10:I2C mode 01:SIO mode 11:reserved Software reset generate write “10” and “01”, then an internal reset signal is generated. - - - - SBIM1 SBIM0 - - W W W - - - - 0 0 0 0 SBI2CR2 SBI2 Control Register 2 183H (no RMW) SIO mode Operation mode selection 00:Port mode 10:I2C mode 01:SIO mode 11:reserved Fix to “00” MST TRX BB PIN AL AAS AD0 LRB R 0 0 0 1 0 0 0 0 183H (no RMW) I2C mode 0:Slave 1:Master 0:Receive 1:transmit Bus status monitor 0:Free 1:Busy INTSBE1 interrupt 0:request 1:Cancel Arbitration lost detection monitor 1:Detect Slave address match detection monitor 1:Detect General call detection 1:Detect Last receive bit monitor 0: “0” 1: “1” - - - - SIOF SEF - - R - - - - 0 0 - - SBI2SR SBI2 Status Register 183H (no RMW) SIO mode Transfer status 0:Stopped 1:In progress Shift status 0:Stopped 1:In progress

Symbol Name ADDRESS 7 6 5 4 3 2 1 0 W R/W SBI0 Baud rate Register 0 174H Fix to “0” IDLE2 0:Abort 1:Operate P4EN - - - - - - - R/W 0 - - - - - - - SBI0BR1 SBI0 Baud rate Register 1 175H Clock control 0:Abort 1:Operate W R/W SBI1 Baud rate Register 0 17CH Fix to “0” IDLE2 0:Abort 1:Operate P4EN - - - - - - - R/W 0 - - - - - - - SBI1BR1 SBI1 Baud rate Register 1 17DH Clock control 0:Abort 1:Operate W R/W SBI2 Baud rate Register 0 184H Fix to “0” IDLE2 0:Abort 1:Operate P4EN - - - - - - - R/W 0 - - - - - - - SBI2BR1 SBI2 Baud rate Register 1 185H Clock control 0:Abort 1:Operate

(12) CAN controller (1/5) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 R/W MBnMI0L Message Identifier MBn* + 00H (no RMW) - - - - - - - - IDE GAME RFH ID28 ID27 ID26 ID25 ID24 R/W MBnMI0H Message Identifier MBn* + 01H ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 R/W MBnMI1L Message Identifier MBn* + 02H ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 R/W MBnMI1H Message Identifier MBn* + 03H - - - RTR DLC3 DLC2 DLC1 DLC0 R/W MBnMCFL Message Control Field L MBn* + 04H - - - - - - - - MBnMCFH Message Control Field H MBn* + 05H D07 D06 D05 D04 D03 D02 D01 D00 R/W MBnD0 Data 0 MBn* + 06H D17 D16 D15 D14 D13 D12 D11 D10 R/W MBnD1 Data 1 MBn* + 07H D27 D26 D25 D24 D23 D22 D21 D20 R/W MBnD2 Data 2 MBn* + 08H D37 D36 D35 D34 D33 D32 D31 D30 R/W MBnD3 Data 3 MBn* + 09H D47 D46 D45 D44 D43 D42 D41 D40 R/W MBnD4 Data 4 MBn* + 0AH D57 D56 D55 D54 D53 D52 D51 D50 R/W MBnD5 Data 5 MBn* + 0BH D67 D66 D65 D64 D63 D62 D61 D60 R/W MBnD6 Data 6 MBn* + 0CH D77 D76 D75 D74 D73 D72 D71 D70 R/W MBnD7 Data 7 MBn* + 0DH TSV7 TSV6 TSV5 TSV4 TSV3 TSV2 TSV1 TSV0 R MBnTSVL Time Stamp Value L MBn* + 0EH - - - - - - - - TSV15 TSV14 TSV13 TSV12 TSV11 TSV10 TSV9 TSV8 R MBnTSVH Time Stamp Value H MBn* + 0FH - - - - - - - - * MBn = 200H + n x 10H, n = 0, 1, 2, 3, … , 15

CAN controller (2/5) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 MC7 MC6 MC5 MC4 MC3 MC2 MC1 MC0 R/W MCL Mailbox Configuration Register L 300H 0 0 0 0 0 0 0 0 MC15 MC14 MC13 MC12 MC11 MC10 MC9 MC8 R/W MCH Mailbox Configuration Register H 301H 0 0 0 0 0 0 0 0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 R/W MDL Mailbox Direction Register L 302H 0 0 0 0 0 0 0 0 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 R R/W MDH Mailbox Direction Register H 303H 1 0 0 0 0 0 0 0 TRS7 TRS6 TRS5 TRS4 TRS3 TRS2 TRS1 TRS0 R/S TRSL Transmission Request Set Register L 304H (no RMW) 0 0 0 0 0 0 0 0 - TRS14 TRS13 TRS12 TRS11 TRS10 TRS9 TRS8 R/S TRSH Transmission Request Set Register H 305H (no RMW) - 0 0 0 0 0 0 0 TRR7 TRR6 TRR5 TRR4 TRR3 TRR2 TRR1 TRR0 R/S TRRL Transmission Request Reset Register L 306H (no RMW) 0 0 0 0 0 0 0 0 - TRR14 TRR13 TRR12 TRR11 TRR10 TRR9 TRR8 R/S TRRH Transmission Request Reset Register H 307H (no RMW) - 0 0 0 0 0 0 0 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 R/C TAL Transmission Acknowledge Register L 308H (no RMW) 0 0 0 0 0 0 0 0 - TA14 TA13 TA12 TA11 TA10 TA9 TA8 R/C TAH Transmission Acknowledge Register H 309H (no RMW) - 0 0 0 0 0 0 0 AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 R/C AAL Abort Acknowledge Register L 30AH (no RMW) 0 0 0 0 0 0 0 0 - AA14 AA13 AA12 AA11 AA10 AA9 AA8 R/C AAH Abort Acknowledge Register H 30BH (no RMW) - 0 0 0 0 0 0 0 RMP7 RMP6 RMP5 RMP4 RMP3 RMP2 RMP1 RMP0 R/C RMPL Receive Message Pending Register L 30CH (no RMW) 0 0 0 0 0 0 0 0 RMP15 RMP14 RMP13 RMP12 RMP11 RMP10 RMP9 RMP8 R/C RMPH Receive Message Pending Register H 30DH (no RMW) 0 0 0 0 0 0 0 0 RML7 RML6 RML5 RML4 RML3 RML2 RML1 RML0 R/C RMLL Receive Message Lost Register L 30EH (no RMW) 0 0 0 0 0 0 0 0 RML15 RML14 RML13 RML12 RML11 RML10 RML9 RML8 R/C RMLH Receive Message Lost Register H 30FH (no RMW) 0 0 0 0 0 0 0 0

CAN controller (3/5) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 LAM23 LAM22 LAM21 LAM20 LAM19 LAM18 LAM17 LAM16 R/W LAM0L Local Acceptance Mask Register 310H 0 0 0 0 0 0 0 0 LAMI - - LAM28 LAM27 LAM26 LAM25 LAM24 R/W R/W LAM0H Local Acceptance Mask Register 311H 0 - - 0 0 0 0 0 LAM7 LAM6 LAM5 LAM4 LAM3 LAM2 LAM1 LAM0 R/W LAM1L Local Acceptance Mask Register 312H 0 0 0 0 0 0 0 0 LAM15 LAM14 LAM13 LAM12 LAM11 LAM10 LAM9 LAM8 R/W LAM1H Local Acceptance Mask Register 313H 0 0 0 0 0 0 0 0 GAM23 GAM22 GAM21 GAM20 GAM19 GAM18 GAM17 GAM16 R/W GAM0L Global Acceptance Mask Register 314H 0 0 0 0 0 0 0 0 GAMI - - GAM28 GAM27 GAM26 GAM25 GAM24 R/W R/W GAM0H Global Acceptance Mask Register 315H 0 - - 0 0 0 0 0 GAM7 GAM6 GAM5 GAM4 GAM3 GAM2 GAM1 GAM0 R/W GAM1L Global Acceptance Mask Register 316H 0 0 0 0 0 0 0 0 GAM15 GAM14 GAM13 GAM12 GAM11 GAM10 GAM9 GAM8 R/W GAM1H Global Acceptance Mask Register 317H 0 0 0 0 0 0 0 0 CCR SMR HMR WUBA MTOS - TSCC SRES R/W W MCRL Master Control Register L 318H 1 0 0 0 0 - 0 0 - - - - - - TSTLB TSTERR R/W MCRH Master Control Register H 319H - - - - - - 0 0 CCE SMA HMA - TSO BO EP EW R R GSRL Global Status Register L 31AH 1 0 0 - 0 0 0 0 MsgInSlot<3:0> RM TM - - R GSRH Global Status Register H 31BH 1 1 1 1 0 0 - - BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 R/W BCR1L Bit Configuration Register 1L 31CH 0 0 0 0 0 0 0 0 - - - - - - - - BCR1H Bit Configuration Register 1H 31DH - - - - - - - - SAM TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 R/W BCR2L Bit Configuration Register 2L 31EH 0 0 0 0 0 0 0 0 - - - - - - SJW1 SJW0 R/W BCR2H Bit Configuration Register 2H 31FH - - - - - 0 0

CAN controller (4/5) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 RFPF WUIF RMLIF TRMABF TSOIF BOIF EPIF WLIF R/C GIFL Global Interrupt Flag L 320H (no RMW) 0 0 0 0 0 0 0 0 - - - - - - - - GIFH Global Interrupt Flag H 321H (no RMW) - - - - - - - - RFPM WUIM RMLIM TRMABM TSOIM BOIM EPIM WLIM R/W GIML Global Interrupt Mask L 322H 0 0 0 0 0 0 0 0 - - - - - - - - GIMH Global Interrupt Mask H 323H - - - - - - - - MBTIF7 MBTIF6 MBTIF5 MBTIF4 MBTIF3 MBTIF2 MBTIF1 MBTIF0 R/C MBTIFL Mailbox Transmit Int. Flag L 324H (no RMW) 0 0 0 0 0 0 0 0 - MBTIF14 MBTIF13 MBTIF12 MBTIF11 MBTIF10 MBTIF9 MBTIF8 R/C MBTIFH Mailbox Transmit Int. Flag H 325H (no RMW) - 0 0 0 0 0 0 0 MBRIF7 MBRIF6 MBRIF5 MBRIF4 MBRIF3 MBRIF2 MBRIF1 MBRIF0 R/C MBRIFL Mailbox Receive Int. Flag L 326H (no RMW) 0 0 0 0 0 0 0 0 MBRIF15 MBRIF14 MBRIF13 MBRIF12 MBRIF11 MBRIF10 MBRIF9 MBRIF8 R/C MBRIFH Mailbox Receive Int. Flag H 327H (no RMW) 0 0 0 0 0 0 0 0 MBIM7 MBIM6 MBIM5 MBIM4 MBIM3 MBIM2 MBIM1 MBIM0 R/W MBIML Mailbox Interrupt Flag L 328H 0 0 0 0 0 0 0 0 MBIM15 MBIM14 MBIM13 MBIM12 MBIM11 MBIM10 MBIM9 MBIM8 R/W MBIMH Mailbox Interrupt Flag H 329H 0 0 0 0 0 0 0 0 CDR7 CDR6 CDR5 CDR4 CDR3 CDR2 CDR1 CDR0 R/W CDRL Change Data Request Register L 32AH 0 0 0 0 0 0 0 0 - CDR14 CDR13 CDR12 CDR11 CDR10 CDR9 CDR8 R/W CDRH Change Data Request Register H 32BH - 0 0 0 0 0 0 0 RFP7 RFP6 RFP5 RFP4 RFP3 RFP2 RFP1 RFP0 R/C RFPL Remote Frame Pending Register L 32CH (no RMW) 0 0 0 0 0 0 0 0 RFP15 RFP14 RFP13 RFP12 RFP11 RFP10 RFP9 RFP8 R/C RFPH Remote Frame Pending Register H 32DH (no RMW) - - - - - - - - REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 R/W CECL CAN Error Counter L 32EH (no RMW) 0 0 0 0 0 0 0 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 R/W CECH CAN Error Counter H 32FH (no RMW) 0 0 0 0 0 0 0 0

CAN controller (5/5) Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - - - - TSP3 TSP2 TSP1 TSP0 R/W TSPL Time Stamp Prescaler L 330H - - - - 0 0 0 0 - - - - - - - - TSPH Time Stamp Prescaler H 331H - - - - - - - - TSC7 TSC6 TSC5 TSC4 TSC3 TSC2 TSC1 TSC0 R/W TSCL Time Stamp Counter L 332H (no RMW) 0 0 0 0 0 0 0 0 TSC15 TSC14 TSC13 TSC12 TSC11 TSC10 TSC9 TSC8 R/W TSCH Time Stamp Counter H 333H (no RMW) 0 0 0 0 0 0 0 0

(13) RTC control Symbol Name ADDRESS 7 6 5 4 3 2 1 0 - - - - RTCSEL2 RTCSEL1 RTCSEL0 RTCRUN R/W R/W R/W 0 - - - 0 0 0 0 RTCCR RTC Control Register 118h Write to “0” 1x0: 2 16/fs 1x1: 215/fs 00: 214/fs 01: 213/fs 10: 212/fs 11: 211/fs 0: Stop & Clear 1: Run XTSEL - - - - - - XTEN R/W R/W 0 - - - - - - 0 RTCFC RTC Function Control Register 119h 0:Crystal 1:CR Low frequency Oscillator (fs) 1:oscillation

1. Port Section Equivalent Circuit Diagram.

• Reading The Circuit Diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when the halt mode setting register is set to the Stop mode and the CPU executes the HALT instruction. When the drive enable bit <DRVE> is set to “1”, however, Stop remains at “0”.
• The input protection resistance ranges from several tens of ohms to several hundreds of ohms. ■ P0 (D0 to D7), P4 (A0 to A7), P70, P71, P73 to P75, PC0 to PC5, PD0 to PD7, PF1(RXD0), PF2 (CTS0, SCLK0), PF4 (RXD1), PF5 ( CTS1, SCLK1), PF6 (TX), PF7 (RX), PM0 ( SS ), PN0 (SCK0), PN3 (SCK1), PM4 (SCK2) P72 (SI2/SCL2), PF0 (TXD0), PF3 (TXD1), PM1 (MOSI), PM2 (MISO), PM3 (SECLK), PN1 (SO0/SDA0), PN2 (SI0/SCL0), PN4 (SO1/SDA1), PN5 (SI1/SCL1), PN6 (SO2/SDA2) Output Enable STOP Input Data Input Enable I/O N-ch P-chOutput Data VCC VCC N-ch P-ch Input Data Input Enable I/O N-ch P-ch VCC Output Data STOP Open Drain output enable Output Enable VCC N-ch P-ch

■ PG(AN0 to 7), PL0 to 3(AN8 to 11) INT0 RESET Input Schmitt VCC 100 kΩ Typ. RESET WDTOUT Reset Enable VCC INT0 Input Schmitt Input Data Input N-ch P-ch Analog input channel select Analog input Input Enable VCC N-ch P-ch N-ch P-ch

■ X1, X2 XT1, XT2 oscillation enable clock N-chP-ch High frequency oscillator VCC VCC N-ch P-ch N-ch P-ch Low frequency oscillation enable Type of low frequency oscillation select 0:Crystal 1:CR clock N-ch P-ch oscillator XT2 XT1 VCC VCC N-ch P-ch N-ch P-ch

■ VREFH, VREFL NMI NMI Input Schmitt P-ch VREFH VREFL String Resistance VREFON VCC VCC N-ch P-ch N-ch P-ch

■ CLK AM0 to 1, TEST0 to 1 Input Data Input VCC VCC VCC P-ch N-ch Output CLK Output Enable Internal Reset P-ch VCC N-ch P-ch N-ch P-ch

■ REGOUT ■ REGEN Regulator Enable Input Input VCC VCC P-ch Output BGR Regulator + BGR VCC N-ch P-ch

1. Points to Note and Restrictions

7.1 Notation

(1) The notation for built-in I/O registers is as follows register symbol <Bit symbol> Example: TRUN01<T0RUN> denotes bit T0RUN of register TRUN01. (2) Read-modify-write instructions (RMW) An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. Example 1: SET 3, (TRUN01); Set bit3 of TRUN01. Example 2: INC 1, (400H); Increment the data at 400H.

• Examples of read-modify-write instructions on the TLCS-900/H1 Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# ADC (mem), R/# SUB (mem), R/# SBC (mem), R/# INC #3, (mem) DEC #3, (mem) Logic operations AND (mem), R/# OR (mem), R/# XOR (mem), R/# Bit manipulation operations STCF #3/A, (mem) RES #3, (mem) SET #3, (mem) CHG #3, (mem) TSET #3, (mem) Rotate and shift operations RLC (mem) RRC (mem) RL (mem) RR (mem) SLA (mem) SRA (mem) SLL (mem) SRL (mem) RLD (mem) RRD (mem)

7.2 Points to Note

(1) Watchdog timer The watchdog timer starts operation immediately after a reset is released. When the watchdog timer is not to be used, disable it. (2) The stable time of the internal clock When releasing the external reset using “built-in clock doubler” until the internal reset is released, the requiring time to stabilize the circuit is automatically set. See section 3.1.2 “Reset Operation” for details. Also when releasing standby mode in STOP mode using an interrupt until the internal circuit starts the operation, the stable time of the oscillator is automatically input. See section 3.4 “Standby Function (3) STOP mode” for details. (3) Undefined bit in the built-in I/O register When reading the undefined bit in the built-in I/O register, the undefined value is output. Thus, when creating program, it should not be depending on this bit condition. (4) Reserved address areas The 16 bytes area (FFFFF0H to FFFFFFH) cannot be used for it is reserved as internal area. If using emulator, optional 64 Kbytes of 16M bytes area are used for control emulator. Therefore, if using emulator, its area cannot be used. (5) POP SR instruction Execute the POP SR instruction during DI condition.

1. Package 26100 251 14.0±0.2 16.0±0.2 1.0TYP 1.0TYP 14.0±0.2 16.0±0.2 0.2 ±0.1 0.5 0.08 M 15.0±0.2 1.85MAX 1.4±0.2 0.08 0.5±0.2 0~10° 0.125 +0.1 -0.05 Unit : mm 0.1 +0.15 -0.1