9250YF-27LF-T | DigiCamel IC Datasheet

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IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM DATASHEET Pin ConfigurationRecommended Application: 810/810E and 815 type chipset. Output Features:

3 CPU (2.5V) (up to 133MHz achievable through I 2C) 9 SDRAM (3.3V) (up to 133MHz achievable through I2C) 7 PCI (3.3 V) @33.3MHz 2 IOAPIC (2.5V) @ 33.3 MHz 3 Hublink clocks (3.3 V) @ 66.6 MHz 2 (3.3V) @ 48 MHz (Non spread spectrum) 1 REF (3.3V) @ 14.318 MHz Features: Supports spread spectrum modulation, 0 to -0.5% down spread. I 2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal Alternate frequency selections available through I 2C control. 56-Pin 300mil SSOP * This input has a 50K Ω pull-down to GND. *FS2//REF0 VDD GND GND 3V66-0 3V66-1 3V66-2 VDD VDD PCICLK_F PCICLK0 GND PCICLK1 PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 VDD VDD GND GND 48MHz_0 48MHz_1 VDD FS0 GND IOAPIC0 IOAPIC1 VDDL CPUCLK0 VDDL0 CPUCLK1 CPUCLK2 GNDL GND SDRAM0 SDRAM1 VDD SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD SDRAM6 SDRAM7 GND SDRAM_F VDD PD# SCLK SDATA FS1 ICS9250-27 Block Diagram REF0 VDDL 3V66 (2:0) SDRAM (7:0) PCICLK (5:0) IOAPIC (1:0) VDDL SDRAM_F PCICLK_F PLL2 48MHz (1:0) XTAL OSC Control Logic Config Reg FS (2:0) PD# /2 /3 PLL1 Spread Spectrum SDATA SCLK Functionality Power Groups AVDD = Pin 22 Analog power for PLL AGND = Pin 23 Analog ground VDD48 = Pin 27 Analog power for 48MHz PLL GND = Pin 24 Analog ground for 48MHz PLL 2SF1 SF0 SFn oitcnuF X00 e tatsirT X0 1t seT 01 0 zHM66=UPCevitcA zHM001=MARDS 011 zHM001=UPCevitcA zHM001=MARDS 110 zHM331=UPCevitcA zHM331=MARDS 111 zHM331=UPCevitcA zHM001=MARDS

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Pin Description REBMUNNIPE MANNIPE PYTN OITPIRCSED 2SFN I ytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF 0FERT UO. tuptuokcolcecnereferzHM813.41,V3.3

31 XN I kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC

42 XT UO daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC )Fp33(pac ,32,71,41,6,5 ,74,14,53,42 65,84 DNGR WPy lppusV3.3rofsnipdnuorG 7,8,9) 0:2(66V3T UOB UHrofstuptuokcolczHM66dexiFV3.3 ,12,11,01,2 ,83,33,72,22 DDVR WPy lppusrewopV3.3 21F _KLCICPT UOt uptuokcolcICPV3.3gninnureerF ,61,81,91,02 31,51 )0:5(KLCICPT UOs tuptuokcolcICPV3.3 520 _zHM84T UOB SUrofstuptuokcolczHM84dexiFV3.3 621 _zHM84T UO oediv/scihpargroftuptuoregnortS.tuptuokcolczHM84dexifV3.3 )etaregdesn/V1muminim(ecafretni 82,92) 0:1(SFN I tuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF 1egapnoelbatytilanoitcnuFotreferesaelP.ytilanoitcnuf 03A TADSO /II rofnipataD 2 tnarelotV5yrtiucricC 13K LCSN II fonipkcolC 2 tnarelotV5yrtiucricC 23# DPN I ecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA OCVehtdnadelbasideraskcolclanretniehT.etatsrewopwolaotni tonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrcehtdna .sm3nahtretaergeb ,04,93,73,63 64,54,34,24 )0:7(MARDST UO ffodenrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3 Ihguorht 2C 43F _MARDST UO Ihguorhtffodenrutebtonnac,MARDSzHM001gninnureerfV3.3 2C 25,05,94 KLCUPC )0:2( TUO gnidnepedzHM331rozHM001,zHM66.tuptuokcolcsubtsoHV5.2 .snipSFno 35,15L DDVR WPC IPAOI&UPCrofylppyusrewopV5.2 55,45) 0:1(CIPAOIT UO. zHM3.33tagninnurstuptuokcolcV5.2 The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250- 27 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. General Description

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz Maximum Allowed Current Clock Enable Configuration #DPK LCUPCM ARDSC IPAOIz HM66K LCICP ,FER zHM84 csOs OCV 0W OLW OLW OLW OLW OLW OLF FOF FO 1N ON ON ON ON ON ON ON O 518 noitidnoC noitpmusnocylppusV5.2xaM ,sdaolpacetercsidxaM V526.2=2qddV DNGro3qddV=stupnicitatsllA noitpmusnocylppusV5.2xaM ,sdaolpacetercsidxaM V564.3=2qddV DNGro3qddV=stupnicitatsllA edoMnwodrewoP 0=#NWDRWP( Am01A m01 zHM66evitcAlluF 010=]0:2[SF Am07A m082 zHM001evitcAlluF 110=]0:2[SF Am001A m082 zHM331evitcAlluF 111=]0:2[SF

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 2SF1 SF0 SFU PCM ARDS6 6V3I CPz HM84F ERC IPAOI X00 e tatsirTe tatsirTe tatsirTe tatsirTe tatsirTe tatsirTe tatsirT X0 1 2 /KLCT2 /KLCT3 /KLCT6 /KLCT2 /KLCTK LCT6 /KLCT 01 0 z HM6.66z HM001 6.66 zHM zHM3.33z HM84 813.41 zHM 3.33 zHM 011 z HM001z HM001 6.66 zHM zHM3.33z HM84 813.41 zHM 3.33 zHM 110 z HM331z HM331 6.66 zHM zHM3.33z HM84 813.41 zHM 3.33 zHM 111 z HM331z HM001 6.66 zHM zHM3.33z HM84 813.41 zHM 3.33 zHM Truth Table Byte 0: Control Register (1 = enable, 0 = disable) tiB# niPe maND WPn oitpircseD 7tiBD IdevreseR0 ) evitcanI/evitcA( 6tiBD IdevreseR0 ) evitcanI/evitcA( 5tiBD IdevreseR0 ) evitcanI/evitcA( 4tiBD IdevreseR0 ) evitcanI/evitcA( 3tiB murtcepSdaerpS )ffO=0/nO=1( 1) evitcanI/evitcA( 2tiB6 21 zHM841 ) evitcanI/evitcA( 1tiB5 20 zHM841 ) evitcanI/evitcA( 0tiB9 42 KLCUPC1 ) evitcanI/evitcA( Note: Reserved ID bits must be wirtten as "0". Byte 1: Control Register (1 = enable, 0 = disable) tiB# niPe maND WPn oitpircseD 7tiB6 37 MARDS1 ) evitcanI/evitcA( 6tiB7 36 MARDS1 ) evitcanI/evitcA( 5tiB9 35 MARDS1 ) evitcanI/evitcA( 4tiB0 44 MARDS1 ) evitcanI/evitcA( 3tiB2 43 MARDS1 ) evitcanI/evitcA( 2tiB3 42 MARDS1 ) evitcanI/evitcA( 1tiB5 41 MARDS1 ) evitcanI/evitcA( 0tiB6 40 MARDS1 ) evitcanI/evitcA( Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD) Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free during this transition, and only SDRAM will change. Note 2: "ICS RESERVED BITS" must be writtern as "O". Note3: Undefined bits can be written either as "1 or 0" tiBn oitpitcseDD WP 7tiB) 2etoN(tibdevreseRSCI 0 6tiB) 2etoN(tibdevreseRSCI 0 5tiB) 2etoN(tibdevreseRSCI 0 4tiB) 2etoN(tibdevreseRSCI 0 3tiB) 2etoN(tibdevreseRSCI 0 2tiB) 3etoN(tibdenifednU X 1tiB) 3etoN(tibdenifednU X 0tiB 0tiB0 SF1 SF KLCUPC zHM MARDS zHM 66V3 zHM KLCICP zHM CIPAOI zHM 1etoN Byte 2: Control Register (1 = enable, 0 = disable) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 3. Undefined bit can be wirtten with either a "1" or "0". tiB# niPe maND WPn oitpircseD 7tiB9 ) PGA(2-66V31 ) evitcanI/evitcA( 6tiB0 25 KLCICP1 ) evitcanI/evitcA( 5tiB9 14 KLCICP1 ) evitcanI/evitcA( 4tiB8 13 KLCICP1 ) evitcanI/evitcA( 3tiB6 12 KLCICP1 ) evitcanI/evitcA( 2tiB5 11 KLCICP1 ) evitcanI/evitcA( 1tiB3 10 KLCICP1 ) evitcanI/evitcA( 0tiB- t ibdenifednUX ) evitcanI/evitcA(

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Byte 4: Reserved Register (1 = enable, 0 = disable) Byte 5: Reserved Register (1 = enable, 0 = disable) tiB# niPe maND WPn oitpircseD 7tiB- d evreseR0 ) evitcanI/evitcA( 6tiB- d evreseR0 ) evitcanI/evitcA( 5tiB- d evreseR0 ) evitcanI/evitcA( 4tiB- d evreseR0 ) evitcanI/evitcA( 3tiB- d evreseR0 ) evitcanI/evitcA( 2tiB- d evreseR0 ) evitcanI/evitcA( 1tiB- d evreseR0 ) evitcanI/evitcA( 0tiB- d evreseR0 ) evitcanI/evitcA( tiB# niPe maND WPn oitpircseD 7tiB- d evreseR0 ) evitcanI/evitcA( 6tiB- d evreseR0 ) evitcanI/evitcA( 5tiB- d evreseR0 ) evitcanI/evitcA( 4tiB- d evreseR0 ) evitcanI/evitcA( 3tiB- d evreseR0 ) evitcanI/evitcA( 2tiB- d evreseR0 ) evitcanI/evitcA( 1tiB- d evreseR0 ) evitcanI/evitcA( 0tiB- d evreseR0 ) evitcanI/evitcA( Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default Group Timing Relationship Table 1 puorGz HM66UPC zHM001MARDS zHM001UPC zHM001MARDS zHM331UPC zHM001MARDS zHM331UPC zHM331MARDS tesffOe cnareloTt esffOe cnareloTt esffOe cnareloTt esffOe cnareloT MARDSotUPCs n5.2s p005s n0.5s p005s n0.0s p005s n57.3s p005 66V3otUPCs n5.7s p005s n0.5s p005s n0.0s p005s n0.0s p005 66V3otMARDSs n0.0s p005s n0.0s p005s n0.0s p005s n57.3s p005 TOD&BSUh cnysAA /Nh cnysAA /Nh cnysAA /Nh cnysAA /N

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Absolute Maximum Ratings Core Supply Voltage 4.6 V I/O Supply Voltage 3.6V Logic Inputs GND –0.5 V to V DD +0.5 V Ambient Operating Temperature 0°C to +70°C Storage Temperature –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2V DD+0.3 V Input Low Voltage V IL VSS-0.3 0.8 V Input High Current I IH VIN = VDD -5 5 µA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 2 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 -100 CL = 0 pF; Select @ 66 MHz 97 115 CL = 0 pF; Select @ 100 MHz 91 110 CL = 0 pF; Select @ 133 MHz 100 165 CL = Max loads; Select @ 66 MHz 295 330 CL = Max loads; Select @ 100 MHz 280 320 CL = Max loads; Select @ 133 MHz 300 395 CL = 0 pF; Select @ 66 MHz 16 19 CL = 0 pF; Select @ 100 MHz 25 35 CL = 0 pF; Select @ 133 MHz 26 40 CL = Max loads; Select @ 66 MHz 19 30 CL = Max loads; Select @ 100 MHz 34 50 CL = Max loads; Select @ 133 MHz 40 70 IDD3.3PD CL = Max loads 220 400 IDD.25PD Input address VDD or GND <1 10 Input Frequency F i VDD = 3.3 V 12 14.318 16 MHz Pin Inductance L pin 7n H CIN Logic Inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 27 45 pF Transition time1 Ttrans To 1st crossing of target frequency 5 ms Settling time1 Ts From 1st crossing to 1% target frequency 5 ms Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target frequency 5 ms tPZH,tPZL Output enable delay (all outputs) 1 10 ns tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns 1Guaranteed by design, not 100% tested in production. Delay1 mA mA Input Capacitance1 IDD2.5OP µAPowerdown Current Operating Supply Current Input Low Current µA mA mA IDD3.3OP

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Electrical Characteristics - CPU TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP2B 1 VO = VDD*(0.5) 13.5 22 45 Ω Output Impedance R DSN2B 1 VO = VDD*(0.5) 13.5 23 45 Ω Output High Voltage V OH2B IOH = -1 mA 2 V Output Low Voltage V OL2B IOL = 1 mA 0.4 V VOH @ MIN = 1.0 V -27 -68 VOH @ MAX = 2.375 V -9 -27 VOL @ MIN = 1.2 V 27 54 VOL @ MAX = 0.3 V 11 30 Rise Time1 Fall Time1 VT = 1.25 V, 66, 100 MHz 45 50 55 VT = 1.25 V, 133 MHz 45 53 55 Skew window1 tsk2B VT = 1.25 V 118 175 ps Jitter, Cycle-to-cycle1 tjcyc-cyc2B VT = 1.25 V 148 250 ps 1Guaranteed by design, not 100% tested in production. %dt2BDuty Cycle1 mA mA Output High Current Output Low Current IOH2B IOL2B Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP1 1 VO = VDD*(0.5) 12 17 55 Ω Output Impedance R DSN1 1 VO = VDD*(0.5) 12 18 55 Ω Output High Voltage V OH1 IOH = -1 mA 2.4 V Output Low Voltage V OL1 IOL = 1 mA 0.55 V VOH @ MIN = 1.0 V -33 -108 VOH @ MAX = 3.135 V -9 -33 VOL @ MIN = 1.95 V 30 95 VOL @ MAX = 0.4 V 29 38 Rise Time1 Fall Time1 Duty Cycle1 dt1 VT = 1.5 V 45 50 55 % Skew window1 tsk1 VT = 1.5 V 82 175 ps Jitter, Cycle-to-cycle1 tjcyc-cyc1 VT = 1.5 V 123 500 ps 1Guaranteed by design, not 100% tested in production. Output High Current Output Low Current mA mA IOH1 IOL1

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Electrical Characteristics - IOAPIC TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP4B 1 VO = VDD*(0.5) 9 21.5 30 Ω Output Impedance R DSN4B 1 VO = VDD*(0.5) 9 23 30 Ω Output High Voltage V OH4B IOH = -1 mA 2 V Output Low Voltage V OL4B IOL = 1 mA 0.4 V VOH @ MIN = 1.0 V -27 -68 VOH @ MAX = 2.375 V -9 -27 VOL @ MIN = 1.2 V 27 54 VOL @ MAX = 0.3 V 11 30 Rise Time1 Fall Time1 Duty Cycle1 dt4B VT = 1.25 V 45 50 55 % Jitter, Cycle-to-cycle1 tjcyc-cyc4B VT = 1.25 V 123 500 ps 1Guaranteed by design, not 100% tested in production. Output High Current IOH4B mA Output Low Current IOL4B mA Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP3 1 VO = VDD*(0.5) 10 14 24 Ω Output Impedance R DSN3 1 VO = VDD*(0.5) 10 18 24 Ω Output High Voltage V OH3 IOH = -1 mA 2.4 V Output Low Voltage V OL3 IOL = 1 mA 0.4 V VOH @ MIN = 2.0 V -54 -92 VOH @ MAX = 3.135 V -16 -46 VOL @ MIN = 1.0 V 54 68 VOL @ MAX = 0.4 V 29 53 Rise Time1 tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 1 1.6 ns Fall Time1 Duty Cycle1 dt3 VT = 1.5 V 45 52 55 % Skew window1 tsk3 VT = 1.5 V 164 250 ps 1Guaranteed by design, not 100% tested in production. mA mA Output High Current Output Low Current IOH3 IOL3 250Jitter, Cycle-to-cycle1 tjcyc-cyc3 psVT = 1.5 V, 66, 100 MHz 180

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP1 1 VO = VDD*(0.5) 12 14 55 Ω Output Impedance R DSN1 1 VO = VDD*(0.5) 12 18 55 Ω Output High Voltage V OH1 IOH = -1 mA 2.4 V Output Low Voltage V OL1 IOL = 1 mA 0.55 V VOH @ MIN = 1.0 V -33 -106 VOH @ MAX = 3.135 V -14 -33 VOL @ MIN = 1.95 V 30 94 VOL @ MAX = 0.4 V 29 38 Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1.3 2 ns Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.4 2 ns Duty Cycle1 dt1 VT = 1.5 V 45 52 55 % Skew window1 tsk1 VT = 1.5 V 304 500 ps Jitter, Cycle-to-cycle1 tjcyc-cyc1 VT = 1.5 V 170 500 ps 1Guaranteed by design, not 100% tested in production. Output High Current IOH1 mA Output Low Current IOL1 mA Electrical Characteristics - REF, 48MHz_0 (Pin 25) TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP5 1 VO = VDD*(0.5) 20 32.6 60 Ω Output Impedance R DSN5 1 VO = VDD*(0.5) 20 31 60 Ω Output High Voltage V OH15 IOH = -1 mA 2.4 V Output Low Voltage V OL5 IOL = 1 mA 0.55 V VOH @ MIN = 1.0 V -29 -54 VOH @ MAX = 3.135 V -11 -23 VOL @ MIN = 1.95 V 29 54 VOL @ MAX = 0.4 V 16 27 Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V 0.4 1.4 4 ns Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V 0.4 1.7 4 ns Duty Cycle1 dt5 VT = 1.5 V 45 53 55 % Jitter, Cycle-to-cycle1 tjcyc-cyc5 VT = 1.5 V, Fixed clocks 215 500 ps Jitter, Cycle-to-cycle1 tjcyc-cyc5 VT = 1.5 V, Ref clocks 930 1000 ps 1Guaranteed by design, not 100% tested in production. Output High Current IOH5 mA Output Low Current IOL5 mA

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Electrical Characteristics - 48MHz_1 (Pin 26) TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP3 1 VO = VDD*(0.5) 10 16.7 24 Ω Output Impedance R DSN3 1 VO = VDD*(0.5) 10 18.4 24 Ω Output High Voltage V OH3 IOH = -1 mA 2.4 V Output Low Voltage V OL3 IOL = 1 mA 0.55 V VOH @ MIN = 2.0 V -54 -82 VOH @ MAX = 3.135 V -20 -46 VOL @ MIN = 1.0 V 54 95 VOL @ MAX = 0.4 V 28 53 Rise Time1 Fall Time1 Duty Cycle1 dt3 VT = 1.5 V 45 51 55 % Skew tsk3 VT = 1.5 V 116 250 ps Jitter, Cycle-to-cycle1 tjcyc-cyc3B VT = 1.5 V 196 500 ps 1Guaranteed by design, not 100% tested in production. Output High Current IOH3 mA Output Low Current IOL3 mA

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Group Offset Waveforms Cycle Repeats 0ns CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 133MHz SDRAM 100MHz 3.3V 66MHz PCI 33MHz IOAPIC 33MHz REF 14.318MHz USB 48MHz 10ns 20ns 30ns 40ns

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 1. The ICS clock generator is a slave/receiver, I 2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2C interface, the protocol is set to use only " Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. General I 2C serial interface information The information in this section assumes familiarity with I 2C programming. How to Write:

Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0) through byte 5
ICS clock will acknowledge each byte one at a time. How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit Notes: Controller (Host) ICS (Slave/Receiver) Start Bit Address D2(H ) ACK Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D3(H ) ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit How to Read:

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM 0395F—01/25/10 ICS9250-27 Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

Ordering Information

Designation for tape and reel packaging RoHS Compliant (Optional) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Example: XXXX y F - PPP LF - T MIN MAX MIN MAX A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 18.31 18.55 .720 .730 10-0034 0.635 BASIC 0.025 BASIC COMMON DIMENSIONS In Millimeters In Inches COMMON DIMENSIONS Reference Doc.: JEDEC Publication 95, MO-118 56-Lead, 300 mil Body, 25 mil, SSOP N SEE VARIATIONS SEE VARIATIONS D mm. D (inch) SYMBOL SEE VARIATIONS SEE VARIATIONS

Frequency Generator and Integrated Buffers for Celeron & PII/IIITM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G

435 Orchard Road

#20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2009 Integrated Device Technology , Inc. All rights reserved. Product specifications subject to change without notice. IDT, IC S, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA TM

Revision History

Rev. Issue Date Description Pa ge # C 8/17/2005 Added LF Or dering Informati on 14 D 10/25/2005 Removed "Contact ICS for an I C programming application" note reference. 13 E 9/11/2008 Corrected typo on pin# 28/29 pin description 2 F 1/25/2010 Updated document template

Product Information

9250YF-27LF-T specifications and overview.

Summary

Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

Description

Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

Source title 9250YF-27LF-T Datasheet(PDF) - Integrated Device Technology

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