ICS9220B IDT | Alldatasheet
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IDTTM Programmable RambusTM XDRTMClock Generator Programmable Rambus TM XDR TM Clock Generator DATASHEET 1427A — 01/26/10 General Description Features The ICS9220 clock generator provides Programmable clock signals to support the Rambus XDRTMmemory subsystem and Redwood logic interface. The ICS9220 has been optimized for 100MHz reference input that may or may not be modulated for spread spectrum. The ICS9220 provides 2 differential clock pairs in a space saving 28-pin TSSOP package and provides an off-the-shelf high-performance interface solution. Figure 1 shows the major components of the ICS9220 XDR Clock Generator. These include the a PLL, a Bypass Multiplexer and two differential output buffers. The outputs can be disabled by a logic low on the OE pin. An output is enabled by the combination of the OE pin being high, and 1 in its SMBus Output control register bit. The PLL receives a reference clock, CLK_INT/C and outputs a clock signal at a frequency equal to the input frequency times a multiplier. Table 2 shows the multipliers selectable via the SMBus interface. This clock signal is then fed to the differential output buffers to drive the enabled clocks. Disabled outputs are set to Hi-Z. The Bypass mode routes the input clock, CLK_INT/C, directly to the differential output buffers, bypassing the PLL. Up to four ICS9220 devices can be cascaded on the same SMBus. Table 3 shows the SMBus addressing and control for the four devices. Block Diagram 300 - 700 MHz clock source 2 open-drain differential output drives with short term jitter < 40ps Spread spectrum compatible Reference clock is differential or single-ended 100MHz SMBus programmability for: - frequency multiplier - output enable - operating mode Support systems where XDR subsystem is asynchronous to other system clocks 2.5V power supply PLL Bypass MUX RegA RegB CLK_INT CLK_INC SMBCLK OE OE OE BYPASS#/PLL SMBDAT AS1 AS2 ODCLK_C1 ODCLK_T1 ODCLK_C0 ODCLK_T0 Pin Configuration AVDD2.5 1 28 VDD2.5 AGND 2 27 GND IREFY 3 26 GND AGND 4 25 ODCLK_T0 CLK_INT 5 24 ODCLK_C0 CLK_INC 6 23 GND VDD2.5 7 22 VDD2.5 GND 8 21 VDD2.5 SMBCLK 9 20 GND SMBDAT 10 19 ODCLK_T1 OE 11 18 ODCLK_C1 AS1 12 17 GND AS2 13 16 GND BYPASS#/PLL 14 15 VDD2.5 ICS9220 28-Pin 4.4mm TSSOP
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 AVDD2.5 PWR 2.5V Analo g Power pin for Core PLL 2A G N D P W R A n a l o g Ground pin for Core PLL 3I R E F Y I N This pin establishes the reference current for the differential clock pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 4A G N D P W R A n a l o g Ground pin for Core PLL 5 CLK_INT IN "True" reference clock in put. 6 CLK_INC IN "Com plementary" reference clock input. 7 VDD2.5 PWR Power su pply, nominal 2.5V 8 GND PWR Ground pin.
9 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
11 OE IN Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 12 AS1 IN Default SMBus Address Select. 13 AS2 IN Default SMBus Address Select.
14 BYPASS#/PLL IN Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode 15 VDD2.5 PWR Power su pply, nominal 2.5V 16 GND PWR Ground pin. 17 GND PWR Ground pin. 18 ODCLK_C1 OUT "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. 19 ODCLK_T1 OUT "True" side of open drain differential clock output. This open drain output needs an external resistor network.. 20 GND PWR Ground pin. 21 VDD2.5 PWR Power su pply, nominal 2.5V 22 VDD2.5 PWR Power su pply, nominal 2.5V 23 GND PWR Ground pin. 24 ODCLK_C0 OUT "Complementary" side of open drain differential clock output. This open drain output needs an external resistor network.. 25 ODCLK_T0 OUT "True" side of open drain differential clock output. This open drain output needs an external resistor network.. 26 GND PWR Ground pin. 27 GND PWR Ground pin. 28 VDD2.5 PWR Power su pply, nominal 2.5V
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator General SMBus serial interface information for the ICS9220B How to Write:
- Controller (host) sends a start bit. Controller (host) sends the write address per table 3 ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address per table 3 ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address per table 3 ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit ICS (Slave/Receiver) T WR ACK ACK ACK ACK ACK P Byte N + X - 1 Data Byte Count = X Beginning Byte N stoP bit X Byte Index Block Write Operation Slave Address table 3 Beginning Byte = N WRite starT bit Controller (Host) T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge Ps t o P b i t Slave Address table 3 Index Block Read Operation Slave Address table 3 Beginning Byte = N ACK ACK Data Byte Count = X ACK ICS (Slave/Receiver)Controller (Host) X Byte ACK ACK
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator I2C Table: Output Enable Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Test Mode Reserved For Vendor RW Disable Enable 0 Bit 6 Reserved Reserved RW - - 0 Bit 5 Reserved Reserved RW - - 0 Bit 4 Reserved Reserved RW - - 0 Bit 3 Reserved Reserved RW - - 0 Bit 2 Reserved Reserved RW - - 0 Bit 1 ODCLK_T/C1 Output Control RW Disable Enable 1 Bit 0 ODCLK_T/C0 Output Control RW Disable Enable 1 I2C Table: Frequency Multiplier Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved R - - 0 Bit 6 AS1 SMBus Address Select R x Bit 5 AS2 SMBus Address Select R x Bit 4 Reserved Reserved R - - 0 Bit 3 Reserved Reserved R - - 0 Bit 2 Reserved Reserved R - - 0 Bit 1 Reserved Reserved R - - 0 Bit 0 Reserved Reserved R - - 0 I2C Table: Vendor & Revision ID Register Pin # Name Control Function Type 0 1 PWD Bit 7 RID 3 R - - 0 Bit 6 RID 2 R - - 0 Bit 5 RID 1 R - - 0 Bit 4 RID 0 R - - 0 Bit 3 VID 3 R - - 0 Bit 2 VID 2 R - - 0 Bit 1 VID 1 R - - 0 Bit 0 VID 0 R - - 1 I2C Table: Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved RW - - 0 Bit 6 Reserved Reserved RW - - 0 Bit 5 Reserved Reserved RW - - 0 Bit 4 Reserved Reserved RW - - 0 Bit 3 Reserved Reserved RW - - 0 Bit 2 Reserved Reserved RW - - 0 Bit 1 Reserved Reserved RW - - 0 Bit 0 Reserved Reserved RW - - 0 Revision ID Vendor ID Byte 3 Byte 2 Byte 1 Byte 0 See Table 2
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator I2C Table: Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved RW - - 0 Bit 6 Reserved Reserved RW - - 0 Bit 5 Reserved Reserved RW - - 0 Bit 4 Reserved Reserved RW - - 0 Bit 3 Reserved Reserved RW - - 0 Bit 2 Reserved Reserved RW - - 0 Bit 1 Reserved Reserved RW - - 0 Bit 0 Reserved Reserved RW - - 0 I2C Table: VCO Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Reserved Reserved RW - - 0 Bit 6 Reserved Reserved RW - - 0 Bit 5 Reserved Reserved RW - - 0 Bit 4 Reserved Reserved RW - - 0 Bit 3 M DIV3 RW 0 Bit 2 M DIV2 RW 0 Bit 1 M DIV1 RW 1 Bit 0 M DIV0 RW 0 I2C Table: VCO Frequency Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 Reserved RW - - 0 Bit 6 Reserved RW - - 0 Bit 5 N DIV5 RW 0 Bit 4 N DIV4 RW 0 Bit 3 N DIV3 RW 1 Bit 2 N DIV2 RW 0 Bit 1 N DIV1 RW 1 Bit 0 N DIV0 RW 0- The decimal representation of M and N Divider in Byte 5 and 6 will configure the PLL VCO frequency. VCO frequency = 100 x {[NDIV(5:0)+2]/[MDIV(3:0)+2]} Byte 5 Byte 4 Byte 6 N Divider Programming b(5:0) M Divider Programming b(3:0) The decimal representation of M and N Divider in Byte 5 and 6 will configure the PLL VCO frequency. VCO frequency = 100 x {[NDIV(5:0)+2]/[MDIV(3:0)+2]}
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator I2C Table: Byte Count Register Pin # Name Control Function Type 0 1 PWD Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 0 Bit 2 BC2 RW 1 Bit 1 BC1 RW 1 Bit 0 BC0 RW 1 Byte 7 Byte Count Programming Reserved Reserved Reserved Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes-
SMBus Multiplier Control register. Power up default is 4. Table 2. PLL Multiplier Programming Selection
or read operation. Table 3 shows the addresses for four ICS9220 devices on the same SMBus.
1 Bypass Mode
2 Power up default mode
Table 3. SMBus Device Addresses 8 bit SMBus Device Address Including Oper.
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator Absolute Maximum Ratings Supply Voltage 4.0 V Logic Inputs GND –0.5 V to V DD +0.5 V Ambient Operating Temperature -40°C to +85°C Storage Temperature –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. DC Characteristics - Outputs TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) SYMBOL CONDITIONS MIN TYP MAX UNITS tPU Power within spec to outputs within spec 3m s tCO SMBus or Mode Select transition to outputs valid and within spec 3m s VOX Measured as shown in Fig. 3 0.9 1.1 V VCOS Measured as shown in Fig. 3. Excludes over and undershoot. 300 350 mV VOL, ABS Measured at ODCLK_T/C pins 0.85 V VISET VDD = 2.3V, VOUT = 1V 0.98 1.02 V IOL/IREF IREF is equal to VISET/RRC. Tolerance of RRC <=+/-1%. 6.8 7 7.2 - IOL, ABS Measured at ODCLK_T/C pins with termination per Figure 3. 45 - mA VOLSMB IOL = 4 mA -0 . 4 V IOLSMB VOL= 0.8 V 6- m A IOZ Differential clock output pins - 50 µΑ Notes: 1 There is no output latency or glitches if a value written to an output register is the same as its current contents. Minimum current at VOLABS Output Voltage Swing (peak-to-peak singled ended) Absolute output low voltage Reference Voltage for swing control current Ratio of output low current to reference current at typical VDD2.5 Low-level output voltage SMBus Low-level output current SMBus Tristate output current PARAMETER Power up latency State transition latency1 Differential output crossing voltage
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator DC Characteristics - Inputs TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) SYMBOL CONDITIONS MIN TYP MAX UNITS VDD2.5, AVDD 2.375 2.625 V VIHCLK 0.6 0.95 V VILCLK -0.15 0.15 V VIXCLK 0.2 0.55 V VIXCLK 0.15 V VTH 0.35 0.5 VDD2.5 V VIHSE VTH + 0.3 2.625 V VILSE -0.15 VTH - 0.3 V VIH 1.4 2.625 V VIL -0.15 0.8 V VIHSMB 1.4 3.4652 V VILSMB -0.15 0.8 V Notes: When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2. Duty cycle of singled-ended CLK_IN is measured at VTH. This range of SMBus input high voltages allows the 9220 to co-exist with 3.3V, 2.5V and 1.8V devices on the same SMBus. PARAMETER Supply Voltage High-level input voltage Low-level input voltage Crossing point voltage Difference in crossing point voltage Input threshold voltage High-level input voltage for single-ended CLK_IN Low-level input voltage - SMBus CLK_INT, CLK_INC Singled-ended CLK_IN1 OE, AS1, AS2, BYPASS#/PLL SMBCLK, SMBDAT Low-level input voltage for single-ended CLK_IN High-level input voltage Low-level input voltage High-level input voltage - SMBus SYMBOL CONDITION MIN TYP MAX UNITS f = 400 to 635 MHz -4 0 ps f = 635 to 800 MHz -3 0 ps Tjcyc-cyc 100 ps DC 45 55 % tR, tF 20% to 80% of output voltage 140 300 ps tR-F 20% to 80% of output voltage - 100 ps ZOUT 2 VOL = 0.9 V 1000 - Ω Notes: AC Characteristics-Outputs PARAMETER1 Cycle-to-cycle Jitter Duty cycle Short term jitter (over 1 to 6 clock cycles) Guaranteed by design and characterization, not 100% tested in production Zout is defined at the output pins. Dynamic output impedance TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) Output rise and fall times Difference between output rise and fall time on same pin of a single device tJ
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units θJA Still air 120 °C/W θJA 1 m/s air flow 95 °C/W θJA 3 m/s air flow 80 °C/W Thermal Resistance Junction to Case θJC 20 °C/W Thermal Resistance Junction to Top of Case ΨJT Still Air 4.5 °C/W Maximum Case Temp 120 °C Thermal Resistance Junction to Ambient SYMBOL CONDITION MIN TYP MAX UNITS tCYCLEIN 91 0 1 1 n s tcyc-tcyc 2 185 ps dtin over 10,000 cycles 40 60 % tR, tF 20% to 80% of input voltage 175 700 ps tR-F 20% to 80% of input voltage - 150 ps fINM 3 30 33 kHz Triangular modulation 0.6 % Non-triangular modulation 0.54 % tsl(I) 20% to 80% of input voltage 1 4 V/ns CINCLK CLK_INT, CLK_INC 7 pF CIN VI = V DD2.5 or GND 10 pF tCYCLETST Bypass Mode 4 40 ns fSMB 10 100 kHz Notes: 5 Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV. m INDEX Measured at (VIH(nom) - VIL(nom))/2 and is the absolute value of the worst case deviation. Measured at crossing points for differential clock input or at VTH for single- ended clock input. If input modulation is used. Input modulation is not necessary. The amount of allowed spreading for non-triangular modulation is determined by the induced downstream tracking skew. Spread spectrum modulation index SMBus clock frequency CLK_INT cycle time Input Capacitance Input clock duty cycle Cycle-to-Cycle Jitter AC Characteristics-Inputs TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) PARAMETER CLK_INT/CLK_INC cycle time1 Input clock slew rate Input Capacitance5 CLK_INT/CLK_INC rise and fall time Difference between input rise and fall time on same pin of a single device Spread spectrum modulation frequency
current. The minimum current is zero. through RRC. So, the output low current can be estimated as I OL = 7/ RRC. specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors. = 54.9 Ohms and R RC = 200 Ohms can be used to match a 28 Ohm channel. Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel1
1 A different set of resistors is used in Figure 2 when testing
for maximum output current of the clock driver (IOLABS). Figure 1. Differential and single-ended reference clock inputs
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator INDEX AREA INDEX AREA 121 2 N D E1 E α SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C MIN MAX MIN MAX A- - 1 . 2 0 - - . 0 4 7 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D E E1 4.30 4.50 .169 .177 e L 0.45 0.75 .018 .030 N a 0 °8 °0 °8 ° VARIATIONS MIN MAX MIN MAX 28 9.60 9.80 .378 .386 10-0035 4.40 mm. Body, 0.65 mm. Pitch TSSOP 6.40 BASIC 0.252 BASIC
0.0256 BASIC
(173 mil) (25.6 mil) SYMBOL SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
Reference Doc.: JEDEC Publication 95, MO-153 N SEE VARIATIONS SEE VARIATIONS D mm. D (inch)
Ordering Information
Part / Order Number Shipping Packaging Package Temperature 9220BGILF Tubes 28-pin TSSOP -40 to +85°C 9220BGILFT Tape and Reel 28-pin TSSOP -40 to +85°C "LF" suffix to the part numbers are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate to the datasheet revision).
1427A — 01/26/10 ICS9220B Programmable RambusTM XDRTMClock Generator IDTTM Programmable RambusTM XDRTMClock Generator
Revision History
Rev. Issue Date Description Page # 0.1 12/10/2007 Initial release - 0.2 11/9/2009 Removed "Advanced Information" banner - A 1/26/2010 Removed watermarks; updated ordering information; released to final -