ICS9179-12 RENESAS | Alldatasheet

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Technical content

Systems, Inc. General Description Features ICS9179-12 0264E—12/09/08 Block Diagram PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

3 DIMM Buffer

The ICS9179-12 is a buffer intended for reduced pin count 2 - chip Intel BX chipset designs An I2C interface is included, enabling individual outputs to be turned on or off. With 13 outputs, up to 3 DIMMs are supported.

  • Thirteen high speed, low noise buffers, supports up to three SDRAM DIMMs.
  • Buffer outputs skew matched to within 250ps.
  • I2C Serial Configuration interface to allow individual OUTPUTs to be stopped low.
  • Multiple VDD, VSS pins for noise reduction
  • 3.3V±5% supply voltage
  • 28-pin SOIC and SSOP package
  • Propagation delay between 1 to 5.5ns
  • Operation to 133MHz at 3.3V±5% 28-Pin SOIC and SSOP * Internal pull-up resistor of 100K Ohms to 3.3V on indicated inputs Power Groups VDD (0:4), GND (0:4) = Power supply for OUTPUT buffer VDDI, GNDI = Power supply for I2C circuitry

0264E—12/09/08 Pin Descriptions Notes: 1. At power up all thirteen OUTPUTs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both have internal pull-up resistors with values above 100K Ohms. REBMUNNIPE MANNIPE PYTN OITPIRCSED ,11,01,7,6,3,2 ,32,22,91,81,21 72,62 )21:0(TUPTUOT UOs tuptuokcolC 1 9N I_FUBN Is reffubroftupnI 41A TADSO /II rofnipataD 2 yrtiucricC 3 51K LCSO /II rofnipkcolC 2 yrtiucricC 3 82,42,02,5,1) 4:0(DDVR WPs reffubTUPTUOrofylppusrewoPV3.3 52,12,71,8,4) 4:0(DNGR WPs reffubTUPTUOrofdnuorG 31I DDVR WPI rofylppusrewoPV3.3 2 cigollanretnidnayrtiucricC 61I DNGR WPI rofdnuorG 2 cigollanretnidnayrtiucricC

0264E—12/09/08 VDD This is the power supply to the internal core logic of the device as well as the clock output buffers for OUTPUT (0:12). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. OUTPUT (0:12) These Output Clocks are use to drive Dynamic RAM’s and are low skew copies of the CPU Clocks. The voltage swing of the OUTPUTs output is controlled by the supply voltage that is applied to VDD of the device, operates at 3.3 volts. I The SDATA and SCLOCK Inputs are used to program the device. The clock generator is a slave-receiver device in the I 2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I 2C specification in Philips I 2C Peripherals Data Handbook (1996) should be followed. BUF_IN Input for Fanout buffers (OUTPUT 0:12). VDDI This is the power supply to I 2C circuitry. Technical Pin Function Descriptions

0264E—12/09/08 Controller (Host) ICS (Slave/Receiver) Start Bit Address D2(H) ACK Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D3(H) ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit How to Read: 1. The ICS clock generator is a slave/receiver, I 2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2C interface, the protocol is set to use only " Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. General I 2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write:

  • Controller (host) sends a start bit.
  • Controller (host) sends the write address D2 (H)
  • ICS clock will acknowledge
  • Controller (host) sends a dummy command code
  • ICS clock will acknowledge
  • Controller (host) sends a dummy byte count
  • ICS clock will acknowledge
  • Controller (host) starts sending first byte (Byte 0) through byte 5
  • ICS clock will acknowledge each byte one at a time.
  • Controller (host) sends a Stop bit How to Read:
  • Controller (host) will send start bit.
  • Controller (host) sends the read address D3 (H)
  • ICS clock will acknowledge
  • ICS clock will send the byte count
  • Controller (host) acknowledges
  • ICS clock sends first byte (Byte 0) through byte 6
  • Controller (host) will need to acknowledge each byte
  • Controller (host) will send a stop bit Notes:

0264E—12/09/08 noitidnoC noitpmusnocylppusV3.3xaM sdaolpacetercsidxaM V564.3=DDV DNGroDDV=stupnicitatsllA edoMkcolCoN )DNGro1DDV-NI_FUB( I2 evitcAyrtiucriCC Am3 zHM66evitcA )zHM66.66=NI_FUB( Am032 zHM001evitcA )zHM00.001=NI_FUB( Am063 zHM331evitcA )zHM33.331=NI_FUB( Am005 Byte 1: OUTPUT Clock Register Functionality ICS9279-12 Power Consumption The values below are estimates of target specifications. #EO) 31:0(TUPTUO 0Z -iH 1N I_FUBX1 Serial Configuration Command Bitmaps Byte 0: OUTPUT Clock Register (Default=0) TIB# NIPD WPN OITPIRCSED 7tiB1 11 5 TUPTUO 6tiB0 11 4 TUPTUO 5tiB -1 devreseR 4tiB- 1 devreseR 3tiB 71 3TUPTUO 2tiB6 1 2TUPTUO 1tiB3 1 1 TUPTUO 0tiB2 1 0 TUPTUO Byte 2: OUTPUT Clock Register TIB# NIPD WPN OITPIRCSED 7tiB- 1 d evreseR 6tiB2 11 ) tcanI/tcA(21TUPTUO 5tiB- 1 d evreseR 4tiB- 1 d evreseR 3tiB- 1 d evreseR 2tiB- 1 d evreseR 1tiB- 1 d evreseR 0tiB- 1 d evreseR Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default TIB# NIPD WPN OITPIRCSED 7tiB7 21 ) tcanI/tcA(11TUPTUO 6tiB6 21 ) tcanI/tcA(01TUPTUO 5tiB3 21 ) tcanI/tcA(9TUPTUO 4tiB2 21 ) tcanI/tcA(8TUPTUO 3tiB- 1 d evreseR 2tiB- 1 d evreseR 1tiB9 11 ) tcanI/tcA(7TUPTUO 0tiB8 11 ) tcanI/tcA(6TUPTUO

0264E—12/09/08 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input & Supply TA = 0 - 70C; Supply V oltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High V oltage V IH 2V DD +0.3 V Input Low V oltage V IL VSS-0.3 0.8 V Input High Current I IH VIN = VDD 5u A Input Low Current I IL VIN = 0 V ; Inputs with no pull-up resistors -5 uA IIL VIN = 0 V ; Inputs with 100K pull-up resistors -60 uA IDD1 CL = 0 pF; FIN @ 66MHz 120 mA Operating I DD2 CL = 0 pF; FIN @ 100MHz 180 mA IDD3 CL = 0 pF; FIN @ 133MHz 250 mA Supply Current I DD4 CL = 30 pF; RS=33Ω; FIN @ 66MHz 230 mA IDD5 CL = 30 pF; RS=33Ω; FIN @ 100MHz 360 mA IDD6 CL = 30 pF; RS=33Ω; FIN @ 133MHz 500 mA Input frequency F i VDD = 3.3 V; All Outputs Loaded 10 133 MHz Input Capacitance CIN Logic Inputs 5 pF G uarenteed by design, not 100% tested in production.

0264E—12/09/08 Electrical Characteristics - Outputs TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL C ONDITIONS MIN TYP MAX UNITS Output Impedance R DSP VO = VDD*(0.5) 10 24 Ω Output Impedance R DSN VO = VDD*(0.5) 10 24 Ω Output High Voltage V OH IOH = -30 mA 2.6 V Output Low Voltage V OL IOL = 23 mA 0.4 V Output High Current I OH VOH = 2.0 V -54 mA Output Low Current I OL VOL = 0.8 V 40 mA Rise Time1 Tr VOL = 0.4 V, VOH = 2.4 V 1.33 ns Fall Time1 Tf VOH = 2.4 V, VOL = 0.4 V 1.33 ns Duty Cycle1 Dt VT = 1.5 V 45 55 % Skew1 Tsk VT = 1.5 V 250 ps TPROP1 VT = 1.5 V 1 5.5 ns TPROP2 VT = 50% BIN to 10% OUT 1 5 ns Propagation1 TPROPEN VT = 1.5 V 1 8 ns TPROPDIS VT = 1.5 V 18 n s 1Guarenteed by design, not 100% tested in production.

0264E—12/09/08

28 Pin SSOP Package

Ds noitairaVeeS0 37 93.02 04.07 04.0 E5 02.09 02.02 12.0 e 6520.0 CSB H1 03.07 03.01 13.0 L5 20.00 30.07 30.0 Ns noitairaVeeS ∝ °0° 4° 8 9179yF-12LFT XXXX y F - PPPLFT Designation for tape and reel packaging Annealed Lead Free (optional, RoHs compliant part) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revison Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers)

Ordering Information

Example:

0264E—12/09/08 TNUOCDAELL 82 LNOISNEMID4 07.0 9179yM-12LFT XXXX y M - PPPLFT Designation for tape and reel packaging Annealed Lead Free (optional, RoHs compliant part) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Revison Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Example:

0264E—12/09/08

Revision History

Rev. Issue Date Description Page # E 12/9/2008 Removed ICS prefix from ordering information 8-9