9173B-01CS08LF

ICS9173B RENESAS | Alldatasheet

Document overview

• Manufacturer or author: mamiller
• PDF pages: 10

Technical content

Features

• Phase-detector/VCO circuit block
• Ideal for genlock system
• Reference clock range 12 kHz to 1 MHz for full output clock range
• Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions
• On-chip loop filter
• Single 5 V power supply
• Low power CMOS technology
• 8-pin SOIC package Block Diagram

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 2 ICS9173B REV D 012913 Pin Assignment Pin Descriptions Allowable Input Frequency to Output Frequency for ICS9173B-01 (in MHz) (ICS9173B-15 outputs run at exactly half of the ICS9173B-01 frequencies) FBIN IN GND VDD FS0 CLK1 OE CLK21 8 pin SOIC Pin Number Pin Name Pin Type Pin Description 1 FBIN Input Feedback input. 2 IN Input Input for reference sync pulse. 3 GND Power Ground. 4 FS0 Input Frequency select 0 input. 5 OE Input Output enable. 6 CLK1 Output Clock output 1. 7 VDD Power Power supply (+5 V). 8 CLK2 Output Clock output 2 (divided-by-2 from Clock 1). fOUT for FS = 0 f OUT for FS = 1 fIN (kHz) CLK1 Output CLK2 Output CLK1 Output CLK2 Output

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 3 ICS9173B REV D 012913 Using the ICS9173B in Genlock Applications Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video “genlock” (generator lock) circuit is required. The ICS9173B integrates the analog blocks which make the task much easier. In the complete video genlock circuit, the primary function of the ICS9173B is to provide the analog circuitry required to generate the video dot clock within a PLL. This application is illustrated in Figure 1. The input reference signal for this circuit is the horizontal synchronization (H-SYNC) signal. If a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. A video sync separator circuit, such as the National Semiconductor LM1881, can be used for this purpose. The clock feedback divider shown in Figure 1 is a digital divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. For example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. Hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: f OUT = fIN x N where N is external divide ratio Both input pins IN and FBIN respond only to negative-going clock edges of the input signal. The H-SYNC signal must be constant frequency in the 12 kHz to 1 MHz range and stable (low clock jitter) for creation of a stable output clock. The output hook-ups of the ICS9173B are dictated by the desired dot clock frequency. The primary consideration is the internal VCO which operates over a frequency range of 10 MHz to 75 MHz. Because of the selectable VCO output divider and the additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following Table lists these ranges and the corresponding device configuration. Note that both outputs, CLK1 and CLK2, are available during operation even though only one is fed back via the external clock divider. Pin 5, OE, tristates both CLK1 and CLK2 upon logic low input. This feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). When unused, inputs FS0 and OE must be tied to either GND (logic low) or VDD (logic high). Figure 1: Typical Application of ICS9173B in a Video Genlock System FS0 State Output Used Frequency/Range ICS9173B-01 Frequency/Range IcS9173B-15 0 CLK1 10 to 75 MHz 5 to 37.5 MHz 0 CLK2 5 to 37.5 MHz 2.5 to 18.75 MHz 1 CLK1 2.5 to 18.75 MHz 1.25 to 9.375 MHz 1 CLK2 1.25 to 9.375 MHz 0.625 to 4.6875 MHz

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 4 ICS9173B REV D 012913 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS9173B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70C Notes: 1. Duty cycle measured at 1.4 V. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. Item Rating Supply Voltage, VDD 7 V Storage Temperature -65 to +150 C Voltage on I/O Pins referenced to GND GND - 0.5 V to VDD + 0.5 V Junction Temperature 125 C Soldering Temperature 260 C Power Dissipation 0.5 Watts Parameter Min. Typ. Max. Units Operating Temperature under Bias -0 +70 C Power Supply Voltage (measured with respect to GND) +4.75 +5 V +5.25 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Supply Current IDD No load,50 MHz 20 50 mA Input Low Voltage V IH VDD = 5 V 0.8 V Input High Voltage V IL VDD = 5 V 2.0 V Input Low Current I IL VIN = 0V -5 µA Input High Current I IH VIN = VDD -5 5 µA Output Low Voltage V OL IOL = 8 mA 0.4 V Output High Voltage 1 VOH1 IOH = -1 mA VDD-0.4 V Output High Voltage 1 VOH2 IOH = -4 mA VDD-0.8 V Output High Voltage 1 VOH3 IOH = -8 mA 2.4 V

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 5 ICS9173B REV D 012913 Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70 C Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. I nput Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pix els. 3. CL K1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. 4. An App lication Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following thes e guidelines, the ICS9173B will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot v ariation. 5. Jitt er values are measured at frequencies > 25 MHz for IDT9173B-01, for ICS9173B-15, jitter is measured at frequency > 12.5 MHz. Parameter Symbol Conditions Min. Typ. Max. Units Output Clock Rise Time 1 ICLKr 10 ns Output Clock Fall Time 1 ICLKf 10 ns Output Rise Time 1 tr1 15 pF load, 0.8 to 2.0V 0.6 1.5 ns Output Rise Time 1 tr2 15 pF load, 20% to 80% VDD 1.3 3.0 ns Output Fall Time 1 tf1 15 pF load, 0.8 to 2.0V 0.6 1.5 ns Output Fall Time 1 tf2 15 pF load, 80% to 20% VDD 0.7 2.0 ns Output Duty Cycle 1 15 pF load 40 47 55 % One-Sigma Jitter 1, 5 T1S1 CLK1 frequency 3, 25 MHz 120 250 ps Jitter, Absolute 1, 5 TABS1 CLK1 frequency 3, 25 MHz -400 ±250 400 ps One-Sigma Jitter 1, 5 T1S2 CLK1 frequency < 25 MHz 1 % Jitter, Absolute 1, 5 TABS2 CLK1 frequency < 25 MHz 2 % Line-to-Line Jitter 1, Absolute 2 TLABS ±4 ns Input Frequency 1, IN or FBIN f IN see allowable fi below 12 1000 kHz CLK1 Frequency, -01 1, 3, 4 fCLK1 12 < fIN < 14 kHz 44 75 MHz 14 < fIN < 17 kHz 30 75 17 < fIN < 30 kHz 25 75 30 < fIN < 35 kHz 15 75 35 < fIN < 1000 kHz 10 75 CLK1 Frequency, -15 1, 3, 4 fCLK1 12 < fIN < 14 kHz 22 37.5 MHz 14 < fIN < 17 kHz 15 37.5 17 < fIN < 30 kHz 12.5 37.5 30 < fIN < 35 kHz 7.5 37.5 35 < fIN < 1000 kHz 5 37.5

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 6 ICS9173B REV D 012913 Thermal Characteristics Marking Diagram Notes: 1. L ine 1: truncated part number 2. YYW W is the last two digits of the year and week that the part was assembled. 3. “LOT” denotes the lot number. 4. “L ” suffix designates RoHS compliant package. Bo ttom mark: country of origin. Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W Thermal Resistance Junction to Case JC 40 C/W Thermal Resistance Junction to Top of Case JT Still air 20 C/W B01CS08L LOT YYWW

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 7 ICS9173B REV D 012913 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Shipping Packaging Package Temperature 9173B-01CS08LF Tubes 8-pin SOIC 0 to +70  C 9173B-01CS08LFT Tape and Reel 8-pin SOIC 0 to +70  C 9173B-15CS08LF Tubes 8-pin SOIC 0 to +70  C 9173B-15CS08LFT Tape and Reel 8-pin SOIC 0 to +70  C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0

VIDEO GENLOCK PLL CLOCK SYNTHESIZER IDT® VIDEO GENLOCK PLL 8 ICS9173B REV D 012913

Revision History

Rev. Originator Date Description of Change A R.Willner 09/23/08 New datasheet. B RDW 11/12/09 Released to final. C RDW 07/29/11 Corrected typographical errors on page 5 for rise/fall times D LPL 01/29/13 Added top-side device marking

© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER

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