91719YGLF-T

ICS91719 RENESAS | Alldatasheet

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Technical content

0506E—06/24/09 Block Diagram Pin Configuration 16-pin TSSOP Features:  ICS91719 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications. Generates an EMI optimized clock signal (EMI peak reduction of 7- 14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques.  ICS91719 focuses on the lower input frequency range of 14.318 to 80.00 MHz with a spread modulation of 20kHz to 40kHz. Specifications:  Supply Voltages: VDD = 3.3V ±0.3V  Frequency range: 14.318 MHz ≤ Fin ≥ 80 MHz  Cyc to Cyc jitter: <150ps  Output duty cycle 40/60% (worst case)  Guarantees +85°C operational condition.  16-pin TSSOP package 4.4mm body (173mils), 0.65 mm pitch  14.318 MHz crystal input or reference clock input  27MHz, 48MHz and 66MHz reference clock input Low EMI, Spread Modulating, Clock Generator ** Internal pull-down ^ Internal pull-up CLKCL REFOUT KOUTOUT PD#PD# SPREAD#SPREAD# CLKINCLKIN PLL1PLL1 SpreadSpread SpectrSpectrumum SDSDAATT REF_STOP AA SCLKSCLK FS_IN0:1 ControlControl LogicLogic Config.Config. Reg.Reg. REF Voltage Select Functionality Input Select Functionality Pin14 Pin15 REF Voltage 0 0 N/A 0 1 1.8V 1 0 2.5V 1 1 3.3V FS_IN1 FS_IN0 MHZ Default Spread % 0 0 14.318 in 27.00 out -0.8% downspr ead 0 1 14.318 in/out -0.8% downspr ead 1 0 27.00 in/out -0.8% downspr ead 1 1 48.00 in/out 66. 66 in/out -0.8% downspread GND 1 16 VDDREF X1 _CLKIN 2 15 VDDREF_SEL_2.5V/3.3V# ^ X2 3 14 REF_OUT/VDDREF_SEL_1.8V * * GNDA 4 13 **REF_Stop VDDA 5 12 ^PD# VDD 6 11 SCLK GND 7 10 SDATA * * C LKOUT/FS_IN0 8 9 ^SPREAD_ENABLE/FS_IN1

0506E—06/24/09 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION

1 GND POWER Ground pin for 3V outputs

2 X1 _CLKIN INPUT Crystal input or CLOCKIN input

3 X2 OUTPUT Crystal output

4 GNDA POWER Analog ground

5 VDDA POWER Analog power supply for 3V

6 VDD POWER Power supply for 3V

7 GND POWER Ground pin for 3V outputs

CLKOUT OUTPUT Modulated clock output FS_IN0 INPUT Latched input for input frequency select Spread enable pin Latched input for input frequency select

10 SDATA INPUT Data pin for I2C circuitry 5V tolerant

11 SCLK INPUT Clock pin for I2C circuitry 5V tolerant

12 ^PD# I NPUT Power down 13 **REF_Stop INPUT Stop control for REF_CLOCK output STOP:1, RUNNING:0 14 REF_OUT/VDDREF_SEL_1.8V * * INPUT/OUTPUT REF_CLOCK output 15 VDDREF_SEL_2.5V/3.3V# ^ POWER REF_CLOCK power supply voltage select

16 VDDREF POWER Power supply for REF_CLOCK

^internal pull-up **internal pull-down 9 ^SPREAD_ENABLE FS_IN1 INPUT

0506E—06/24/09 Table 1: Frequency Configuration Table (See I2C Byte 0) FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd % 00000 0 . 6 0 00001 0 . 8 0 00010 1 . 0 0 00011 1 . 2 5 00100 1 . 5 0 00101 2 . 0 0 00110 0 . 5 0 00111 1 . 0 0 01000 0 . 6 0 01001 0 . 8 0 01010 1 . 0 0 01011 1 . 2 5 01100 1 . 5 0 01101 1 . 7 5 01110 2 . 0 0 01111 2 . 5 0 10000 3 . 0 0 10001 0 . 3 0 10010 0 . 4 0 10011 0 . 5 0 10100 0 . 7 0 10101 1 . 0 0 10110 1 . 2 0 10111 1 . 5 0 11000 0 . 6 0 11001 0 . 8 0 11010 1 . 0 0 11011 1 . 2 5 11100 1 . 5 0 11101 2 . 0 0 11110 0 . 5 0 11111 1 . 0 0 DOWN SPREAD (-) Center Spread (+/-) DOWN SPREAD (-) CENTER SPREAD (+/-) 48in/48ou t 66in/66ou t DOWN SPREAD (-) Center Spread (+/-) 14in/27out 14in/14ou t 27in/27ou t

0506E—06/24/09 1. The ICS clock generator is a slave/receiver, I 2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol . 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2C interface, the protocol is set to use only " Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. Controller (Host) ICS (Slave/Receiver) Start Bit Address D2(H) ACK Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 ACK Stop Bit How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D3(H) ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit How to Read: General I 2C serial interface information The information in this section assumes familiarity with I 2C programming. For more information, contact ICS for an I 2C programming application note. How to Write:  Controller (host) sends a start bit.  Controller (host) sends the write address D2 (H)  ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0) through byte 6  ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit How to Read:  Controller (host) will send start bit.  Controller (host) sends the read address D3 (H)  ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 7  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit Notes:

0506E—06/24/09 Byte 0: Byte 1: Byte 2: BYTE

0 Pin # Name Control Function 0 1 PWD

Bit 7 -F S 0 S pread/FS0 RW 1 Bit 6 -F S 1 S pread/FS1 RW 0 Bit 5 FS2 S pread/FS2 RW 0 Bit 4 FS3 S pread/FS3 R 0 Bit 3 FS4 FS4 R/R Bit 2 PD# Tri_Sate PD# Tri_Sate RW Hi-Z LOW 1 Bit 1 Spread Enable S pread Enable RW OFF ON 1 Bit 0 HW/SW Control Spread Spectrum Control FS 3:4 Hard/Software Select RW HW SW 0 Affected Pin TYPE Bit Control BYTE

1 Pin # Name Control Function 0 1 PWD

Bit 7 Reserved Reserved R - - 1 Bit 6 - SLEW Slew Rate REF-OUT RW Nominal Fast 1 Bit 5 FS-IN_1 Readback FS-IN_1 Readback RW Not Freerun Freerun 1 Bit 4 FS-IN_0 Readback FS-IN_0 Readback RW Nominal Fast 1 Bit 3 SLEW Slew Rate CLK-OUT RW Nominal Fast 1 Bit 2 CLK_OUT_Enable CLK_OUT_Enable RW Disable Enable 1 Bit 1 REF_OUT_Enable REF_OUT_Enable RW Disable Enable 1 Bit 0 Reserved Reserved R - - 1 TYPE Bit ControlAffected Pin BYTE

2 Pin # Name Control Function 0 1 PWD

Bit 7 x - RESERVED - - - 1 Bit 6 x RESERVED RESERVED RW Disable E nable 1 Bit 5 x RESERVED RESERVED RW Disable E nable 1 Bit 4 x RESERVED RESERVED RW Disable E nable 1 Bit 3 x RESERVED RESERVED RW Disable E nable 1 Bit 2 x RESERVED RESERVED RW Disable E nable 1 Bit 1 x RESERVED RESERVED RW Disable E nable 1 Bit 0 x RESERVED RESERVED RW Disable E nable 1 Affected Pin TYPE Bit Control

0506E—06/24/09 Byte 3: Byte 4: Byte 5: BYTE

3 Pin # Name Control Function 0 1 PWD

Bit 7 X RESERVED RESERVED RW Disable E nable 1 Bit 6 X RESERVED RESERVED RW Disable E nable 1 Bit 5 X RESERVED RESERVED RW Freerun Not Freerun 1 Bit 4 X RESERVED RESERVED RW Freerun Not Freerun 1 Bit 3 x RESERVED RESERVED RW Freerun Not Freerun 1 Bit 2 X RESERVED RESERVED RW Disable E nable 1 Bit 1 X RESERVED RESERVED RW Disable E nable 1 Bit 0 X RESERVED RESERVED RW Disable E nable 1 Affected Pin Bit Control TYPE BYTE

4 Pin # Name Control Function 0 1 PWD

Bit 7 X RESERVED RESERVED RW Disable E nable 1 Bit 6 X RESERVED RESERVED RW Disable E nable 1 Bit 5 X RESERVED RESERVED RW Disable E nable 1 Bit 4 X RESERVED RESERVED RW Disable E nable 1 Bit 3 X RESERVED RESERVED RW Disable E nable 1 Bit 2 X RESERVED RESERVED RW Disable E nable 1 Bit 1 X RESERVED RESERVED RW Disable E nable 1 Bit 0 X RESERVED RESERVED RW Disable E nable 1 TYPE Bit ControlAffected Pin BYTE

5 Pin # Name Control Function 0 1 PWD

Bit 7 X RESERVED RESERVED - - - 1 Bit 6 X RESERVED RESERVED - - - 1 Bit 5 X RESERVED RESERVED - - - 1 Bit 4 X RESERVED RESERVED - - - 1 Bit 3 X RESERVED RESERVED RW Disable E nable 1 Bit 2 X RESERVED RESERVED RW Disable E nable 1 Bit 1 X RESERVED RESERVED RW Disable E nable 1 Bit 0 X RESERVED RESERVED RW Disable E nable 1 Affected Pin TYPE Bit Control

0506E—06/24/09 Byte 6: BYTE

6 Pin # Name Control Function 0 1 PWD

Bit 7 X Revision ID Bit 3 (Reserved) R- -1 Bit 6 X Revision ID Bit 2 (Reserved) R- -1 Bit 5 X Revision ID Bit 1 (Reserved) R- -1 Bit 4 X Revision ID Bit 0 (Reserved) R- -1 Bit 3 X Vendor ID Bit 3 (Reserved) R- -1 Bit 2 X Vendor ID Bit 2 (Reserved) R- -1 Bit 1 X Vendor ID Bit 1 (Reserved) R- -1 Bit 0 X Vendor ID Bit 0 (Reserved) R- -1 Affected Pin TYPE Bit Control

0506E—06/24/09 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Ambient Operating Temperature under Bias. -55 to +125 °C Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2V DD + 0.3 V Input Low Voltage V IL VSS - 0.3 0.8 V Input High Current I IH VIN = V DD -5 5 mA Input Low Current I IL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA Powerdown Current I DD3.3PD 35 mA Input Frequency Fi V DD = 3.3 V 14.318 MHz Input Crystal Frequency F CYI 14.318 Typ + 10% MHz Input Clock Frequency F CLKI 80 MHz Pin Inductance Lpin 7n H Input Ca pacitance 1 CIN Logic Inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 27 36 45 pF Transition time 1 Ttrans To 1st crossin g of tar get fre quenc y 3m s Settlin g time 1 Ts From 1st crossin g to 1% tar get fre quenc y 3m s Clk Stabilization 1 TSTAB From V DD = 3.3 V to 1% target frequency 1 3 ms Delay 1 tPZH,tPZL Output enable delay (all outputs) 1 10 ns 1Guaranteed b y desi gn, not 100% tested in production.

0506E—06/24/09 Electrical Characteristics - REF TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 20 48 60 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.4 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 1 1.25 2 ns Fall Time t f1 1 VOH = 2.4 V, VOL = 0.4 V 1 1.3 2 ns Duty Cycle dt1 1 VT = 1.5 V 45 53 55 % Jitter tjcyc-cyc 1 VT = 1.5 V 170 300 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage V OH3 IOH = -1 mA 2.4 V Output Low Voltage V OL3 IOL = 1 mA 0.4 Rise Time tr3 V OL = 0.41V, VOH = 0.86V 0.5 0.7 1 ns Fall Time tf3 V OH = 0.86V VOL = 0.41V 0.5 0.8 1 ns Duty Cycle dt3 measurement from differential waveform - 0.35V to +035V 45 51 55 % Jitter, Cycle to cycle tjcyc-cyc

1 VT = 50% 76 150 ps

1Guaranteed by design, not 100% tested in production.

2 IOWT

can be varied and is selectable thru the MULTSEL pin.

0506E—06/24/09 4.40mm Body, .65mm pitch

Ordering Information

N D E1 E α SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C MIN MAX MIN MAX A -- 1.20 -- .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D E E1 4.30 4.50 .169 .177 e L 0.45 0.75 .018 .030 N a0 ° 8 ° 0 ° 8 ° VARIATIONS MIN MAX MIN MAX 16 4.90 5.10 .193 .201 10-0035 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS SEE VARIATIONS 6.40 BASIC 0.252 BASIC 0.65 BASIC 0.0256 BASIC SEE VARIATIONS SEE VARIATIONS N D mm. D (inch) Reference Doc.: JEDEC Publication 95, MO-153 Example: Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type XXXX y G LF- T 1719BGLF YYWW Line 1. Part number. Line 3. YYWW = date code Marking Diagram

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