908E626_09 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • High performance M68HC08EY16 core
  • 1 6 K bytes of on-chip flash memory
  • 512 bytes of RAM
  • Internal clock generation module
  • Two 16-bit, 2-channel timers
  • 10-Bit Analog-to-Digital converter
  • Four low R DS(ON) half-bridge outputs
  • 13 microcontroller I/Os
  • Pb-free packaging designated by suffix code EK VSS EVSS VSSA VREFL VDD EVDD VDDA VREFH LIN FGEN PTD1/TACH1 PTE1/RXD RXD PTD0/TACH0/BEMF PTB1/AD1 BEMF SS IRQ_A RST_A IRQ RST Port C I/Os Port B I/Os Port A I/Os HVDD HB4 HB3 HB2 HB1 EPGND[1:2] VSUP[1:3] 908E626 908E626 Simplified Application Diagram Switchable Internal VDD Output Microcontroller Ports Bipolar Step Motor N S

Figure 1. 908E626 Simplified Application Diagram

10 Bit Analog-to-

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Figure 2. Figure 1. 908E626 Simplified Internal Block Diagram

Figure 3. 908E626 Pin Connections Table 1. 908E626 PIN DEFINITIONS A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. shared with other functional modules in the MCU. shared with other functional modules in the MCU. This pin is an asynchronous external interrupt input pin. driven low when any internal reset source is asserted. shared with other functional modules in the MCU.

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NC No Connect Not connected. shared with other functional modules in the MCU. MCU operates from a single power supply. shared with other functional modules in the MCU. MCU 51 FLSVPP Test Pin For test purposes only. Do not connect in the application. Analog 17 RST_A Internal Reset This pin is the bidirectional reset pin of the analog die. Analog 19 SS Slave Select This pin is the SPI slave select pin for the analog chip. Analog 20 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver. drivers, DC motor drivers, or as high side and low side switches. Power Supply Pins These pins are device power supply pins. Power Ground Pins These pins are device power ground connections. requiring a regulated 5.0V supply; e.g., 3 pin Hall-effect sensors. (microcontroller and sensors). This pin is the output of LIN transceiver. heat from the chip to the PCB board. A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 908E626

ELECTRICAL CHARACTERISTICS

Table 2. MAXIMUM RATINGS

  1. Transient capability for pulses with a time of t < 0.5 sec.
  2. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100pF, RZAP = 1500Ω).
  3. ESD2 testing is performed in ac cordance with the Machine Model (CZAP = 200pF, RZAP = 0Ω).
  4. ESD3 testing is performed in accordanc e with Charge Device Model, robotic (CZAP = 4.0pF).
  5. The limiting factor is junction temperat ure, taking into account the power dissipation, thermal resistance, and heat sinking.
  6. The temperature of analog and MCU die is strongly linked via t he package, but can differ in dynamic load conditions, usually because
  7. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

  1. STOP mode current will increase if V SUP exceeds 15V.
  2. This parameter is guaranteed by process monitoring but is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 908E626 STATIC ELECTRICAL CHARACTERISTICS SYSTEM RESETS AND INTERRUPTS High Voltage Reset Threshold Hysteresis VHVRON VHVRH 1.5 V Low Voltage Reset Threshold Hysteresis VLVRON VLVRH 3.6 4.0 100 4.7 V mV High Voltage Interrupt Threshold Hysteresis VHVION VHVIH 17.5 1.0 V Low Voltage Interrupt Threshold Hysteresis VLVION VLVIH 6.5 0.4 8.0 V High Temperature Reset (11) Threshold Hysteresis TRON TRH 5.0 170 High Temperature Interrupt (12) Threshold Hysteresis TION TIH 5.0 160 VOLTAGE REGULATOR Normal Mode Output Voltage IOUT = 60mA, 6.0V < VSUP < 18V VDDRUN 4.75 5.0 5.25 V Load Regulation IOUT = 80mA, VSUP = 9.0V VLR – – 100 mV STOP Mode Output Voltage (Maximum Output Current 100μA)(10) VDDSTOP 4.45 4.7 5.0 V Notes 10. Tested to be VLVRON < VDDSTOP 11. This parameter is guaranteed by process monitoring but is not production tested. 12. High Temperature Interrupt (HTI) threshold is linked to High Temperature Reset (HTR) threshold (HTR = HTI + 10°C). Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER Output Low Level TXD LOW, 500Ω Pull-up to VSUP VLIN-LOW – – 1.4 V Output High Level TXD HIGH, IOUT = 1.0μA VLIN-HIGH VSUP - 1.0 – – V Pullup Resistor to VSUP RSLAVE 20 30 60 kΩ Leakage Current to GND Recessive State (- 0.5V < VLIN < VSUP) IBUS_PAS_REC 0.0 – 20 μA Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18V Including Internal Pullup Resistor, VLIN @ +18V IBUS_NO_GND IBUS - 600 μA LIN Receiver Recessive Dominant Threshold Input Hysteresis VIH VIL VITH VIHY 0.6VLIN 0.01V SUP V SUP / 2 VSUP 0.4VLIN 0.1VSUP V LIN Wake-up Threshold VWTH – VSUP / 2 – V HALF-bridge OUTPUTS (HB1 : HB4) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0A High Side Low Side RDS(ON)HB_HS RDS(ON)HB_LS 425 400 500 500 mΩ High Side Over-current Shutdown IHBHSOC 3.0 – 7.5 A Low Side Over-current Shutdown IHBLSOC 2.5 – 7.5 A Low Side Current Limitation @ TJ = 25°C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) I CL1 ICL2 ICL3 ICL4 ICL5 210 300 450 600 260 370 550 740 315 440 650 880 mA Half-bridge Output HIGH Threshold for BEMF Detection VBEMFH – - 30 0.0 V Half-bridge Output LOW Threshold for BEMF Detection VBEMFL – - 60 - 5.0 mV Hysteresis for BEMF Detection VBEMFHY – 30 – mV Low Side Current-to-Voltage Ratio (VADOUT [V] / IHB [A]) CSA = 1 CSA = 0 RATIOH RATIOL 7.0 1.0 12.0 2.0 14.0 3.0 V/A noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 908E626 STATIC ELECTRICAL CHARACTERISTICS SWITCHABLE VDD OUTPUT (HVDD) Over-current Shutdown Threshold IHVDDOCT 24 30 40 mA VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP / VADOUT) RATIOVSUP 4.8 5.1 5.35 – INTERNAL DIE TEMPERATURE SENSOR Voltage / Temperature Slope STTOV – 19 – mV/ °C Output Voltage @ 25°C VT25 1.7 2.1 2.5 V noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS MICROCONTROLLER PARAMETRICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS microcontroller chip. Characteristics noted under conditions 9.0V ≤ VSUP ≤ 16V, -40°C ≤ TJ ≤ 135°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

  1. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0 : SRS1= 00).

Table 5. MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 908E626 LIN Recessive State Recessive State Dominant State

0.9 VSUP

0.4 VSUP

0.6 VSUP

0.1 VSUP

tTXD-LIN-LOW tTXD-LIN-HIGH TXD RXD LIN 0.9 VSUP Figure 4. LIN Timing Description For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.

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Figure 5. LIN Slew Rate Description Figure 6. Free Wheel Diode Forward Voltage

0.8 VSUP

0.2 VSUP

ILoad (m A) Drop Out (mV) TA = 125°C TA = 25°C TA = -40°C Dropout (mV) ILOAD (mA) 5.0 Analog Integrated Circuit Device Data Freescale Semiconductor 13 908E626 Figure 7. Dropout Voltage on HVDD

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The 908E626 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E626 is well suited to perform stepper motor control, e.g. for climate or light-levelling control via a 3-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as four half-bridge outputs. Other ports are also provided including a selectable HVDD pin. An internal voltage regulator is provided on the SMARTMOS IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL PIN DESCRIPTION See Figures 1, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on Figures 3 for a depiction of the pin locations on the package. PORT A I /O PINS (PTA0:4) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt pins, KBD0 : KBD4. The PTA5/SPSCK pin is not accessible in this device and is internally connected to the SPI clock pin of the analog die. The PTA6/SS pin is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT B I/O PINS (PTB1, PTB3:7) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. All pins are shared with the ADC module. The PTB6 : PTB7 pins are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT pin of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 pin is not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT C I/O PINS (PTC2:4) These pins are special function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI pins of the analog die. For details refer to the 68HC908EY16 datasheet. PORT D I /O PINS (PTD0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are special function, bidirectional I /O port pins that can also be programmed to be timer pins. In step motor applications the PTD0 pin should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 pin is recommended for use as an output pin for generating the FGEN signal (PWM signal) if required by the application. PORT E I /O PIN (PTE1) PTE1/ RXD and PTE0/ TXD are special function, bidirectional I/O port pins that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD pin of the analog die. The connection for the receiver must be done externally. EXTERNAL INTERRUPT PIN (IRQ) The IRQ pin is an asynchronous external interrupt pin. This pin contains an internal pull-up resistor that is always activated, even when the IRQ pin is pulled LOW. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET PIN (RST) A logic [0] on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This pin contains an internal pull-up resistor that is always activated, even when the reset pin is pulled LOW. For details refer to the 68HC908EY16 datasheet.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 908E626 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT PIN (FGEN) Input pin for the half-bridge current limitation PWM frequency. This input is not a real PWM input pin; it should just supply the period of the PWM. The duty cycle will be generated automatically. Important The recommended FGEN frequency should be in the range of 0.1kHz to 20kHz. BACK ELECTROMAGNETIC FORCE OUTPUT PIN (BEMF) This pin gives the user information about back electromagnetic force (BEMF). This feature allows stall detection and coil failures in step motor applications. In order to evaluate this signal the pin must be directly connected to pin PTD0 / TACH0 / BEMF. RESET PIN (RST_A) RST_A is the bidirectional reset pin of the analog die. It is an open drain with pull-up resistor and must be connected to the RST pin of the MCU. INTERRUPT PIN (IRQ_A) IRQ_A is the interrupt output pin of the analog die indicating errors or wake-up events. It is an open drain with pull-up resistor and must be connected to the IRQ pin of the MCU. SLAVE SELECT PIN (SS) This pin is the SPI Slave Select pin for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I /O of the microcontroller. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. HALF-BRIDGE OUTPUT PINS (HB1: HB4) The 908E626 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1: HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high side and low side switches. The HB1: HB4 outputs are short-circuit and over- temperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low side MOSFETs. POWER SUPPLY PINS (VSUP1: VSUP3) VSUP1: VSUP3 are device power supply pins. The nominal input voltage is designed for operation from 12V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs, multiple VSUP pins are provided. All VSUP pins must be connected to get full chip functionality. POWER GROUND PINS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs multiple pins are provided. GND1 and GND2 pins must be connected to get full chip functionality. SWITCHABLE VDD OUTPUT PIN (HVDD) The HVDD pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0V supply; The output is short-circuit protected. + 5.0V VOLTAGE REGULATOR OUTPUT PIN (VDD) The VDD pin is needed to place an external capacitor to stabilize the regulated output voltage. The VDD pin is intended to supply the embedded microcontroller. Important The VDD pin should not be used to supply other loads; use the HVDD pin for this purpose. The VDD, EVDD, VDDA, and VREFH pins must be connected together. VOLTAGE REGULATOR GROUND PIN (VSS) The VSS pin is the ground pin for the connection of all non- power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL pins must be connected together. LIN TRANSCEIVER OUTPUT PIN (RXD) This pin is the output of LIN transceiver. The pin must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD pin). ADC REFERENCE PINS (VREFL AND VREFH) VREFL and VREFH are the reference voltage pins for the ADC. It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC SUPPLY PINS (VDDA AND VSSA) VDDA and VSSA are the power supply pins for the analog- to-digital converter (ADC). It is recommended that a high quality ceramic decoupling capacitor be placed between these pins. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces.

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FUNCTIONAL PIN DESCRIPTION VSSA is the ground pin for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY PINS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST PIN (FLSVPP) This pin is for test purposes only. This pin should be either left open (not connected) or connected to GND. EXPOSED PAD PIN The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 908E626 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPTS The 908E626 has six different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. LOW VOLTAGE INTERRUPT The Low Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-bridges (high side MOSFET only) are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. HIGH VOLTAGE INTERRUPT The High voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-bridges (high side MOSFET only) are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. HIGH TEMPERATURE INTERRUPT The High Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the High Temperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. AUTONOMOUS WATCHDOG INTERRUPT (AWD) Refer to Autonomous Watchdog (AWD) on page 31. LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN pin will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. OVER-CURRENT INTERRUPT If an over-current condition on a half-bridge or the HVDD output is detected and the OCIE bit is set and an interrupt generated. SYSTEM WAKE-UP System wake-up can be initiated by any of four events:

  • A falling edge on the LIN pin
  • A wake-up signal from the AWD
  • An LVR condition If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (MREG) Figures 8.

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Figure 8. STOP Mode / Wake-up Procedure clears the LINF bit. Writing a logic [0] to LINF has no effect.

  • 1 = Falling edge on LIN data line has occurred.
  • 0 = Falling edge on LIN data line has not occurred since last clear. HTF — HIGH TEMPERATURE FLAG BIT This read / write flag is set on a high temperature condition. Clear HTF by writing a logic [1] to HTF. If a high temperature condition is still present while writing a logic [1] to HTF, the From Reset Initialize Operate SPI: GS =1 (MREG off) STOP IRQ Interrupt? SPI: Reason for Interrupt Operate STOP MREG Wait for Action LIN AWD Hallport Assert IRQ_A Start MREG MREG = Main Voltage Regulator MCU Die Analog Die Register Name and Address: IFR - $05 0 0 LINF HTF LVF HVF OCF 0 0 0 0 0 0 0 0 0

clears the HTF bit. Writing a logic [0] to HTF has no effect.

  • 1 = High temperature condition has occurred.
  • 0 = High temperature condition has not occurred. LVF — LOW VOLTAGE FLAG BIT This read / write flag is set on a low voltage condition. Clear LVF by writing a logic [1] to LVF. If a low voltage condition is still present while writing a logic [1] to LVF, the writing has no effect. Therefore, a low voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a logic [0] to LVF has no effect.
  • 1 = Low voltage condition has occurred.
  • 0 = Low voltage condition has not occurred. HVF — HIGH VOLTAGE FLAG BIT This read / write flag is set on a high voltage condition. Clear HVF by writing a logic [1] to HVF. If high voltage condition is still present while writing a logic [1] to HVF, the writing has no effect. Therefore, a high voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a logic [0] to HVF has no effect.
  • 1 = High voltage condition has occurred.
  • 0 = High voltage condition has not occurred. OCF — OVER-CURRENT FLAG BIT This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 9, which shows the two signals triggering the OCF.
  • 1 = High current condition has occurred.
  • 0 = High current condition has not occurred. OCF HVDD_OCF HB_OCF

Figure 9. Principal Implementation for OCF LINF. Reset clears the LINIE bit.

  • 1 = Interrupt requests from LINF flag enabled.
  • 0 = Interrupt requests from LINF flag disabled. Register Name and Address: IMR - $04 0 0 LINIE HTIE LVIE HVIE OCIE 0 0 0 0 0 0 0 0

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temperature flag, HTF. Reset clears the HTIE bit.

  • 1 = Interrupt requests from HTF flag enabled.
  • 0 = Interrupt requests from HTF flag disabled. LVIE — LOW VOLTAGE INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the low voltage flag, LVF. Reset clears the LVIE bit.
  • 1 = Interrupt requests from LVF flag enabled.
  • 0 = Interrupt requests from LVF flag disabled. HVIE — HIGH VOLTAGE INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the high voltage flag, HVF. Reset clears the HVIE bit.
  • 1 = Interrupt requests from HVF flag enabled.
  • 0 = Interrupt requests from HVF flag disabled. OCIE — OVER-CURRENT INTERRUPT ENABLE BIT This read / write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit.
  • 1 = Interrupt requests from OCF flag enabled.
  • 0 = Interrupt requests from OCF flag disabled. RESET The 908E626 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 10 depicts the internal reset sources. HTRE Flag HVRE Flag AWDRE Flag AWD Reset Sensor High-Voltage Reset Sensor High-Temperature Reset Sensor MONO FLOP Low-Voltage Reset VDD RST_A SPI REGISTERS

Figure 10. Internal Reset Routing reset the high temperature reset is disabled. falls below a certain threshold, it will pull down the RST_A pin.

SMARTMOS device by pulling down the RST pin.

  • 1 = Low temperature threshold enabled.
  • 0 = Low temperature threshold disabled. HVRE — High Voltage Reset Enable Bit This read / write bit enables resets on high voltage conditions. Reset clears the HVRE bit.
  • 1 = High voltage reset enabled.
  • 0 = High voltage reset disabled. HTRE — High Temperature Reset Enable Bit This read / write bit enables resets on high temperature conditions. Reset clears the HTRE bit.
  • 1 = High temperature reset enabled.
  • 0 = High temperature reset disabled. SERIAL PERIPHERAL INTERFACE The serial peripheral interface (SPI) creates the communication link between the microcontroller and the 908E626. The interface consists of four pins (see Figure 11):
  • SS — Slave Select
  • M O S I — Master-Out Slave-In
  • M I S O — Master-In Slave-Out
  • SPSCK — Serial Clock (maximum frequency 4.0 MHz) A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address. S7 S6 S5 S4 S3 S2 S1 S0 R/W A4 A3 A2 A1 A0 P X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 System Status Register Read/Write, Address, Parity Data (Register write) Data (Register read) Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data SS MOSI MISO SPSCK

Figure 11. SPI Protocol clock edges are present in the active phase of SS.

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high impedance. MASTER ADDRESS BYTE A4 : A0 Contains the address of the desired register. R / W Contains information about a read or a write operation.

  • I f R / W = 1, the second byte of master contains no valid information, slave just transmits back register data.
  • I f R / W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS register on rising edge of SS. Parity P The parity bit is equal to “0” if the number of 1 bits is an even number contained within R/ W, A4 : A0. If the number of 1 bits is odd, P equals “1”. For example, if R/ W = 1, A4 : A0 = 00001, then P equals “0.” The parity bit is only evaluated during a write operation. Bit X Not used. Master Data Byte Contains data to be written or no valid data during a read operation.

Table 6. List of Registers layer is designed to meet the LIN physical layer specification. between both slew rate controls is guaranteed.

0000 H V D D O N 0

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control it during system power-up or power-down. state) by a low level on RXD. used to read six internal diagnostic analog voltages. The 908E626 includes an on-chip temperature sensor. selected with the ADMUX Register. SS3, SS2, SS1, and SS0 bits. Table 7. Analog Multiplexer Configuration Register

  1. This bit must always be set to 0.
  • 1 = HVDD enabled.
  • 0 = HVDD disabled. HALF-BRIDGES Outputs HB1 : HB4 provide four low resistive half-bridge output stages. The half-bridges can be used in H-bridge, high side, or low side configurations. Reset clears all bits in the H-bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1: HB4 output features:
  • Short circuit (over-current) protection on high side and low side MOSFETs.
  • Current recopy feat ure (low side MOSFET).
  • Over-temperature protection.
  • Over-voltage and under-voltage protection.
  • Current limitation feature (low side MOSFET). High-Side Driver Charge Pump, Overtemperature Protection, Overcurrent Protection Low-Side Driver Current Recopy, Current Limitation, Overcurrent Protection Control On/Off Status On/Off Status Current Limit HBx VSUP GND BEMF

Figure 12. Half-bridge Push-Pull Output Driver high side MOSFET has a higher priority. the high side MOSFET did not fall below a certain threshold.

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES HBx_L — Low Side On / Off Bits These read / write bits turn on the low side MOSFETs. Reset clears the HBx_L bits.

  • 1 = Low side MOSFET turned on for half-bridge output
  • 0 = Low side MOSFET turned off for half-bridge output HBx_H — High Side On/Off Bits These read / write bits turn on the high side MOSFETs. Reset clears the HBx_H bits.
  • 1 = High side MOSFET turned on for half-bridge output
  • 0 = High side MOSFET turned on for half-bridge output HALF-BRIDGE CURRENT LIMITATION Each low side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. The recommended frequency range for the FGEN and the PWM is 0.1kHz to 20kHz. Functionality Each low side MOSFET switches off if a current above the selected current limit was detected. The 908E626 offers five different current limits (refer to Table 8, page 30, for current limit values). The low side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 13).

Figure 13. Half-bridge Current Limitation

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Figure 14. Offset Chopping for Step Motor Control and switched to the analog multiplexer. selected via bit CSA in the System Control Register.

  • CSA = 1: Low resolution selected (500 mA measurement range).
  • CSA = 0: High resolution selected (2.5 A measurement range). HALF-BRIDGE BEMF GENERATION The BEMF output is set to “1” if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal) (see Figure 15, page 29).

Figure 15. BEMF Signal Generation HB_OCF in the System Status Register (SYSSTAT) is set. System Status Register or by reset.

  • 1 = Offset chopping enabled.
  • 0 = Offset chopping disabled. Coil Current Voltage on BEMF Signal Register Name and Address: HBCTL - $02 OFC_EN CSA 0 0 0 CLS2 CLS1 CLS0 0 0 0 0 0 0 0 0

30 Freescale Semiconductor

of the H-bridges. Reset clears the CSA bit.

  • 1 = Current sense amplification set for measuring 0.5 A.
  • 0 = Current sense amplification set for measuring 2.5 A. CLS2 : CLS0 — H-bridge Current Limitation Selection Bits These read / write bits select the current limitation value according to Table 8. Reset clears the CLS2 : CLS0 bits.

Table 8. H-bridge Current Limitation Value Selection used for driving external circuitry that requires a VDD voltage. HVI) have no influence on this circuitry. temperature reset is enabled. the System Status Register is set.

  • 1 = Power stages enabled.
  • 0 = Power stages disabled. SRS0 : SRS1 — LIN Slew Rate Selection Bits These read / write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 9. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application.

Table 9. LIN Slew Rate Selection Bits

  • 1 = Power down and go into STOP mode
  • 0 = Not in STOP mode System Status Register (SYSSTAT) Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset LINCL — LIN Current Limitation Bit This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation CLS2 CLS1 CLS0 Current Limit 0 0 0 No Limit0 0 1 0 1 0 0 1 1 55mA (typ) 1 0 0 260mA (typ) 1 0 1 370mA (typ) 1 1 0 550mA (typ) 1 1 1 740mA (typ) Register Name and Address: SYSCTL - $03 Bit 7 6 5 4 3 2 1 Bit 0 Read PSON SRS1 SRS0 0 0 0 0 0 Write GS Reset 000 0 0 0 00 SRS1 SRS0 LIN Slew Rate 0 0 Initial Slew Rate (20 kBaud) 0 1 Slow Slew Rate (10 kBaud) 1 0 High Speed II (8 x) 1 1 High Speed I (4 x) Register Name and Address: SYSSTAT - $0c LINCL HVDD _OCF 0 LVF HVF HB_ OCF HTF 00000000

Analog Integrated Circuit Device Data Freescale Semiconductor 31 908E626 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES in the transmitter, software is advised to turn the transmitter off immediately.

  • 1 = Transmitter operating in current limitation region.
  • 0 = Transmitter not operating in current limitation region. HVDD_OCF — HVDD Output Over-current Flag Bit This read / write flag is set on an over-current condition at the HVDD pin. Clear HVDD_OCF and enable the output by writing a logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect.
  • 1 = Over-current condition on HVDD has occurred.
  • 0 = No over-current condition on HVDD has occurred. LVF — Low Voltage Bit This read only bit is a copy of the LVF bit in the Interrupt Flag Register.
  • 1 = Low voltage condition has occurred.
  • 0 = No low voltage condition has occurred. HVF — High Voltage Sensor Bit This read-only bit is a copy of the HVF bit in the Interrupt Flag Register.
  • 1 = High voltage condition has occurred.
  • 0 = No high voltage condition has occurred. HB_OCF — H-bridge Over-current Flag Bit This read / write flag is set on an over-current condition at the H-bridges. Clear HB_OCF and enable the H-bridge driver by writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a logic [0] to HB_OCF has no effect.
  • 1 = Over-current condition on H-bridges has occurred.
  • 0 = No over-current condition on H-bridges has occurred. HTF — Over-temperature Status Bit This read-only bit is a copy of the HTF bit in the Interrupt Flag Register.
  • 1 = Over-temperature condition has occurred.
  • 0 = No over-temperature condition has occurred. AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module consists of three functions:
  • Watchdog function for the CPU in RUN mode
  • Periodic interrupt function in STOP mode The Autonomous Watchdog module allows to protect the CPU against code runaways. The AWD is enabled if AWDIE, AWDRE in the AWDCTL Register is set. If this bit is cleared, the AWD oscillator is disabled and the watchdog switched off. Watchdog The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. PERIODIC INTERRUPT Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. Autonomous Watchdog Control Register (AWDCTL) Bit 7 6 5 4 3 2 1 Bit 0 Read Write Reset 17. This bit must always be set to 0. AWDRST — Autonomous Watchdog Reset Bit This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit.
  • 1 = Reset AWD and restart timeout period.
  • 0 = No effect. AWDRE — Autonomous Watchdog Reset Enable Bit This read / write bit enables resets on AWD time-outs. A reset on the RST_A is asserted when the Autonomous Watchdog has reached the timeout and the Autonomous Watchdog is enabled. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit.
  • 1 = Autonomous watchdog enabled.
  • 0 = Autonomous watchdog disabled. Autonomous Watchdog Interrupt Enable Bit (AWDIE) This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit.
  • 1 = CPU interrupt requests from AWDF enabled
  • 0 = CPU interrupt requests from AWDF disabled Register Name and Address: AWDCTL - $0a 00 0 AWDRE AWDIE 0(17) 0 AWDR AWDRST 00 0 0 0 00 0 Notes

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION AWDR — Autonomous Watchdog Rate Bit This read / write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit.

  • 1 = Fast rate selected (10ms).
  • 0 = Slow rate selected (20ms). VOLTAGE REGULATOR The 908E626 chip contains a low power, low drop voltage regulator to provide internal power and external power for the MCU. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD pin to provide the 5.0V to the microcontroller. Note: Under loss of power conditions, the discharge of the VDD capacitor may occur relatively slow. Based on the selected external components and external VDD load, additional external load may be required guarantee the MCU POR threshold being reached before the next power up. RUN Mode During RUN mode, the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP Mode During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E626, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state:
  • 0xFD80: 0xFDDF Trim and Calibration Values
  • 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate this dependencies a ICG trim values is located at address $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4.7uF) V DD = 5V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset.

34 Freescale Semiconductor

Figure 17. Normal Monitor Mode Circuit Table 10. Monitor Mode Signal Requirements and Options

  1. PTA0 must have a pull-up resistor to V DD in monitor mode
  2. External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1
  3. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
  4. V TST is a high voltage VDD + 3.5V ≤ VTST ≤ VDD + 4.5V

36 Freescale Semiconductor

Figure 19. PCB Layout Recommendations

  1. Freescale does not assume liability, endorse , or want components from external manufactures that are referenced in circuit drawings
  2. Components are recommended to improve EMC and ESD performance.

Table 11. Component Value Recommendation should be connected right at the C3. Total Capacitance on LIN has to be below 220pF.

Analog Integrated Circuit Device Data Freescale Semiconductor 37 908E626 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10519D. DWB SUFFIX EK SUFFIX (PB-FREE) 54-PIN 98ARL10519D ISSUE D

EK SUFFIX (PB-FREE) 54-PIN 98ARL10519D ISSUE D Analog Integrated Circuit Device Data

38 Freescale Semiconductor

EK SUFFIX (PB-FREE) 54-PIN 98ARL10519D ISSUE D Analog Integrated Circuit Device Data Freescale Semiconductor 39 908E626 PACKAGING PACKAGING DIMENSIONS

40 Freescale Semiconductor

electrical, application and packaging information is provided in the data sheet. temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. RθJ21 and RθJ22, respectively. Figure 20. Thermal Land Pattern for Direct Thermal Table 12. Thermal Performance Comparison

  1. Per JEDEC JESD51-2 at natural convection, still air
  2. 2s2p thermal test board per JEDEC JESD51-7and
  3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

  1. Single layer thermal test board per JEDEC JESD51-3 and
  2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

Figure 21. Thermal Test Board where the junction temperature is sensed. Table 13. Thermal Resistance Performance

42 Freescale Semiconductor

Figure 22. Device on Thermal Test Board RθJA Figure 23. Transient Thermal Resistance RθJA (1.0W Step Response)

Analog Integrated Circuit Device Data Freescale Semiconductor 43 908E626

REVISION HISTORY

THERMAL ADDENDUM (REV 1.0) REVISION DATE DESCRIPTION OF CHANGES 4.0 9/2008 5.0 7/2009

  • Implemented Revision History page
  • Minor corrections throughout the document
  • Updated to current Freescale format and style
  • Added MM908E626AVEK to the ordering information
  • Corrected package drawing designation
  • Added STOP mode
  • Corrected several non-technical cross-references.

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