MM908E624 MOTOROLA | Alldatasheet
Document overview
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Technical content
Features
- High-Performance M68HC908EY16 Core
- 16 K Bytes of On-Chip Flash Memory
- 512 Bytes of RAM
- Internal Clock Generator Module
- Two 16-Bit, 2-Channel Timers
- 10-Bit Analog-to-Digital Converter (ADC)
- LIN Physical Layer Interface
- Low Dropout Voltage Regulator
- Three High-Side Outputs
- Two Wake-Up Inputs
- 16 Microcontroller I/Os
Figure 1. 908E624 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MM908E624ACDWB/R -40°C to 85°C 54 SOICW DW SUFFIX 98ASA99294D 54-TERMINAL SOICW M PTD1/TACH1 PTA0−4 PWMin PTD0/TACH0 IRQB_A IRQB RSTB_A RSTB PTE1/RxD RxD GND EVSS VSSA VREFL VDD EVDD VDDA VREFH LIN HS3 HS1 HS2 OUT WDCONF VSUP1 VSUP2 VBAT LIN Interface Microcontroller Ports To Microcontroller A/D Channel +5.0 V VCC AGND PTB1;3−7 PTC2−4
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1024 Bytes
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10 Bit Analog-to-Digital
Figure 2. 908E624 Simplified Internal Block
Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 17. that are shared with other functional modules in the MCU. that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. driven low when any internal reset source is asserted. that are shared with other functional modules in the MCU. NC No Connect Not connected. can is shared with other functional modules in the MCU.
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respectively. The MCU operates from a single-power supply. that are shared with other functional modules in the MCU. MCU 51 FLSVPP Test Terminal For test purposes only. Do not connect in the application. RST_A Internal Reset Output This terminal is the reset output terminal of the analog die. Wake-Up Inputs These terminals are the wake-up inputs of the analog chip. High-Side Output These output terminals are low R DS(ON) high-side switches. These terminals are device power supply terminals. Analog 29 LIN LIN Bus This terminal represents the single-wire bus transmitter and receiver. These terminals are device power ground connections. Analog 36 OUT Amplifier Output This terminal is the output of the operational amplifier. Amplifier Inputs These terminals are the am plifier inverted and non-inverted inputs. allows the disabling of the watchdog. This terminal is the output of LIN transceiver. Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 17.
Table 2. Maximum Ratings
- ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP =1 5 0 0Ω).
- ESD2 testing is performed in ac cordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
- ESD3 testing is performed in accordanc e with Charge Device Model, Robotic (CZAP =4 . 0p F ) .
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- Die temperature of analog and MCU is linked via the package. High temperature on analog die can lead to a high MCU temperature.
- Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- All power outputs ON and dissipating equal power.
- Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7.
Table 2. Maximum Ratings (continued)
Table 3. Static Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
- Device is fully functional . All functions are operating. Overtemperature may occur.
- Total current (I VSUP1 + IVSUP2) measured at GND terminal.
- Stop and Sleep mode current will increase if V SUP exceeds 15 V.
- This parameter is guaranteed by process monitoring but is not production tested.
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- Measured when voltage has dropped 100 mV below its nominal value.
- When switching from Normal to Stop mode or from Stop mode to No rmal mode, the output voltage can vary within the output voltage
- This parameter is guaranteed by process monitoring but not production tested
Table 3. Static Electrical Characteristics (continued) noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
- Watchdog timing period calculation formula: P WD = 0.991 * REXT+0.648 (REXT in kΩ and PWD in ms).
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
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- This parameter is guaranteed by process monitoring but it is not production tested
- When overtemperature occurs, switch is tu rned off and latched off. Flag is set in SPI.
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
6.0 V < VSUP <1 8V
18 V < VSUP <2 7V
5.5 V < V
- This parameter is guaranteed by process monitoring but is not production tested.
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
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Table 4. Dynamic Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. to LIN signal threshold defined at each parameter.
- Measured between LIN signal threshold V IL or VIH and 50% of RXD signal.
- t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
- This parameter is guaranteed by process monitoring but is not production tested.
- Delay between turn-on or turn-off command and high-side on or high-si de off, excluding rise or fall time due to external load.
- Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation.
- This parameter is guaranteed by process monitoring but it is not production tested.
Table 4. Dynamic Electrical Characteristics (continued) microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
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Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
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Figure 7. LIN Timing Measurements for Slow Slew Rate Figure 8. Wake-Up Sleep Mode Timing Figure 9. Wake-Up Stop Mode Timing
0.4 VSUP
Analog Integrated Circuit Device Data Freescale Semiconductor 17 908E624 Functional Description Introduction FUNCTIONAL DESCRIPTION INTRODUCTION The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high-side outputs. Other ports are also provided, which include an operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT A I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/ SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT B I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT C I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. PORT D I/O TERMINALS PTD1/TACH1 and PTD0/TACH0/BEMF are special- function, bidirectional I/O port terminals that can also be programmed to be timer terminals. For details refer to the 68HC908EY16 datasheet. PORT E I/O TERMINAL PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details refer to the 68HC908EY16 datasheet. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals, respectively. The MCU operates from a single- power supply.
Analog Integrated Circuit Device Data
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Functional Terminal Description Fast signal transitions on MCU terminals place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details refer to the 68HC908EY16 datasheet. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. Do not connect in the application. PWMIN TERMINAL This terminal is the direct PWM input for high-side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs. LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). RESET TERMINAL (RST_A) RST_A is the reset output terminal of the analog die and must be connected to the RST terminal of the MCU. Important To ensure proper operation, do not add any external pullup resistor. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal must be connected to the IRQ terminal of the MCU. WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) This terminal is the configuration terminal for the internal watchdog. A resistor is connected to this terminal. The resistor value defines the watchdog period. If the terminal is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this terminal to GND. POWER SUPPLY TERMINALS (VSUP1 AND VSUP2) This VSUP1 power supply terminal supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply terminal is the positive supply for the high-side switches. POWER GROUND TERMINAL (GND) This terminal is the device ground connection. HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2) These terminals are high-side switch outputs to drive loads such as relays or lamps. Each switch is protected with overtemperature and current limit (overcurrent). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by SPI and have a direct enabled input (PWMIN) for PWM capability. HIGH-SIDE OUTPUT TERMINAL (HS3) This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. The switch is protected with overtemperature and current limit (overcurrent). The output is controlled only by SPI. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. WAKE-UP TERMINALS (L1 AND L2) These terminals are high-voltage capable inputs used to sense external switches and to wake up the device from Sleep or Stop mode. During Normal mode the state of these terminals can be read through SPI.
Analog Integrated Circuit Device Data Freescale Semiconductor 19 908E624 Functional Description Functional Terminal Description SENSE AMPLIFIER TERMINALS (E+, E-, OUT, VCC) These are the terminals of the single-supply sense amplifier.
- The E+ and E- input terminals are the non-inverting and inverting inputs of the amplifier, respectively.
- The OUT terminal is the output terminal of the current sense amplifier.
- The VCC terminal is the +5.0 V single-supply connection. +5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. The terminal is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH terminals must be connected together. VOLTAGE REGULATOR AND SENSE AMPLIFIER GROUND TERMINAL (AGND) The AGND terminal is the ground terminal of the voltage regulator and the Sense Amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL terminals must be connected together.
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voltage regulator is turned off (VDD = 0 V). the voltage regulator is turned back on. MODE1:2 bits in the SPI Control register. overview of the operating mode. Figure 10. Operating Modes and Transitions
maskable and cannot be disabled. voltage condition is present. the high-voltage condition is present. interrupts are not maskable and cannot be disabled. remains set as long as the error condition is present. temperature prewarning circuitry is disabled. as the error condition is present. shutdown circuitry is disabled. Table 6. Operating Modes Overview
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Figure 11. Stop Mode/Wake-Up Procedure same applies to the HS2 output. them against overcurrent and short circuit conditions. In Sleep and Stop modes the high-sides are disabled. possible on this terminal (refer to Figure 13, page 23). it against overcurrent and short circuit conditions. In Sleep and Stop mode the high-side is disabled.
Analog Integrated Circuit Device Data
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Functional Device Operation Watchdog Configuration If the WDCONF terminal is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF terminal must be connected to GND. The watchdog period is calculated using the following formula: P WD [ms] = 0.991 * REXT [kΩ] + 0.648 VOLTAGE REGULATOR The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The V DD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. Current Limit (Overcurrent) Protection The voltage regulator has current limit to protect the device against overcurrent and short circuit conditions. Overtemperature Protection The voltage regulator also features an overtemperature protection having an overtemperature warning (Interrupt - VDDT) and an overtemperature shutdown. Stop Mode During Stop mode the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. Sleep Mode In Sleep mode the voltage regulator external VDD is turned off. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” (0xFF) state:
- 0xFD80:0xFDDF Trim and Calibration Values
- 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 datasheet.
- SS—Slave Select
- MOSI—Master-Out Slave-In
- MISO—Master-In Slave-Out
- SPSCK—Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data.
Figure 15. SPI Protocol latches the analog status data (Register read data). SPI clock SPSCK the data is sampled by the Receiver. edges are present in the active (low) phase of SS.
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value, and bit reset condition. Table 8 shows the SPI Control register bits by name.
- 1 = Pullup disconnected in Sleep and Stop modes.
- 0 = Pullup connected in Sleep and Stop modes. HS3ON:HS1ON—High-Side H3:HS1 Enable Bit This bit enables the HSx. Reset clears the HSx bit.
- 1 = HSx switched on (refer to Note below).
- 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN terminal must be connected to the VDD terminal. MODE2:1—Mode Section Bits The MODE2:1 bits control the operating modes and the watchdog in accordance with Table 10. To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep/Stop commands require two SPI transmissions.
Table 7. SPI Register Overview
- D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.
- The first SPI read after reset returns the BATFAIL flag state on bit D4.
Table 8. Control Bits Function (Write Operation) Table 9. LIN Baud Rate and Low-Power Mode Selection Table 10. Mode Selection Bits
- To enter Sleep and Stop mode, a special sequence of SPI
- The device stays in Run (Normal) mode.
Table 13 shows the SPI Status register bits by name. an interrupt/wake-up interrupt source.
- 1 = D6:D0 reflects the interrupt or wake-up source.
- 0 = No interrupt occurred. Other SPI bits report real time status. LINWU/LINFAIL—LIN Status Flag Bit This bit indicates a LIN wake-up condition.
- 1 = LIN bus wake-up occurred or LIN overcurrent/ overtemperature occurred.
- 0 = No LIN bus wake-up occurred. HVF —High-Voltage Flag Bit This flag is set on an overvoltage (VSUP1) condition.
- 1 = High-voltage condition has occurred.
- 0 = no High-voltage condition. LVF/BATFAIL—Low-Voltage Flag Bit This flag is set on an undervoltage (VSUP1) condition.
- 1 = Low-voltage condition has occurred.
- 0 = No low-voltage condition. VDDT—Voltage Regulator Status Flag Bit This flag is set as pre-warning in case of an over- temperature condition on the voltage regulator.
- 1 = Voltage regulator over temperature condition, pre- warning.
- 0 = No overtemperature detected. HSST—High-Side Status Flag Bit This flag is set on overtemperature conditions on one of the high-side outputs.
- 1 = HSx off due to overtemperature.
- 0 = No overtemperature. L2:L1— Wake-Up Inputs L1, L2 Status Flag Bit These flags reflect the status of the L2 and L1 input terminals and indicate the wake-up source.
- 1 = L2:L1 input high or wake-up by L2:L1 (first register read after wake-up indicated with INTSRC = 1).
- 0 = L2:L1 input low.
Table 11. Sleep Command Bits Table 12. Stop Command Bits Table 13. Control Bits Function (Read Operation)
Analog Integrated Circuit Device Data
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Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. CASE 1365-01 ISSUE O DATE 09/19/01 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY . 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL17.8 7.4 27 28 0.10 A 2.35 SEATING PLANE 0.9 SECTION B-B 0.65 R0.08 MIN B A (0.29) 0.38 0.30 (0.25) PLATING BASE METAL SECTION A-A ROTATED 90 CLOCKWISE° 0.25 0.22
0.13 M CAB
A C7.6 18.0 10.3 5.15 A 54X 52X 2.65 0.3 A 2X 27 TIPS B C BB 0.29 0.13 0.50° 0.25 GAUGE PLANE MIN PIN 1 INDEX DWB SUFFIX 54-TERMINAL SOIC WIDE BODY PLASTIC PACKAGE 98ASA99294D ISSUE O
© Freescale Semiconductor, Inc., 2004. All rights reserved. the reference temperature while only heat source 1 is heating with P1. to the reference temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22, respectively. the performance of a package in an application-specific environment. according to the standards listed below. Table 1. Thermal Performance Comparison
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Figure 1. Thermal Test Board the junction temperature is sensed. Table 2. Thermal Resistance Performance
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