908E624

908E624_10 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 40

Technical content

Features

• High-Performance M68HC908EY16 Core
• 1 6 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM
• Internal Clock Generator Module
• Two 16-Bit, 2-Channel Timers
• 10-Bit Analog-to-Digital Converter (ADC)
• LIN Physical Layer Interface
• Low Dropout Voltage Regulator
• Three high side Outputs
• Two Wake-Up Inputs
• 16 Microcontroller I / Os
• Pb-Free Packaging Designated by Suffix Code EW

Figure 1. 908E624 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MM908E624ACDWB/ R2 - 40°C to 85°C

54 SOICW*MM908E624ACEW/ R2

*MM908E624AYEW/ R2 - 40°C to 125°C Notes* Recommended for new designs DWB SUFFIX EW (Pb-FREE) SUFFIX 98ASA99294D 54-TERMINAL SOICW M PTD1/TACH1 PTA0-4 PWMIN PTD0/TACH0 PTE1/RXD RXD GND EVSS VSSA VREFL VDD EVDD VDDA VREFH LIN HS3 HS1 HS2 OUT WDCONF VSUP1 VSUP2 VBAT LIN Interface Microcontroller Ports To Microcontroller A/D Channel +5.0 V VCC AGND PTB1; 3-7 PTC2-4 908E624 RST RST_A IRQ IRQ_A

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1024 Bytes

24 Internal System

10 Bit Analog-to-Digital

Figure 2. 908E624 Simplified Internal Block Diagram

Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18. that are shared with other functional modules in the MCU. that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. driven low when any internal reset source is asserted. that are shared with other functional modules in the MCU. NC No Connect Not connected. can is shared with other functional modules in the MCU.

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respectively. The MCU operates from a single-power supply. that are shared with other functional modules in the MCU. MCU 51 FLSVPP Test Terminal For test purposes only. Do not connect in the application. Analog 18 RST_A Internal Reset Output This terminal is the reset output terminal of the analog die. Wake-Up Inputs These terminals are the wake-up inputs of the analog chip. These terminals are device power supply terminals. Analog 29 LIN LIN Bus This terminal represents the single-wire bus transmitter and receiver. These terminals are device power ground connections. Analog 36 OUT Amplifier Output This terminal is the output of the current sense operational amplifier. allows the disabling of the watchdog. This terminal is the output of LIN transceiver. Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 908E624

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings

1. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP =

200 pF, RZAP = 0 Ω), and the Charge Device Model, Robotic (CZAP = 4.0 pF).

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Package Operating Ambient Temperature (4) MM908E624ACDWB and MM908E624ACEW MM908E624AYEW TA - 40 to 85 - 40 to 125 Operating Junction Temperature (2)(4) MM908E624ACDWB and MM908E624ACEW MM908E624AYEW TJ - 40 to 125 - 40 to 125 Storage Temperature TSTG - 40 to 150 °C Peak Package Reflow Temperature During Reflow(3)(5) TPPRT Note 5 °C Notes 2. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because of higher power dissipation of the analog die. The analog die junction temperature must not exceed 150°C under these conditions. 3. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 4. Independent of T A, device parametrics are only guaranteed for - 40 < TJ < 125°C. Please see note 2. TJ is a factor of power dissipation, package thermal resistance, and available heat sinking. 5. Freescale’s Package Reflow capability meets Pb-free requirem ents for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 2. Maximum Ratings (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 7 908E624 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

1. Device is fully functional . All functions are operating. Over-temperature may occur.
2. Total current (I VSUP1 + IVSUP2) measured at GND terminal.
3. Stop and Sleep mode current will increase if V SUP exceeds 15 V.
4. This parameter is guaranteed by process monitoring but is not production tested.

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STATIC ELECTRICAL CHARACTERISTICS SYSTEM RESETS AND INTERRUPTS Low-Voltage Reset (LVR) Threshold V LVRON 3.6 4.0 4.4 V Low-Voltage Interrupt (LVI) Threshold Hysteresis V LVI V LVI_HYS 5.7 6.0 1.0 6.6 V High-Voltage Interrupt (HVI) Threshold Hysteresis V HVI V HVI_HYS 19.25 220 20.5 V mV VOLTAGE REGULATOR (10) Normal Mode Output Voltage 2.0 mA < IDD < 50 mA, 5.5 V < VSUP < 27 V V DDRUN 4.75 5.0 5.25 V Normal Mode Output Current Limitation (11) IDDRUN 50 110 200 mA Dropout Voltage VSUP = 4.9 V, IDD = 50 mA V DDDROP —0 . 1 0 . 2 V Stop Mode Output Voltage (12) V DDSTOP 4.75 5.0 5.25 V Stop Mode Regulator Current Limitation IDDSTOP 4.0 8.0 14 mA Line Regulation Normal Mode, 5.5 V < VSUP < 27 V, IDD = 10 mA Stop Mode, 5.5 V < VSUP < 27 V, IDD = 2.0 mA VLRRUN VLR STOP 150 100 mV Load Regulation Normal Mode, 1.0 mA < IDD < 50 mA, VSUP = 18 V Stop Mode, 1.0 mA < IDD < 5.0 mA, VSUP = 18 V VLRRUN VLDSTOP 150 150 mV Over-temperature Pre-Warning (Junction) (13) T PRE 120 135 160 °C Thermal Shutdown Temperature (Junction) (13) T SD 155 170 — °C Temperature Threshold Difference TSD - TPRE ΔT SD-T PRE 20 30 45 Notes 10. Specification with external capacitor 2.0 μF< C < 10 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Capacitor value up to 47 μF can be used. 12. When switching from Normal to Stop mode or from Stop mode to No rmal mode, the output voltage can vary within the output voltage specification. 13. This parameter is guaranteed by process monitoring but not production tested Table 3. Static Electrical Characteristics (continued) noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 908E624 STATIC ELECTRICAL CHARACTERISTICS WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) External Resistor Range REXT 10 — 100 k Ω Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy) (14) WDCACC -15 — 15 LIN PHYSICAL LAYER LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0 μA Dominant State, TXD LOW, 500 Ω External Pullup Resistor V LIN_REC V LIN_DOM VSUP -1 1.4 V Normal Mode Pullup Resistor to VSUP R PU 20 30 60 k Ω Stop, Sleep Mode Pullup Current Source IPU —2 . 0— μA Output Current Shutdown Threshold IOV-CUR 50 75 150 mA Leakage Current to GND VSUP Disconnected, VBUS at 18 V Recessive State, 8.0 V ≤ VSUP ≤ 18 V, 8.0 V≤ VBUS ≤ 18 V, VBUS ≥ VSUP GND Disconnected, VGND = VSUP, VBUS at -18 V IBUS 0.0 -1.0 1.0 3.0 1.0 μA LIN Receiver Receiver Threshold Dominant Receiver Threshold Recessive Receiver Threshold Center Receiver Threshold Hysteresis V BUS_DOM V BUS_REC V BUS_CNT V BUS_HYS 0.6 0.475 0.5 0.4 0.525 0.175 VSUP Notes 14. Watchdog timing period calculation formula: P WD = 0.991 * REXT + 0.648 (REXT in kΩ and PWD in ms). noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS HIGH SIDE OUTPUTS HS1 AND HS2 Switch On Resistance TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP > 9.0 V RDS(ON) 2.0 3.0 2.5 4.5 Ω Output Current Limit ILIM 300 — 600 mA Over-temperature Shutdown (15), (16) THSSD 155 — 190 °C Leakage Current ILEAK ——1 0 μA Output Clamp Voltage IOUT = -100 mA VCL - 6.0 — — V HIGH SIDE OUTPUT HS3 Switch On Resistance TJ = 25°C, ILOAD = 50 m A, VSUP > 9.0 V TJ = 125°C, ILOAD = 50 mA, VSUP > 9.0 V TJ = 125°C, ILOAD = 30 mA, 5.5 V < VSUP > 9.0 V RDS(ON) 7.0 Ω Output Current Limitation ILIM 60 100 200 mA Over-temperature Shutdown (15), (16) THSSD 155 — 190 °C Leakage Current ILEAK ——1 0 μA Notes 15. This parameter is guaranteed by process monitoring but it is not production tested 16. When over-temperature occurs, switch is turned off and latched off. Flag is set in SPI. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 908E624 STATIC ELECTRICAL CHARACTERISTICS CURRENT SENSE OPERATIONAL AMPLIFIER Rail-to-Rail Input Voltage VIMC - 0.1 — V CC + 0.1 V Output Voltage Range Output Current ± 1.0 mA Output Current ± 5.0 mA VOUT1 VOUT2 0.1 0.3 VCC - 0.1 VCC - 0.3 V Input Bias Current IB —— 2 5 0 n A Input Offset Current IO -100 — 100 nA Input Offset Voltage VIO - 25 — 25 mV L1 AND L2 INPUTS Low Detection Threshold 5.5 V < VSUP < 6.0 V

6.0 V < VSUP < 18 V

18 V < VSUP < 27 V

2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.5 3.7 V High Detection Threshold

5.5 V < V

SUP < 6.0 V 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.5 4.7 V Hysteresis

5.5 V < VSUP < 27 V

0.5 — 1.3 V Input Current - 0.2 V < VIN < 40 V IIN -10 — 10 μA noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. to LIN signal threshold defined at each parameter.

1. Measured between LIN signal threshold V IL or VIH and 50% of RXD signal.
2. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the VDD

rise time is strongly dependent upon the decoupling capacitor at VDD terminal.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 908E624 DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER (CONTINUED) Output Current Shutdown Delay tOV-DELAY —1 0— μs SPI INTERFACE TIMING SPI Operating Recommended Frequency f SPIOP 0.25 — 4.0 MHz L1 AND L2 INPUTS Wake-Up Filter Time (22) t WUF 8.0 20 38 μs WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) Watchdog Period External Resistor REXT = 10 kΩ (1%) External Resistor REXT = 100 kΩ (1%) Without External Resistor REXT (WDCONF Terminal Open) t PWD 10.558 99.748 150 205 ms STATE MACHINE TIMING Reset Low-Level Duration after VDD High (26) t RST 0.65 1.0 1.35 ms Interrupt Low-Level Duration t INT 7.0 10 13 μs Normal Request Mode Timeout (26) t NR TOUT 97 150 205 ms Delay Between SPI Command and HS1 / HS2 / HS3 Turn On (23) , (24) t S-HSON —3 . 01 0 μs Delay Between SPI Command and HS1 / HS2 / HS3 Turn Off (23) , (24) t S-HSOFF —3 . 01 0 μs Delay Between Normal Request and Normal Mode After W/ D Trigger Command (25) t S-NR2N 6.0 35 70 μs Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode (VDD On and Reset High) t W-SS 15 40 80 μs Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI Command t W-SPI 90 — N/A μs Delay Between Interrupt Pulse and First SPI Command Accepted t S-1STSPI 30 — N/A μs Minimum Time Between Two Rising Edges on SS t 2SS 15 — — μs Notes 22. This parameter is guaranteed by process monitoring but is not production tested. 23. Delay between turn-on or turn-off command and high side on or high side off, excluding rise or fall time due to external load. 24. Delay between the end of the SPI command (rising edge of the SS) and start of device activation / deactivation. 25. This parameter is guaranteed by process monitoring but it is not production tested. 26. Also see Figure 10 on page 17 Table 4. Dynamic Electrical Characteristics (continued) microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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MICROCONTROLLER PARAMETRICS MICROCONTROLLER PARAMETRICS CURRENT SENSE OPERATIONAL AMPLIFIER Supply Voltage Rejection Ratio (27) SVR 60 — — dB Common Mode Rejection Ratio (27) CMR 70 — — dB Gain Bandwidth (27) GBP 1.0 — — MHz Slew Rate SR 0.5 — — V/ μs Phase Margin (for Gain = 1, Load 100 pF / 5.0 kΩ (27) PHMO 40 — — ° Open Loop Gain OLG — 85 — dB Notes 27. This parameter is guaranteed by process monitoring but it is not production tested. microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, - 40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.

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Figure 7. LIN Timing Measurements for Slow Slew Rate Figure 8. Wake-Up Sleep Mode Timing Figure 9. Wake-Up Stop Mode Timing

0.4 VSUP

Analog Integrated Circuit Device Data Freescale Semiconductor 17 908E624 Figure 10. Power On Reset and Normal Request Time-out Timing

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The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high side outputs. Other ports are also provided, which include a current sense operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT A I /O TERMINALS (PTA0:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0 : PTA4 are shared with the keyboard interrupt terminals KBD0 : KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/ SS terminal is likewise not accessible. For details, refer to the 68HC908EY16 data sheet. PORT B I/O TERMINALS (PTB1:7) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6 : PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details, refer to the 68HC908EY16 data sheet. PORT C I/O TERMINALS (PTC2:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2 : PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details, refer to the 68HC908EY16 data sheet. PORT D I /O TERMINALS (PTD:0:1) PTD1/ TACH1 and PTD0/ TACH0/BEMF are special- function, bidirectional I /O port terminals that can also be programmed to be timer terminals. For details, refer to the 68HC908EY16 data sheet. PORT E I /O TERMINAL (PTE1) PTE1/ RXD and PTE0/ TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/ TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details, refer to the 68HC908EY16 data sheet. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details, refer to the 68HC908EY16 data sheet. EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details, refer to the 68HC908EY16 data sheet.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 908E624 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals, respectively. The MCU operates from a single- power supply. Fast signal transitions on MCU terminals place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details, refer to the 68HC908EY16 data sheet. ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details, refer to the 68HC908EY16 data sheet. ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details, refer to the 68HC908EY16 data sheet. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. Do not connect in the application or connect to GND. PWMIN TERMINAL (PWMIN) This terminal is the direct PWM input for high side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs. LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). RESET TERMINAL (RST_A) RST_A is the reset output terminal of the analog die and must be connected to the RST terminal of the MCU. Important To ensure proper operation, do not add any external pullup resistor. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal must be connected to the IRQ terminal of the MCU. WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) This terminal is the configuration terminal for the internal watchdog. A resistor is connected to this terminal. The resistor value defines the watchdog period. If the terminal is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this terminal to GND. POWER SUPPLY TERMINALS (VSUP1 AND VSUP2) This VSUP1 power supply terminal supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply terminal is the positive supply for the high side switches. POWER GROUND TERMINAL (GND) This terminal is the device ground connection. HIGH SIDE OUTPUT TERMINALS (HS1 AND HS2) These terminals are high side switch outputs to drive loads such as relays or lamps. Each switch is protected with over- temperature and current limit (over-current). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by SPI and have a direct enabled input (PWMIN) for PWM capability. HIGH SIDE OUTPUT TERMINAL (HS3) This high side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. The switch is protected with over-temperature and current limit (over- current). The output is controlled only by SPI. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. WAKE-UP TERMINALS (L1 AND L2) These terminals are high-voltage capable inputs used to sense external switches and to wake up the device from Sleep or Stop mode. During Normal mode the state of these terminals can be read through SPI. Important If unused these terminals should be connected to VSUP or GND to avoid parasitic transitions. In Low Power Mode this could lead to random wakeup events.

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FUNCTIONAL TERMINAL DESCRIPTION CURRENT SENSE OPERATIONAL AMPLIFIER TERMINALS (E+, E-, OUT, VCC) These are the terminals of the single-supply current sense operational amplifier.

• The E+ and E- input terminals are the non-inverting and inverting inputs of the current sense operational amplifier, respectively.
• The OUT terminal is the out put terminal of the current sense operational amplifier.
• The VCC terminal is the + 5.0 V single-supply connection. Note If the operational amplifier is not used, it is possible to connect all terminals (E+, E-, OUT and VCC) to GND - in this case all of the four terminals must be grounded. + 5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. The terminal is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH terminals must be connected together. VOLTAGE REGULATOR AND CURRENT SENSE AMPLIFIER GROUND TERMINAL (AGND) The AGND terminal is the ground terminal of the voltage regulator and the current sense operational amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL terminals must be connected together. NO CONNECT TERMINALS (NC) The NC terminals are not connected internally. Note Each of the NC terminals can be left open or connected to ground (recommended).

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maskable and cannot be disabled. voltage condition is present. the high-voltage condition is present. interrupts are not maskable and cannot be disabled. remains set as long as the error condition is present. temperature prewarning circuitry is disabled. shutdown circuitry is disabled. Table 6. Operating Modes Overview

Figure 12. Stop Mode / Wake-Up Procedure

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same applies to the HS2 output. them against over-current and short circuit conditions. the HSST bit in the SPI Control register. In Sleep and Stop modes the high sides are disabled. possible on this terminal (refer to Figure 14, page 25). it against over-current and short circuit conditions. the HSST bit in the SPI Control register. In Sleep and Stop mode the high side is disabled. Figure 13. High Side HS1 and HS2 Circuitry

Figure 14. High Side HS3 Circuitry between both slew rate controls is guaranteed. during external disturbance. reduce the current consumption in STOP and SLEEP modes.

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Figure 15. LIN Interface HIGH, the LIN output MOSFET is turned off (recessive state). system power-up or power-down. state) by a low level on RXD. and able to detect wake-up events on the LIN bus line. flag in the SPI Status Register. Also see Figure 9, page 16. to be able to detect wake-up events on the LIN bus line.

(150 ms) (first watchdog clear) has no window. Figure 16. Window Watchdog Operation required, the WDCONF terminal must be connected to GND. the VDD terminal to provide the 5.0 V to the microcontroller. against over-current and short circuit conditions. VDDT) and an over-temperature shutdown. limited output current capability.

• 0xFD80 :0xFDDF Trim and Calibration Values
• 0xFFFE : 0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values The usage of the trim values, located in the flash memory, is explained in the following. Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate for these dependencies, an ICG trim value is located at address $FDC2. After trimming the ICG, a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) V DD = 5V, TAmbient~23°C) and will vary over-temperature and voltage (VDD) as indicated in the 68HC908EY16 data sheet. To trim the ICG, these values have to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 data sheet. Window closed no watchdog clear allowed Window open for watchdog clear WD timing x 50% WD timing x 50% WD period (PWD) WD timing selected by resistor on WDCONF terminal. (tPWD)

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• SS — Slave Select
• MOSI — Master-Out Slave-In
• MISO — Master-In Slave-Out
• SPSCK — Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data.

Figure 17. SPI Protocol latches the analog status data (Register read data). SPI clock SPSCK the data is sampled by the Receiver.

Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition. Table 8 shows the SPI Control register bits by name.

• 1 = Pullup disconnected in Sleep and Stop modes.
• 0 = Pullup connected in Sleep and Stop modes. In case the Pullup is disconnected a small current source is used to pull the LIN terminal in recessive state. In case of an erroneous short of the LIN bus to ground this will significantly reduce the power consumption, e.g. in combination with STOP/SLEEP mode. HS3ON : HS1ON — High Side H3 : HS1 Enable Bits These bits enable the HSx. Reset clears the HSxON bit.
• 1 = HSx switched on (refer to Note below).
• 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN terminal must be connected to the VDD terminal. MODE2 : 1 — Mode Section Bits The MODE2 : 1 bits control the operating modes and the watchdog in accordance with Table 10. To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep / Stop commands require two SPI transmissions.

Table 7. SPI Register Overview

1. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.
2. The first SPI read after reset returns the BATFAIL flag state on bit D4.

Table 8. Control Bits Function (Write Operation) Table 9. LIN Baud Rate and Low-Power Mode Selection Table 10. Mode Selection Bits

1. To enter Sleep and Stop mode, a special sequence of SPI
2. The device stays in Run (Normal) mode.

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The Sleep command, as shown in Table 11, must be sent twice. The Stop command, as shown in Table 12, must be sent twice. Table 13 shows the SPI Status register bits by name. an interrupt / wake-up interrupt source.

• 1 = D6 : D0 reflects the interrupt or wake-up source.
• 0 = No interrupt occurred. Other SPI bits report real time status. LINWU / LINFAIL — LIN Status Flag Bit This bit indicates a LIN wake-up condition.
• 1 = LIN bus wake-up occurred or LIN over-current/over- temperature occurred.
• 0 = No LIN bus wake-up occurred. In case of a LIN over-current/over-temperature condition the LIN transmitter is disabled. To reenable the LIN transmitter, the error condition must be GONE and the LINWU/LINFAIL flag must be cleared. The flag is cleared by reading the flag when it is set (SPI command). HVF — High-Voltage Flag Bit This flag is set on an over-voltage (VSUP1) condition.
• 1 = High-voltage condition has occurred.
• 0 = no High-voltage condition. LVF / BATFAIL — Low-Voltage Flag Bit This flag is set on an under-voltage (VSUP1) condition.
• 1 = Low-voltage condition has occurred.
• 0 = No low-voltage condition. VDDT — Voltage Regulator Status Flag Bit This flag is set as pre-warning in case of an over- temperature condition on the voltage regulator.
• 1 = Voltage regulator over-temperature condition, pre- warning.
• 0 = No over-temperature detected. HSST — High Side Status Flag Bit This flag is set on over-temperature conditions on one of the high side outputs.
• 1 = HSx off due to over-temperature.
• 0 = No over-temperature. In case one of the high sides has an over-temperature condition all high side switches are disabled. To reenable the high side switches, the flags have to be cleared, by reading the flag when it is set and by writing a one to high side HSxON bit (two SPI commands are necessary). L2:L1— Wake-Up Inputs L1, L2 Status Flag Bit These flags reflect the status of the L2 and L1 input terminals and indicate the wake-up source.
• 1 = L2 : L1 input high or wake-up by L2 : L1 (first register read after wake-up indicated with INTSRC = 1).
• 0 = L2 : L1 input low.

Table 11. Sleep Command Bits Table 12. Stop Command Bits Table 13. Control Bits Function (Read Operation)

• nominal 12 V rather than 5.0 V or 3.0 V supply
• high voltage V TST might be applied not only to IRQ terminal, but IRQ_A terminal
• MCU monitoring (Normal request timeout) has to be disabled For a detailed information on the MCU related development support see the MC68HC908EY16 data sheet - section development support. The programming is principally possible at two stages in the manufacturing process — first on chip level, before the IC is soldered onto a PCB board and second after the IC is soldered onto the PCB board. Chip Level Programming On Chip level the easiest way is to only power the MCU with +5.0 V (see Figure 18) and not to provide the analog chip with VSUP, in this setup all the analog terminal should be left open (e.g. VSUP[1:2]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 data sheet - section development support.

Figure 18. Normal Monitor Mode Circuit (MCU only) with VSUP (12 V) instead as described in Figure 19, page 32.

32 Freescale Semiconductor

Figure 19. Normal Monitor Mode Circuit Table 14. Monitor Mode Signal Requirements and Options

1. PTA0 must have a pullup resistor to V DD in monitor mode.
2. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256.
3. V TST is a high voltage VDD + 3.5 V ≤ VTST ≤ VDD + 4.5 V.

34 Freescale Semiconductor

Figure 21. PCB Layout Recommendations Table 15. Component Value Recommendation should be connected right at the C3. C5 180 pF, SMD Ceramic Close (<5 mm) to LIN terminal. Total Capacitance per LIN node has to be below 220 pF.

1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings
2. Components are recommended to improve EMC and ESD performance.

Analog Integrated Circuit Device Data Freescale Semiconductor 35 908E624 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. CASE 1365-01 ISSUE O DATE 09/19/01 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY . 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL17.8 7.4 27 28 0.10 A 2.35 SEATING PLANE 0.9 SECTION B-B 0.65 R0.08 MIN B A (0.29) 0.38 0.30 (0.25) PLATING BASE METAL SECTION A-A ROTATED 90 CLOCKWISE° 0.25 0.22

0.13 M CAB

A C7.6 18.0 10.3 5.15 A 54X 52X 2.65 0.3 A 2X 27 TIPS B C BB 0.29 0.13 0.50° 0.25 GAUGE PLANE MIN PIN 1 INDEX DWB SUFFIX EW SUFFIX (Pb-FREE) 54-TERMINAL SOIC WIDE BODY PLASTIC PACKAGE 98ASA99294D ISSUE O

36 Freescale Semiconductor

electrical, application, and packaging information is provided in the datasheet. temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. RθJ21 and RθJ22, respectively. Table 16. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

54 Terminal SOIC

Figure 22. Surface Mount for SOIC Wide Body where the junction temperature is sensed. Table 17. Thermal Resistance Performance

38 Freescale Semiconductor

Figure 23. Device on Thermal Test Board Figure 24. Transient Thermal Resistance RθJA (1.0 W Step Response)

Analog Integrated Circuit Device Data Freescale Semiconductor 39 908E624

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 7.0 5/2006 • Implemented Revision History page

• Added Pb-Free package option (Suffix EW) and higher Soldering temperature
• Added “Y” temperature (TJ - 40°C to 125°C) code option (MM908E624AYEW) and updated condi- tion statement for Static and Dynamic Electrical Characteristics
• Corrected Figure 11, Operating Modes and Transitions (“STOP command” for transition from Nor- mal to Stop state)
• Updated Figure 21, PCB Layout Recommendations, comment NC Terminal used for signal routing
• Updated Table 15, Component Value Recommendation
• Corrected Figure 23, Device on Thermal Test Board
• Removed reference to Note 11, Voltage Regulator - Dropout Voltage
• Added comment “LIN in recessive state” to Supply Current Range in Stop Mode and Sleep Mode
• Updated format to match current data sheet standard.
• Added Figure 10, Power On Reset and Normal Request Time-out Timing
• Added LIN P/L details
• Made clarifications on Max Ratings Table for T A and TJ Thermal Ratings and the accompanying Note 8.0 3/2007 • Removed “Advance Information” watermark from first page. 9.0 9/2010 • Changed Peak Package Reflow Temperature During Reflow(3)(5) description.
• Added note (5)

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