900844

900844 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 118

Technical content

Features

• Main system power management integrated in a single chip
• Fully programmable DC/DC switching, low drop-out regulators, and load switches
• SPI interface (up to 25 MHz operation)
• 10-bit ADC for internal and ex ternal sensing with touch screen interface
• Real time clock (RTC)
• 8 Interrupt capable GPIOs and 8 GPOs
• I/O interrupt and reset controller

Figure 1. 900844 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package SC900844JVK -40 °C to 85 °C 338-MAPBGA POWER MANAGEMENT

Applications

• Netbooks
• Tablet PC
• S l a t e s
• Embedded Devices 11 mm x 11 mm 98ASA10841D 338-MAPBGA Freescale PMIC Ultra-mobile 900844 CORE PMIC Core I/O GPIO / GPO SPI Control CPU (central Platform 3.3 V SMPS SMPS 5.0 V

19 V ADP

processing unit) controller hub ADC Inputs ADC / Touch Screen Inputs Platform SMPS

1.8 V Memory

1 x 3.3 V Power Switch 5VA 3VA

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Figure 2. 900844 Internal Block Diagram

10 Bit

top view. The BGA footprint on the application PCB will have the same mapping as given in Figure 3. Figure 3. 900844 Package Ball Map

18 SPICLK NC GNDLSP

8 CS VOUTPMI

180 VCORE PMICINT VINLSPR NC NC NC NC NC2

9 MOSI THERMT

1 NC GNDAUD

2 RX1 I2SVCC FS1 NC

3 NC ICTEST NC GNDLED

33 NC PVINVIB VOUTIMG

28 ADIN16 XTAL1 GPIO7 RAWCHG NC NC NC4

25 ADIN19 ADIN17 ADIN10 CLK32K NC PGNDCH

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Table 1. 900844 Pin Description

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voltage node when VSDIO is in LDO mode.

when a SPI voltage regulation request has been decoded. The signal is de-asserted on completion of the request (i.e. that all power rails to the platform controller hub are good. Controller Hub will remain “off” until this signal is asserted. 150 ns. The CPU will hold the value for at least 300 ns.

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1. The Type Column indicates the maximum average current through each ball assigned to the different nodes. 500 mA maximum for

Analog Integrated Circuit Device Data Freescale Semiconductor 11 900844

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. The 900844 has input power from 3.3 V supply into VBAT. The cold-boot rails are “ON”.

1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause a malfunction or permanent damage to the device.

1. Freescale's Package Reflow capability m eets the Pb-free requirements for JEDEC standard J-STD-020C, for Peak Package Reflow
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device

Model (CDM), Robotic (CZAP = 4.0 pF).

1. All pins meet 500 V CDM except VCOREREF.

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During operation, the temperature of the die must not exceed the maximum junction temperature. Depending on the operating ambient temperature and the total internal dissipation this limit can be exceeded. To optimize the thermal management scheme and avoid overheating, the 900844 provides a thermal management system that protects against overheating. This protection should be considered as a fail-safe mechanism, and the application design should initiate thermal shutdown under normal conditions. Reference Thermal Management for more details. POWER CONSUMPTION Table 2 defines the maximum power consumption specifications in the various system and device states. For each entry in the table, the component is assumed to be configured for driving purely capacitive loads, and the voltages listed in each entry are nominal output voltages. Note that the “Soft Mechanical Off” state is a transitional state. The device will spend less than 150 µs in this state before V15 starts to turn on, upon detection of a valid input voltage.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 900844 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values are characterized at VPWR = 3.6 V and 25 °C. PMICINT, VRCOMP, RESETB, PWRGD. PMICINT, VRCOMP, RESETB, PWRGD.

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STATIC ELECTRICAL CHARACTERISTICS Crystal OSC Operating Drive Level - 0.25 - 0.5 µW Crystal OSC Nominal Lead Capacitance - - 9.0 - pF Crystal OSC Aging - - - 3.0 ppm/year COIN CELL CHARGER Coin cell Charge Voltage (Selectable through VCOIN[2:0] bits) VCOINCELL 2.5 - 3.3 V Coin cell Charge Voltage Accuracy - -100 - 100 mV Coin cell Charge Current ICOIN - 60 - µA Coin cell Charge Current Accuracy - -15 - 15 % POWER STATES DETECTION THRESHOLDS Battery Cutoff Threshold (Depending on Battery Model) VBATOFF 2.2 - 2.4 V Coin Cell Disconnect Threshold VCOINOFF 1.8 - 2.0 V Low Battery Threshold VLOWBAT 3.2 - - V Valid Battery Threshold VTRKL - 3.0 - V VPWR Rising Under-voltage Threshold VPWRUVR - 3.1 - V VPWR Falling Under-voltage Threshold VPWRUVF - 2.55 - V VCC ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Extended Input Voltage Range VPWR 2.8 3.6 4.7 V Output Voltage Programmability Range Low Power Mode Active Mode VCC 0.3 0.65 0.7 1.2 V Output Voltage Programmability Step Size - - 12.5 - mV Output Voltage Accuracy 0.6 V < VCC < 12 V, 1.5 A < ICC < 3.5 A 0.6 V < VCC < 12 V, ICC < 1.5 A 0.3 V < VCC < 0.6 V -5.0 -4.0 -7.0 5.0 4.0 7.0 Output Voltage Overshoot Maximum overshoot voltage above VID setting voltage. Maximum overshoot time is 10-30 s, output voltage = 0.9 V at 50 mA VOS - - 50 mV Continuous Output Load Current Low Power mode Active Mode ICC - 0.2 0.2 3.5 A Peak Current Limit ILIMCC - 5.0 - A Output Current Limit Accuracy - ±15 - % Transient Load Change Low Power Mode Active Mode ΔICC 0.2 1.2 A values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 900844 STATIC ELECTRICAL CHARACTERISTICS VNN ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Extended Input Voltage Range VPWR 2.8 3.6 4.7 V Output Voltage Programmability Range (Set by VID Control Signals) VNN 0.65 - 1.2 V Output Voltage Programmability Step Size - - 12.5 - mV Output Voltage Accuracy - -5.0 - 5.0 % Output Voltage Overshoot Maximum overshoot voltage above VID setting voltage. Maximum overshoot time is 10 s, output voltage = 0.9 V at 50 mA VOS - - 50 mV Continuous Output Load Current Low Power Mode Active Mode INN 0.2 0.2 1.6 A Peak Current Limit ILIMNN - 2.5 - A Output Current Limit Accuracy - - ±20 - % Transient Load Change ΔINN - - 0.5 A VDDQ ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Extended Input Voltage Range VPWR 2.8 3.6 4.7 V Output Voltage Setting VDDQ - 1.8 - V Output Voltage Accuracy - -5.0 - 5.0 % Continuous Output Load Current IDDQ - - 1.3 A Peak Current Limit ILIMDDQ - 1.78 - A Output Current Limit Accuracy 0.5 A < IDDQ < 1.3 A IDDQ < 0.5 A -15 -20 +15 +20 Transient Load Change IDDQ - - 0.5 A Effective Quiescent Current Consumption (PWM, No Load) IQDDQ - 30 - µA V21 ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Extended Input Voltage Range VPWR 2.8 3.6 4.7 V Output Voltage Setting V21 - 2.1 - V Output Voltage Accuracy - -5.0 - 5.0 % Continuous Output Load Current I21 - - 1.0 A Peak Current Limit ILIM21 - 1.42 - A Output Current Limit Accuracy - -20 - +20 % Transient Load Change I21 - - 0.5 A Effective Quiescent Current Consumption (PWM, No Load) IQ21 - 30 - µA values are characterized at VPWR = 3.6 V and 25 °C.

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STATIC ELECTRICAL CHARACTERISTICS V15 ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Extended Input Voltage Range VPWR 2.8 3.6 4.7 V Output Voltage Setting (Also programmable to 1.6 V, typical) V15 - 1.5 - V Output Voltage Accuracy - -5.0 - 5.0 % Continuous Output Load Current I15 0 0.75 1.5 A Peak Current Limit ILIM15 - 1.6 - A Output Current Limit Accuracy - -20 - +20 % Transient Load Change I15 - - 0.5 A Effective Quiescent Current Consumption (PWM, No Load) IQ15 - 30 - µA VBG ELECTRICAL CHARACTERISTICS Input Voltage Range VDDQ V21 1.71 1.995 1.80 2.100 1.89 2.205 V Output Voltage Setting VBG - 1.25 - V Output Voltage Accuracy - -2.0 - 2.0 % Under-voltage Detection Threshold (With respect to the output voltage) VBGUV - -12 - % Under-voltage Detection Threshold Hysteresis VBGUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IBG - 2.0 mA µA Current Limit ILIMBG - 94 - mA Transient Load Change ΔIBG - - 1.0 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IBG = 1.5 mA, VDDQ = 1.8 V) PSRRBG 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQBG µA VCCA ELECTRICAL CHARACTERISTICS Input Voltage Range VDDQ V21 1.71 1.995 1.80 2.100 1.89 2.205 V Output Voltage Setting VCCA - 1.5 - V Output Voltage Accuracy - -2.0 - 2.0 % Under-voltage Detection Threshold (With respect to the output voltage) VCCAUV - -12 - % Under-voltage Detection Threshold Hysteresis VCCAUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode ICCA 150 3.0 mA mA values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 900844 STATIC ELECTRICAL CHARACTERISTICS Current Limit ILIMCCA - 225 - mA Transient Load Change ΔICCA - - 50 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCA = 112.5 mA, VDDQ = 1.8 V) PSRRCCA 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQCCA µA VCC180 ELECTRICAL CHARACTERISTICS Input Voltage Range V21 1.995 2.1 2.205 V Output Voltage Setting VCC180 - 1.8 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VCC180UV - -12 - % Under-voltage Detection Threshold Hysteresis VCC180UVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode ICC180 390 7.8 mA mA Current Limit ILIMCC180 - 585 - mA Transient Load Change ΔICC180 - - 350 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICC180 = 292.5 mA, V21 = 2.1 V) PSRRCC180 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQCC180 µA VPNL18 ELECTRICAL CHARACTERISTICS SPECIFICATION Input Voltage Range V21 1.995 2.1 2.205 V Output Voltage Setting VPNL18 - 1.8 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VPNL18UV - -12 - % Under-voltage Detection Threshold Hysteresis VPNL18UVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IPNL18 - 210 4.2 mA Current Limit ILIMPNL18 - 315 - mA Transient Load Change ΔIPNL18 - - 100 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IPNL18 = 157.5 mA, V21 = 2.1 V) PSRRPNL18 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQPNL18 µA values are characterized at VPWR = 3.6 V and 25 °C.

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STATIC ELECTRICAL CHARACTERISTICS VPMIC ELECTRICAL CHARACTERISTICS Input Voltage Range V21 1.995 2.1 2.205 V Output Voltage Setting VPMIC - 1.8 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VPMICUV - -12 - % Under-voltage Detection Threshold Hysteresis VPMICUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IPMIC 100 2.0 mA Current Limit ILIMPMIC - 150 - mA Transient Load Change ΔIPMIC - - 20 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IPMIC = 75 mA, V21 = 2.1 V) PSRRPMIC 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQPMIC - µA VYMXYFI18 ELECTRICAL CHARACTERISTICS Input Voltage Range V21 1.995 2.1 2.205 V Output Voltage Setting VYMXYFI18 - 1.8 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VYMXYFI18UV - -12 - % Under-voltage Detection Threshold Hysteresis VYMXYFI18UVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IYMXYFI18 200 4.0 mA Current Limit ILIMYMXYFI18 - 300 - mA Transient Load Change ΔIYMXYFI18 - - 100 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IYMXYFI18 = 150 mA), (V21 = 2.1 V or VPWR = 3.6 V) PSRRYMXYFI18 40 - - dB Output Noise (10 Hz to 100 kHz, IYMXYFI18 = 200 mA), (V21 = 2.1 V or VPWR = 3.6 V) VNOISEYMXYFI18 - - 40 µVRMS Effective Quiescent Current Consumption Active Mode Low Power Mode IQYMXYFI18 µA values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 900844 STATIC ELECTRICAL CHARACTERISTICS VCCPAOAC ELECTRICAL CHARACTERISTICS Input Voltage Range V15 1.425 1.5 1.680 V Output Voltage Setting VCCPAOAC - 1.05 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VCCPAOACUV - -12 - % Under-voltage Detection Threshold Hysteresis VCCPAOACUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode ICCPAOAC 155 3.1 mA Current Limit ILIMCCPAOAC - 232.5 - mA Transient Load Change ΔICCPAOAC - - 50 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCPAOAC = 116 mA, V15 = 1.5 V) PSRRCCPAOAC 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQCCPAOAC µA VCCPDDR ELECTRICAL CHARACTERISTICS Input Voltage Range V15 1.425 1.5 1.680 V Output Voltage Setting VCCPDDR - 1.05 - V Output Voltage Accuracy - -2.0 - 2.0 % Under-voltage Detection Threshold (With respect to the output voltage) VCCPDDRUV - -12 - % Under-voltage Detection Threshold Hysteresis VCCPDDRUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode ICCPDDR 1.2 mA Current Limit ILIMCCPDDR - 90 - mA Transient Load Change ΔICCPDDR - - 10 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCPDDR = 45 mA, V15 = 1.5 V) PSRRCCPDDR 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQCCPDDR µA VAON ELECTRICAL CHARACTERISTICS Input Voltage Range V15 1.425 1.5 1.680 V Output Voltage Setting VAON - 1.2 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VAONUV - -12 - % Under-voltage Detection Threshold Hysteresis VAONUVH - 1.0 - % values are characterized at VPWR = 3.6 V and 25 °C.

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STATIC ELECTRICAL CHARACTERISTICS Continuous Output Load Current Active Mode Low Power Mode IAON 250 5.0 mA Current Limit ILIMAON - 375 - mA Transient Load Change ΔIAON - - 100 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IAON = 187.5 mA, V15 = 1.5 V) PSRRAON 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQAON µA VMM ELECTRICAL CHARACTERISTICS Input Voltage Range V15 1.425 1.5 1.680 V Output Voltage Setting VMM - 1.2 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VMMUV - -12 - % Under-voltage Detection Threshold Hysteresis VMMUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IMM 5.0 0.1 mA Current Limit ILIMMM - 25 - mA Transient Load Change ΔIMM - - 3.0 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IMM = 4.0 mA, V15 = 1.5 V) PSRRMM 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQMM µA VCCP ELECTRICAL CHARACTERISTICS Input Voltage Range V15 1.425 1.5 1.680 V Output Voltage Setting VCCP - 1.05 - V Output Voltage Accuracy - -5 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VCCPUV - -12 - % Under-voltage Detection Threshold Hysteresis VCCPUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode ICCP 445 8.9 mA Current Limit ILIMCCP - 667.5 - mA Transient Load Change ΔICCP - - 100 mA values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 900844 STATIC ELECTRICAL CHARACTERISTICS Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCP = 334 mA, V15 = 1.5 V) PSRRCCP 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQCCP µA VIMG25 ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Output Voltage Setting VIMG25 - 2.5 - V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VIMG25UV - -12 - % Under-voltage Detection Threshold Hysteresis VIMG25UVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IIMG25 1.6 mA Current Limit ILIMIMG25 - 120 - mA Transient Load Change ΔIIMG25 - - 10 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IIMG25 = 60 mA, VPWR = 3.3 V) PSRRIMG25 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQIMG25 µA VIMG28 ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.0 3.6 4.4 V Output Voltage Setting VIMG28 (Selectable, see Table 43) V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VIMG28UV - -12 - % Under-voltage Detection Threshold Hysteresis VIMG28UVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode IIMG28 225 4.5 mA Current Limit ILIMIMG28 - 337.5 - mA Transient Load Change ΔIIMG28 - - 100 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IIMG28 = 169 mA, VPWR = 3.3 V) PSRRIMG28 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQIMG28 µA values are characterized at VPWR = 3.6 V and 25 °C.

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STATIC ELECTRICAL CHARACTERISTICS VSDIO ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.135 3.3 3.465 V Output Voltage Setting VSDIO (Selectable, see Table 44) V Output Voltage Accuracy - -5.0 - 5.0 % Under-voltage Detection Threshold (With respect to the output voltage) VSDIOUV - -12 - % Under-voltage Detection Threshold Hysteresis VSDIOUVH - 1.0 - % Continuous Output Load Current Active Mode Low Power Mode ISDIO 215 4.3 mA Current Limit ILIMSDIO - 322.5 - mA Transient Load Change ΔISDIO - - 100 mA Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ISDIO = 161 mA, VPWR = 3.3 V) PSRRSDIO 50 60 - dB Effective Quiescent Current Consumption Active Mode Low Power Mode IQSDIO µA VPNL33 POWER SWITCH ELECTRICAL CHARACTERISTICS Input Voltage Range VPWR 3.135 3.3 3.465 V Drop Across Switch with reference to VPWR - - - 3.0 % Continuous Output Load Current IPNL33 - - 100 mA ADC ELECTRICAL CHARACTERISTICS Conversion Current - - - 1.2 mA OFF Supply Current - - - 1.0 μA Converter Reference Voltage - - 2.4 - V Integral Nonlinearity (Rs = 5.0 kΩ maximum) (6) - - - ±3.0 LSB Differential Nonlinearity (Rs = 5.0 kΩ maximum) (6) - - - ±1.0 LSB Zero Scale Error (Offset) (Rs = 5.0 kΩ maximum) (6) - - - 10 LSB Full Scale Error (Gain) (Rs = 5.0 kΩ maximum) (6), (7) - - - 11 LSB Drift Over Temperature ±2.0 LSB Source Impedance No Bypass Capacitor at Input Bypass Capacitor at Input of (10 nF) 5.0 kΩ kΩ Input Buffer Input Range(8) - 0.02 - 2.4 V Notes 6. Rs represents a possible external series resi stor between the voltage source and the ADIN input. 7. At room temperature. 8. Refer to Table 57 for analog valid input range and input buffer range characteristics for each ADC Channel values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 900844 STATIC ELECTRICAL CHARACTERISTICS GPIOS ELECTRICAL CHARACTERISTICS GPIO Voltage Level (This is wired externally though GPIOVCC pin) VGPIOVCC - 1.8 V, 2.5 V, 3.3 V - V GPO Voltage Level (This is wired externally though GPOVCC pin) VGPOVCC - 1.8 V, 2.5 V, 3.3 V - V Accuracy for GPIOVCC, GPOVCC - -5.0 - 5.0 % GPIO Output Drive Capability - - 20 - Ω Input Low Voltage VIL 0 - 0.3*VCC V Input High Voltage VIH 0.7*VCC - VCC V Output Low Voltage (VCC = VCC_MIN, IOL = 4.0 mA) VOL - - 0.1 V Output High Voltage (VCC = VCC_MIN, IOH = -4.0 mA) VOL VCC-0.1 - - V values are characterized at VPWR = 3.6 V and 25 °C.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 900844 DYNAMIC ELECTRICAL CHARACTERISTICS VDDQ ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IDDQ/t - - 1.0 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) tSSDDQ - - 200 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tDDQOFF - - 1.0 ms Switching Frequency fSW - 4.0 - MHz V21 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change I21/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 V to 2.1 V) tSS21 - - 84 µs Turn Off Time (OFF to output voltage ramp down to 0 V) t21OFF - - 1.0 ms Switching Frequency fSW - 4.0 - MHz V15 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change I15/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 2.1 V) tSS15 - - 100 µs Turn Off Time (OFF to output voltage ramp down to 0 V) t15OFF - - 1.0 ms Switching Frequency fSW - 4.0 - MHz VBG ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IBG/t - - 0.001 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) tSSBG - - 20 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tBGOFF - - 5.0 ms VCCA ELECTRICAL CHARACTERISTICS Transient Load Speed of Change ICCA/t - - 0.01 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.5 V) tSSCCA - - 30 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tCCAOFF - - 5.0 ms VCC180 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change ICC180/t - - 1.0 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) tSSCC180 - - 30 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tCC180OFF - - 5.0 ms VPNL18 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IPNL18/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) tSSPNL18 - - 140 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tPNL18OFF - - 5.0 ms VPMIC ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IPMIC/t - - 0.01 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) tSSPMIC - - 700 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tPMICOFF - - 5.0 ms values are characterized at VPWR = 3.6 V and 25 °C.

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DYNAMIC ELECTRICAL CHARACTERISTICS VYMXYFI18 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IYMXYFI18/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) tSSYMXYFI18 - - 200 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tYMXYFI18OFF - - 5.0 ms VCCPAOAC ELECTRICAL CHARACTERISTICS Transient Load Speed of Change ICCPAOAC/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) tSSCCPAOAC - - 30 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tCCPAOACOFF - - 5.0 ms VCCPDDR ELECTRICAL CHARACTERISTICS Transient Load Speed of Change ICCPDDR/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) tSSCCPDDR - - 35 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tCCPDDROFF - - 5.0 ms VAON ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IAON/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) tSSAON - - 25 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tAONOFF - - 5.0 ms VMM ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IMM/t - - 0.01 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.2 V) tSSMM - - 125 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tMMOFF - - 5.0 ms VCCP ELECTRICAL CHARACTERISTICS Transient Load Speed of Change ICCP/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) tSSCCP - - 26 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tCCPOFF - - 5.0 ms VIMG25 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IIMG25/t - - 0.01 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 2.5 V) tSSIMG25 - - 200 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tIMG25OFF - - 5.0 ms VIMG28 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change IIMG28/t - - 0.1 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 2.9 V) tSSIMG28 - - 200 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tIMG28OFF - - 5.0 ms values are characterized at VPWR = 3.6 V and 25 °C.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 900844 DYNAMIC ELECTRICAL CHARACTERISTICS VSDIO ELECTRICAL CHARACTERISTICS Transient Load Speed of Change ISDIO/t - - 0.01 A/µs Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) tSSSDIO - - 100 µs Turn Off Time (OFF to output voltage ramp down to 0 V) tSDIOOFF - - 5.0 ms POWER SWITCHES ELECTRICAL CHARACTERISTICS Ramp Up Time - - 50 µs ADC ELECTRICAL CHARACTERISTICS Conversion Time Per Channel - - 10 μs Turn on/off Time - - 31 μs values are characterized at VPWR = 3.6 V and 25 °C.

28 Freescale Semiconductor

Netbook, Tablets, Slates, embedded devices, and other applications requiring “multi-cell” battery voltage. management solution to meet the needs of Ultra-mobile platforms. system design, resulting in a faster time to market development cycle. Figure 4. Power Management Solution - High Level Block Diagram

• Netbook, Tablets, and embedded devices, Ul tra-mobile platform Architecture Support
• Fully Programmable DC/DC Switching, Low Drop-Out Regulators, and Load Switches
• Delivers regulated reliable power to various system components
• High efficiency multi mode power conversion ensuring extended battery life
• Fully programmable with ex tensive protection features and complete fault reporting for best in class overall system reliability
• Internal Compensation
• 5 Buck DC/DC Regulators - 2x VID Controlled with 1.0 MHz switching and external switches for CPU and Graphics core support - 3x with 4.0 MHz switching and integrated MOSFET for platform support and LDO supply for optimized thermal performance and power efficiency.
• 14 Low Dropout (LDO) regulators.
• One configurable LDO/Switch regulator for SDIO card support
• A 3 . 3 V load switch for platform support
• Coin Cell Backup battery charger
• SPI communication interface (up to 25 MHz operation)
• 22 channel (32 capable) 10-bit ADC for internal and external sensing with touch screen interface
• Low power 32.786 kHz XTAL oscillator.
• Real Time Clock (RTC) to provide time reference and alarm functions with wake up control.
• Eight Interrupt capable GPIOs and 8 GPOs
• Various control and status reporting I/Os
• Interrupt and Reset controller. All interrupt signals can be masked.
• Overall solution size target of < 400 mm2 (including clearance and routing)
• Operating temperature of -40 to +85 °C 5 x DC/DC multi-mode SWITCHERS 2 x VID

4.0 MHz Switching

22 Channel 10 bit ADC

8 Interrupt Capable GPIOs

Figure 5. 900844 Functional Block Diagram The component list for those items listed in this schematic can be found in the External Components BOM (23).

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This section addresses the various interfaces and I/Os between the PMIC solution and the rest of the system.

• SPI interface.
• Interrupt controller
• Platform sideband signals
• Special registers SPI INTERFACE The 900844 contains a SPI interface port which allows a host controller to access the register set. Using these registers, 900844 resources can be controlled. The registers also provide information on the PMIC status, as well as information on external signals. The addressable register map spans 1024 registers of 8 data bits each. The map is not fully populated. A detailed structure of the register set along with bit names, positions, and basic descriptions, are given in Table 74. Expanded bit descriptions are included in the individual functional sections for application guidance. Note that not all bits are truly writable. Refer to the individual sub-circuit descriptions and Table 74 to determine the read/write capability of each bit. The System Controller Unit (SCU) within the Platform Controller Hub (PCH) is the master, while the PMIC is the slave. The SPI interface operates at a typical frequency of 12.5 MHz, and at a maximum frequency of 25 MHz, with lower speeds supported. The SPI interface is configured in mode 1: clock polarity is active high (CPOL = 0), and data is latched on the falling edge of the clock (CPHA = 1). The chip select signal, SPICSB, is active low. The SPICSB line must remain active during the entire SPI transfer. The MISO line will be tri-stated while SPICSB is high. The SPI frame consists of 24 bits: a Read/Write bit, a 10-bit address code (MSB first), 5 "dead" bits and 8 data bits (also MSB first). The Read/Write bit selects whether the SPI transaction is a read or a write: for a write operation, the R/W bit must be a one; for a read operation, it must be a zero. For a read transaction, any data on the MOSI pin after the address bits is ignored. The MISO pin will output the data field pointed to by the 10-bit address loaded at the beginning of the SPI sequence. SPI read backs of the address field and unused bits are returned as zero. For read operations, the PMIC supports address auto-increment. For a write operation, once all the data bits are written, the data is transferred into the registers on the falling edge of the 24th clock cycle. All unused SPI bits in each register must be written to a zero. To start a new SPI transfer, the SPICSB line must go inactive and then active. After the LSB of data is sent, if the SPICSB line is held low, up to seven additional address/data packets may be sent as writes to the PMIC. Refer to the VRCOMP Pin section. The following diagrams illustrate the SPI Write Protocol, SPI Read Protocol, and SPI Timing.

Table 5. SPI Interface Pin Functionality

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• The 2nd level bit is set.
• The 1st level bit is set by a rising edge sent from the 2nd level register, and the PMICINT signal goes from low to high
• When the system controller, the SCU, reads the 1st level register the 2nd level registers that were set, remain set. Any unset registers are free to accept an interrupt event.
• When the 1st level register is read, any 1st level register bits that were set at the point the SPI read strobe shifts the register value into the SPI transmit shift register, that bit will be cleared by the SPI self clear signal immediately following the read strobe. This allows new interrupts to be recorded without being lost. If all unmasked 1st level bits get cleared by the read, the PIMCINT pin will de-assert. If a new unmasked 1st level interrupt event happens, just after the read of the 1st level register, the PIMCINT pin interrupt pin will remain asserted. The SCU reads each 2nd level register and these are cleared on read.
• When the 2nd level register is read, any 2nd level register bits that were set at the point the SPI read strobe sweeps, the register value into the SPI transmit shift register, that bit will be cleared by the SPI self clear signal immediately following the read strobe. This allows new interrupts to be recorded without being lost. If a new unmasked 2nd level interrupt event happens just after the read of the 2nd level register, the PMICINT pin will assert if the 1st level bit is not masked. Interrupt Bit Summary Table 7 summarizes all 1st and 2nd level interrupt bits associated with the Interrupt Controller. For more detailed behavioral descriptions, refer to the related sections.

Table 6. Interrupt Registers Summary

1. Because of the design of the clear on read logic, any interrupt event is allowed to happen at any time. If the interrupt event happens

close to when a read of the interrupt register happens, if the SPI read captures that interrupt bit as being set, then that bit will get cleared. If the read does not capture the bit as being set, it will not be cleared. In this way no interrupt events are lost.

1. The 2nd level interrupts that get "Ored" together to set the 1st level interrupt bits can block other 2nd level interrupts from setting the 1st

interrupt bits are set when that register is read.

1. Masking has no affect on interrupt bits being set or cleared. Masking just prevents the interrupt event from asserting the interrupt pin. If
2. Some 2nd level interrupt registers are level sensitive. If the level that sets these interrupts registers is active when the register is read,

it will clear during the active time of the clear on read signal and then reassert. This will reassert the 1st level interrupt bit.

1. The GPIO interrupts do not have interrupt masking bits, they ha ve interrupt prevention bits. This is controlled by bits 5:4 of the GPIO

control register. See GPIOs for more details on using the GPIO as interrupt inputs.

1. Interrupts generated by external events are de-bounced. Theref ore, the event needs to be stable throughout the de-bounce period

of the de-bounce timer, the effective de-bounce time can vary slightly.

Table 7. Interrupt Bit Summary

1. Varies by regulator. Normally it is 1.5 times the regulator turn on time.
2. 32 ms rising and 120 μs falling

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The PMICINT pin interrupts the platform controller hub by rising from low to high when an unmasked interrupt event occurs. Controller for a more detailed explanation of the Interrupt mechanism. The PMICINT pin follows the DC Signaling specifications in Table 3 with a reference of 1.8 V (VPMIC). or other write request has been decoded. The signal is de-asserted on completion of the request (i.e. the rail is in regulation). This signal is relevant to the SPI initiated writes and EXITSTBY assertion. The VRCOMP pin follows the DC Signaling specifications in Table 3 with a reference of 1.8 V (VPMIC). Figure 9. VRCOMP Functionality in a SPI Voltage Regulators Configuration Table 8. Sidebands Pin Functionality VIDEN[1:0] I Active high Input signals driven by the CPU, to indicate if the VID bus is addressing VCC or VNN. VID[6:0] I Active high input signals driven by the CPU, to indicate the output voltage setting for the VCC and VNN rails.

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Figure 11. General Exit Standby Diagram Figure 12. Optimized Exit Standby Diagram change. Note that the VDDQ regulator has to be enabled in order for the VCCA regulator to turn on. THERMTRIPB is an active low Thermal Trip input signal. It is asserted by the CPU to indicate a catastrophic thermal event. VCCP regulator is on. The platform controller hub output driver is a nominal 55 Ω. The THERMTRIPB pin follows the DC Signaling specifications in Table 3 with a reference of 1.05 V (VCCPAOAC). notifies that the VID is invalid. This is used when the CPU is in C6/Standby, to tri-state the VID pins to save power.

level. The VID and VIDEN signals will go through the sequence INVALID >> VNN >> INVALID >> VCC. VID[6:0] and VIDEN[1:0] will transition together and the PMIC must de-bounce the VID[6:0] and VIDEN[1:0] for 100 to 400 ns. (01), the VID signals can change and the VCC regulator will respond by changing the output voltage accordingly. during normal operation, it will only change the VID combination by 1 step, which corresponds to a voltage step of ±12.5 mV. During these changes, the VCC regulator must follow the 25 mV/ms slew rate specification. The VID[6:0] pins are active high signals driven by the CPU to indicate the output voltage setting for the VCC and VNN rails. are not for designed customer use. For question regarding these registers, contact Freescale Semiconductor Technical Support. Table 10. VIDEN Selections Table 11. VCC and VNN Latch Register Structure and Bit Description

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Figure 13. Dynamic VCC Timing Diagram Figure 14. Dynamic VNN Timing Diagram Figure 15 shows the 7-bit VID codes vs. the output voltage of VCC and VNN.

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Figure 16. Relationship Between the VID/VIDEN Pins, the DPV1VRD Bit, and VRCOMP Signal The Vendor ID and other version details can be read via the Identification bits. These are hard-wired on the chip. reset by RTCPORB. The banks can be used for any system need, for bit retention with coin cell backup. Table 12. Vendor ID Registers Structure and Bits Description

X is from 1 to 8 in Table 13. The rest of the 24 registers reside in the Freescale dedicated register space. X is from 1 to 16 in Table 14. the following outputs follow the settings as shown. The following register controls the PLL and the different divider values for different output frequencies. Table 13. General Purpose Memory MEMx Register Structure and Bits Description Table 14. General Purpose Memory FSLMEMx Register Structure and Bits Description Table 15. Output Driver Control Selection Table 16. Output Driver Register Structure and Bit Description

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE TEST MODES Test Mode Configuration During evaluation and testing, the IC can be configured for normal operation or test mode via the ICTEST pin and other register configurations. Details of Test mode programmability are not documented herein, but should be referenced from other Design for Test documentation. Test modes are for Freescale use only, and must not be accessed in applications. In test modes, signals are multiplexed on existing functional pins. The ICTEST pin must therefore be tied to ground (for normal operation) at the board level, in product Test mode also disables the thermal protection for high temperature op life testing. A proprietary protocol is included for scan chain test configurations, which reuses the SPI pins. In-package Trimming During IC final test, several parameters are trimmed in the package, such as the main bandgap, and other precision analog functions. Trim registers are for Freescale use only and must not be accessed in product applications. Fuse programming circuitry will be blocked during normal and test mode operation. Table 17. PLL Control Register Structure and Bit Description

Analog Integrated Circuit Device Data Freescale Semiconductor 43 900844 FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) CLOCK GENERATION AND REAL TIME CLOCK (RTC) CLOCK GENERATION A system clock is generated for internal digital circuitry, as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Clocking Scheme The internal 32 kHz oscillator is an integrated backup for the crystal oscillator and provides a 32.768 kHz nominal frequency at 50% accuracy, if running. The internal oscillator only runs if a valid supply is available at the battery or coin cell, and would not be used as long as the crystal oscillator is active. The crystal oscillator continues running, supplied from one of the sources as described previously, until all power is depleted or removed. All control functions will run off the crystal derived frequency, occasionally referred to as the "32 kHz". At system startup, the 32 kHz clock is driven to the CLK32K output pin, which is SPIVCC referenced. CLK32K is provided as a peripheral clock reference. The driver is enabled by the startup sequencer. Additionally, a SPI bit M32KCLK bit is provided for direct SPI control. The M32KCLK bit defaults to 0 to enable the driver and resets on the RTCPORB to ensure the buffer is activated at the first power up and configured as desired, for subsequent power ups. The drive strength of the output drivers is programmable with CLK32KDRV[1:0] (master control bits that affect the drive strength of CLK32K), see FSLOUTDRVCNTL2 Register in Table 16. If a switch over occurs between the two clock sources (such as when the crystal oscillator is starting up), it will occur during the active low phase of both clocks, to avoid clocking glitches. A status bit, OSCSTP, is available to indicate to the processor which clock is currently selected: OSCSTP=1 when the internal RC is used, and OSCSTP=0 if the XTAL source is used. Oscillator Specifications The 32 kHz crystal oscillator has been optimized for use in conjunction with the Abracon™ ABS07-32.768KHZ-T, or equivalent. The electrical characteristics of the 32 kHz Crystal oscillators are given in the Oscillator section on Table 3 and Table 4, taking into account the crystal characteristics noted previously. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32.768 cycle counter that generates the 1.0 Hz timer and RTC registers; see Real Time Clock (RTC) for more detail. REAL TIME CLOCK (RTC) The RTC block provides a real-time clock with time-of-day, year, month, and date, as well as daily alarm capabilities. The real- time clock will use the 32.768 kHz oscillator as its input clock. The real-time clock will be powered by the coin cell backup battery as a last resort, if no other power source is available (Battery or USB/Wall plug). The register set is compatible with the Motorola™ MC146818 RTC device. Overview The RTC module uses a 15-bit counter to generate a 1.0 Hz clock for timekeeping. The seven time and calendar registers keep track of seconds, minutes, hours, day-of-week, day-of-month, month, and year. The three seconds, minutes, and hours alarm registers can be used to generate time-of-day alarm interrupts. The RTC time, alarm, and calendar values can be represented in 8-bit binary or BCD format. The hours and hours alarm values can be represented in 24 hour or 12 hour format, with AM/PM in the 12 hour mode. RTC control register B allows for software configurable clock formatting and interrupt masking. Control registers A, C, and D, report software testable RTC status, including interrupt flags, update-in-progress, and valid-RAM-time. The RTC resets when the RTCPORB signal is driven low. The clock and calendar registers will be initialized to 00:00:00, Sunday, January 1, 2000.

Analog Integrated Circuit Device Data

44 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) The RTC module includes the following features:

• Counts seconds, minutes, and hours of the day
• Counts days of the week, date, month, and year
• Binary or BCD representation of time, calendar, and alarm
• 12 or 24 hour clock with AM and PM in 12 hour mode
• Automatic leap year compensation
• Automatic end of month recognition
• 15 bytes of clock, calendar, RTC control, and coin cell registers
• Two interrupts are separately software maskable and testable
• Time-of-day Alarm
• End-of-clock update cycle interrupt
• 15-bit counter to generate 1.0 Hz RTC clock
• Software testable Valid-ram-and-time status bit indicates data integrity MODES OF OPERATION Normal mode In Normal mode, the RTC module updates time and calendar registers using the internal 1.0 Hz RTC clock. Once per second, the alarm registers are compared to the current time, and if enabled, an alarm interrupt will occur when the alarm time matches the current time. During normal operation, all 14 bytes of RTC and coin cell battery registers can be read through the SPI interface. Control register B may be updated to enable End-of-clock Update interrupts, alarm interrupts, or to put the RTC in Set mode. The coin cell charger register is available for R/W in normal mode. Coin Cell mode When the application is powered down, the RTC will continue to keep track of time using power provided by the coin cell battery. Since the system SPI will be powered down during this time, there is no read or write access to the RTC registers in Coin Cell mode. Set mode In Set mode, the clock and calendar updates are suspended, and the software may update the time, calendar, and alarm registers. The time and calendar formats must match the formats specified by the DM and 12/24 format bits in RTC register B. When the format bits are modified, all 14 time, calendar, and alarm registers must be updated in the specified format. Scan/Test mode Internal Test mode not available for the end application. Setting the Time, Calendar, and Alarm Before initializing the internal registers, the Set bit in Register B should be set to a "1" to prevent time/calendar updates from occurring. Select the RTC data format by writing the appropriate values to the DM and 24/12 bits in Register B. This can all be done simultaneously with one SPI write to register B. Next, the program should initialize all 10 time, calendar, and alarm locations, in the format specified by Register B (binary or BCD, 12 or 24 hour). All 10 time, calendar, and alarm bytes must use the same data mode, either binary or BCD. Both the alarm hours, and the hours bytes must use the same hours format, either 12 or 24. The Set bit may now be cleared to allow updates. Once initialized, the real-time clock makes all updates in the selected data mode. The data mode (DM) cannot be changed without re-initializing the 10 data bytes. The 24/12 bit in Register B establishes whether the hour locations represent 1-to-12 or 0-to-23. When the 12 hour format is selected the high order bit of the hour bytes represents PM when it is a "1". The 24/12 bit cannot be changed without re-initializing the hour and alarm-hour locations. Table 18 shows the binary and BCD formats of the 10 time, calendar, and alarm locations.

the alarm is only updated by a SPI write instruction, the three alarm registers may be read at any time and will always be defined. (assuming the reads are done sequentially, and uninterrupted): (25 * 7) / (12.5 MHz) = 14 μs. the registers read before the update would not. should be considered undefined. Similarly, all seven bytes should be read between updates to get a consistent time and date. explains how to accommodate the update cycle in the processor program. an existing update and preventing a new one from occurring. corresponding time byte, and issues an alarm if a match is present in all three positions. Table 18. Time, Calendar, and Alarm Data Modes

1. Example: 11:58:21 Thursday 15 February 2008 (time is AM)

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FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Two methods of avoiding undefined output during updates are usable by the program. In discussing the two methods, it is assumed that at random points, user programs are able to call a subroutine to obtain the time of day. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every update cycle, which indicates that over 999 ms are available to read valid time and date information. Before leaving the interrupt service routine, the IRQF bit in Register C should be cleared. The second method uses the update-in-progress bit (UIP) in Register A, to determine if the update cycle is in progress. The UIP bit will pulse once per second. Statistically, the UIP bit will indicate that time and date information is unavailable once every 3,640 attempts. After the UIP bit goes high, the update cycle begins 244.1 μs later. Therefore, if a low is read on the UIP bit, the user has at least 244.1 μs before the time/calendar data will be changed. If a “1” is read in the UIP bit, the time/calendar data may not be valid. The user should avoid interrupt service routines which would cause the time needed to read valid time/calendar data to exceed 244.1 μs. The RTC uses seven synchronous counters to increment the time and calendar values. All seven timekeeping registers are clocked by the same internal 1.0 Hz clock, so updates occur simultaneously, even during rollover. After the counters are incremented, the current time is compared to the time-of-day alarm registers 30.5 μs later, and if they match, the AF bit in register C will be set. The Update-cycle begins when the clock and calendar registers are incremented, and ends when the alarm comparison is complete. During this 30.5 μs update cycle, the time, calendar, and alarm bytes are fully accessible by the processor program. If the processor reads these locations during an update, the transitional output may be undefined. The update in progress (UIP) status bit is set 244.1 μs before this interval, and is cleared when the update cycle completes. Interrupts The RTC includes two separate, fully automatic sources of interrupts to the processor. The alarm interrupt may be programmed to occur at a rate of once per day. The update-ended interrupt may be used to indicate to the program that an update cycle is completed. The processor program selects which interrupts, if any, it wishes to receive. Two bits in Register B enable the two interrupts. Writing a “1” to an interrupt-enable bit permits that interrupt to be initiated when the event occurs. A “0” in the interrupt-enable bit, prohibits the IRQF bit from being asserted due to the interrupt cause. If an interrupt flag is already set when the interrupt becomes enabled, the IRQF bit is immediately activated, though the interrupt initiating the event may have occurred much earlier. Thus, there are cases where the program should clear such earlier initiated interrupts before enabling new interrupts. When an interrupt event occurs, a flag bit is set to a “1” in Register C. Each of the two interrupt sources have separate flag bits in Register C, which are set independent of the state of the corresponding enable bits in Register B. The flag bit may be used with or without enabling the corresponding enable bits. In the software scanned case, the program does not enable the interrupt. The interrupt flag bit becomes a status bit, which the software interrogates when it wishes. When the software detects the flag is set, it is an indication to the software an interrupt event occurred since the bit was last read. However, there is one precaution. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included with Register C, so the bits which are set are stable throughout the read cycle. All bits which are high when read by the program are cleared, and new interrupts (on any bits) are held until after the read cycle. One or two flag bits may be found to be set when Register C is used. The program should inspect all utilized flag bits every time Register C is read to insure that no interrupts are lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQF bit is asserted high. IRQF is asserted as long as at least one of the two interrupt sources has its flag and enable bits both set. The processor program can determine that the RTC initiated the interrupt by reading Register C. A “1” in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the part. The act of reading Register C clears all the then active flag bits, plus the IRQF bit. When the program finds IRQF set, it should look at each of the individual flag bits in the same byte, which have the corresponding interrupt mask bits set and service each interrupt which is set. Again, more than one interrupt flag bit may be set. ALARM INTERRUPT The three alarm bytes may be used to generate a daily alarm interrupt. When the program inserts an alarm time in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day, if the alarm enable bit is high.

approximately 1.2 seconds per month. bit in the Trim register determines if periodic adjustments are made to speed up or slow down the clock. from 0-63. For example, TRIMVAL = 0x08 then 8 seconds out of every 64 will be adjusted up or down, according to the SIGN bit. Table 19. RTC Date/Time Configuration Register Structure and Bits Description

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Table 20. RTC Control Registers Structure and Bit Description

x0 = The update cycle functions normally by advancing the counts once-per-second. update occurring in the midst of initializing. UF 4 Update-Ended Interrupt Flag. Set after each update cycle. AF 5 Alarm Interrupt Flag. Indicates that the current time has matched the alarm time. VRT 7 The Valid RAM and Time (VRT) bit indicates the condition of the contents of the RTC time and calendar registers. be set by reading register D. clears the BKDET to get ready for the next event. registers by the system controller. Their contents are erased on RTCPORB.

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1. No Power State: No input voltage is available at the

main supply or the coin cell battery input.

1. Active State: The PMIC has enough power to supply
2. RTC State: The PMIC has enough power to support

not enough to power the rest of the system.

1. VPWR: This is the main s upply to the system. It must

be externally connected to VBAT.

1. VBAT: This is the main supply voltage sensing input.
2. VCOINCELL: This is the backup input voltage, typically

from a rechargeable coin cell battery. Figure 17 shows the 900844 internal power tree.

Figure 17. 900844 Internal Power Tree Block Diagram

1. V COREREF: This is the main bandgap and reference voltage for all internal circuitries.
2. V CORE: This is the supply for the internal analog circuitry.
3. V COREDIG: This is the supply for the internal digital circuitry.

Table 21 summarizes the voltage references on the 900844. powered from VBOS is now powered from VCOREDIG. Table 21. 900844 Internal Power Supply Summary Bypass Capacitor 100 nF typ. Bypass Capacitor 2.2 μF typ. Bypass Capacitor 2.2 μF typ.

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states. This diagram serves as the basis for the description in the remainder of this section. Figure 18. 900844 Power States

Analog Integrated Circuit Device Data Freescale Semiconductor 53 900844 FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL No Power State In this state, every source of power has been removed or is fully depleted:

• V BAT < VBATOFF: The input voltage is under the cutoff threshold, indicating that the main supply has been removed, or has been isolated by its own protection circuitry, and
• V COIN < VCOINOFF: The coin cell backup battery has been removed or has been isolated by the 900844 coin cell discharge prevention circuitry (see Coin Cell Battery Backup/Charger) The 900844 has lost any source of power to maintain the RTC and its keep alive registers, and all the internal circuits power down and time of day cannot be kept. RTC State In this state, the 900844 has limited power. The VBOS is available and powers the RTC and the Keep Alive Registers. However, the system does not have enough power to enter the active state:
• V COIN > COINOFF: The backup battery is above the coin cell disconnect threshold.
• V PWR < VPWRUVF: The system voltage is less than the under-voltage falling threshold. During this mode, all voltage regulators are off and cannot be powered. The RTC is operating (Real Time Clock (RTC)), and the time of day and all keep alive registers are maintained. Active State In this state, the 900844 internal circuits are fully powered:
• V PWR > VPWRUVR: The system voltage, VPWR, is available and valid, and
• V BAT > VLOWBAT: The main input voltage is above a low battery condition. All features of the 900844 are either operating or can be enabled, which is under the control of the System Control Unit (SCU) within the Platform Controller Hub (PCH). Power State Transitions When power is applied to the 900844 for the first time, it goes from the No Power state into the Active state, with a brief transition through the RTC state. The RTC and the Keep Alive Registers are powered, and the time of day is initialized to a factory set value (See Real Time Clock (RTC)). When VPWR crosses the under-voltage rising detection threshold (VPWRUVR), the internal supplies power on, the logic is reset, the initial power sequence is performed, SPI communication is enabled, and an interrupt to the Platform Controller Hub is generated. The PMIC enters the Active state and the system is under control of the SCU. If VPWR crosses the under-voltage falling detection threshold (VPWRUVF), and at least one of the VBOS supplies (VCOIN or VBAT) is still valid, the 900844 enters the RTC state. Only the RTC is operating and the RTC and Keep Alive registers are maintained. If the 900844 is in the RTC state, full operation is obtained when the voltage at VPWR crosses again the under-voltage rising detection threshold (VPWRUVR). TURN ON EVENTS A turn on event occurs when a valid input voltage is present at VBAT (VBAT > VLOWBAT), and the system voltage goes above the under-voltage rising threshold (VPWR > VPWRUVR). Otherwise, the 900844 is in the RTC or No Power State. When a turn on event occurs, the BATDET interrupt bit is set. Reference Interrupt Controller for more information on the different system interrupts.

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Figure 19. 900844 Initial Power Up Sequence

1. A valid system voltage is applied
2. The 900844 internal circuits are powered
3. The 900844 turns on a minimal set of voltage rails as
4. SPI communication is ready
5. The system controller un it (SCU) reads the 900844

interrupted the platform controller hub.

1. The SCU decides wh ether to boot the rest of the system,

or just run SCU code to manage various functions.

1. If the SCU decides to power up system, then CPU
2. The 900844 drives CPU selected voltage for VNN
3. There will be no explicit signaling from the 900844 that

indicates that the VNN ramp has been complete.

1. VIDEN[1:0] is driven to 00 to avoid it switching from 10 to
2. The CPU drives the VCC boot VID on the VID pins. The

VIDEN[1:0] = 1 enables, only after HPLL has locked.

1. X86 Instruction Executions starts.

Table 22. 900844 Initial Power Up Timing

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Figure 22. 900844 Power Map Table 23. Power States Detection Thresholds

• OFF - The regulator is switched o ff and the output voltage is discharged.
• PFM - The regulator is switched on and set to PFM mode opera tion. In this mode, the regulator is always running in PFM mode. Useful at light loads for optimized efficiency.
• Automatic Pulse Skip - The regulator is switched on and set to Automatic Pulse Skipping. In this mode, the regulator moves automatically between pulse skipping and full PWM mode depending on load conditions.
• PWM - The regulator is switched on and set to PWM mode. In this mode, the regulator is always in full PWM mode operation regardless of load conditions.
• TEST/TRIM - This is not a functional mode, thus requiring certain steps to prevent unintentional activation of this mode. During this mode, the device performs measurements and trimming. DC-DC Power Supply Summary Table Table 24 provides a summary of all DC/DC regulators on the 900844. Note that all of the DC/DC regulators specify an extended input voltage range beyond the 3.0 to 4.4 V applications range. Below this, extended range functionality is maintained, but parametric performance could be compromised. VCC This is a VID controlled single-phase 1.0 MHz 2-switch synchronous Buck PWM voltage mode control DC/DC regulator, designed to power high performance CPUs. VCC uses external MOSFETs, P-Ch high side and N-Ch low side. VCC includes support for VID active voltage positioning requirements. A 7-bit DAC reads the VID input signals and sets the in real time and will be stored in internal registers not accessible to the system host. Reference VIDEN[1:0] & VID[6:0] Pins for more details. The same VID input signals are shared between VCC and VNN, where a latch signal for each regulator decides which regulator takes control of the VID input signals. The DAC value represents the output voltage value. The output voltage node is connected directly to the inverting input of the error amplifier that uses the DAC output as its reference, unity gain configuration. Using this configuration with internal compensation eliminates the need for the feedback and compensation network, which saves board space and cost. The DAC/ output voltage slew rate is internally set 25 mV/µs to minimize transient currents and audible noise.

Table 24. 900844 DC-DC power supplies. signals for VCC or VNN selection. signals for VCC or VNN selection.

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battery life based on load conditions. VCC will be discharged every time the regulator is shutting down. circuitry, which eliminates the need for an external RC filter network in parallel with the output inductor and its winding resistance. the voltage across RW in a similar fashion, while using internal sensing circuitry. turn assert the VRFAULT Interrupt signal. Figure 23. VCC Detailed Internal Block Diagram

• Uses the V PWR rail as its power supply
• It is used to provide power to the CPU Core.
• Single-phase Solution with Integrated Drivers and external MOSFETs
• VID Controlled for dynamic voltage scaling requirements of high performance processors
• 1 . 0 MHz switching frequency
• High efficiency operating modes depending on load conditions
• Output can be discharged through the low side switch.
• Loss-Less Output Current Sensin g with over-current protection
• Uses internal compensation
• Gate drive circuits are supplied directly from VPWR Efficiency Curves The efficiency curves in Figure 24 are calculated under PWM mode, based on the recommended external component values GNDREFVCC Driver Controller EA Internal Compensation VOUTFBCC VPWR COCC CINCC LCCVCC HSCCGT LSCCGT PGNDCC Current Sense Amp CSPCC ICC PVINCC SWFBCC SPI Interface CTLVCC AOACCTLVCC VCCFAULT VREF DAC VID6 VID5 VID4 VID3 VID2 VID1 VID0 MHSCC MLSCC VIDEN0 VIDEN1

Figure 24. VCC Efficiency Curve Reference the register map for read/write conditions and default state for each of these registers. designed to power high performance CPUs. VNN uses external MOSFETs, P-ch high side and N-ch low side. in real time and will be stored in internal registers not accessible to the system host. Reference VIDEN[1:0] & VID[6:0] Pins. Table 25. VCC Status Registers Structure and Bits Description system SPI controller after power up. DVP1VRD 7 VCC Register override enable bit.

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regulator takes control of the VID input signals. output voltage slew rate is internally set 25 mV/µs to minimize transient currents and audible noise. battery life based on load conditions. VNN will be discharged every time the regulator is shutting down. turn assert the VRFAULT Interrupt signal. Figure 25. VNN Detailed Internal Block Diagram

• Uses the V PWR rail as its power supply
• It is used to provide po wer to the Graphics Core.
• Single-phase Solution with Integrated Drivers and external MOSFETs
• VID Controlled for dynamic voltage scaling requirements of high performance processors
• 1 . 0 MHz switching frequency
• High efficiency operating modes depending on load conditions
• Output can be discharged through the low side switch.
• Loss-Less Output Current Sensin g with over-current protection
• Uses internal compensation
• Gate drive circuits are supplied directly from VPWR Efficiency Curves Figure 26 efficiency curves are calculated under PWM mode based on the recommended external component values and Driver Controller EA Internal Compensation VOUTFBNN VPWR CONN CINCC LNNVNN HSNNGT LSNNGT PGNDNN CSPNN PVINNN SWFBNN SPI Interface CTLVNN AOACCTLVNN VNNFAULT VREF DAC VID6 VID5 VID4 VID3 VID2 VID1 VID0 MHSNN MLSNN Current Sense Amp INN VIDEN0 VIDEN1

Figure 26. VNN Efficiency Curve This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator. include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. VDDQ will be discharged every time the regulator is shutting down. Table 26. VNN Status and Control Registers Structure and Bits Description by the system SPI controller after power up. DVP1VRD 7 VNN Register override enable bit.

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VDDQ is originally prepared to provide 1.8 V by connecting VDDQ output voltage directly to FBDDQ node, refer to Figure 27.

• RFBDDQ15_1 = 680 Ω
• RFBDDQ15_2 = 2.21 kΩ

Figure 27. VDDQ Detailed Internal Block Diagram (VDDQ at 1.8 V) Figure 28. VDDQ Detailed Internal Block Diagram (VDDQ at 1.5 V)

• Uses the V PWR rail as its power supply
• It is used as a pre-regulator to many LDO rails, for enhanced efficiency and reduced thermal dissipation. It also supplies power to rails in the CPU (central processing unit), Platform controller hub, and the platform
• Uses Integrated MOSFETs
• 4 . 0 MHz switching frequency
• High efficiency operating modes depending on load conditions
• Output can be discharged through the low side switch.
• Peak current sensing with over-current protection Driver Controller EA VRE F Internal Compensation PVINDDQ SWDDQ FBDDQ ISENSE 5 VPWR CODDQ CI NDDQ LDDQ SPI Interface PGNDDDQ VDDQ CTLVDDQ AOACCTLVDDQ VDDQFAULT Driver Controller EA VREF Internal Compensation PVINDDQ SWDDQ FBDDQ ISENSE5 VPWR CODDQ CINDDQ LDDQ SPI Interface PGNDDDQ VDDQ CTLVDDQ AOACCTLVDDQ VDDQFAULT VCORE RFBDDQ15_2 RFBDDQ15_1

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The output current is measured internally, digitized by the ADC, and stored in a register for the processor to access. turn assert the VRFAULT Interrupt signal. Figure 30. V21 Detailed Internal Block Diagram

• Uses the V PWR rail as its power supply
• It is used as a pre-regulator to many LDO rails, for enhanced efficiency and reduced thermal dissipation.
• Uses Integrated MOSFETs
• 4 . 0 MHz switching frequency
• High efficiency operating modes depending on load conditions
• Output can be discharged through the low side switch.
• Peak current sensing with over-current protection
• Uses internal compensation
• Gate drive circuits are supplied directly from VPWR Efficiency Curves Figure 31 efficiency curves are calculated under PWM mode, based on the recommended external component values and Driver Controller EA VRE F Internal Compensation PVIN 21 SW21 FB21 ISEN SE 5 VPWR CO21 CIN 2 1 L21 SPI Interface PGND21 V21 CTLV21 AOACCTLV21 V21FAULT

Figure 31. V21 Efficiency Waveforms

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Reference the register map for read/write conditions and default state for each of these registers. This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage-mode control DC/DC regulator. battery life based on load conditions. V15 will be discharged every time the regulator is shutting down. The output current is measured internally, digitized by the ADC, and stored in a register for the processor to access. turn assert the VRFAULT Interrupt signal. Figure 32. V15 Detailed Internal Block Diagram

• Uses the V PWR rail as its power supply
• It is used as a pre-regulator to many LDO rails, for enhanced efficiency and reduced thermal dissipation. It also supplies power to rails in the Platform controller hub
• Uses Integrated MOSFETs

Table 28. V21 Status/Control Registers Structure and Bits Description

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION POWER SUPPLIES LDO POWER SUPPLIES Freescale’s power management solution for the Ultra-mobile platform for Netbooks, Tablets, and Slates includes 14 LDO regulators, all of which are housed in the 900844 PMIC. LDO OPERATION MODES SELECTIONS

• OFF - The regulator is switched off
• ACTIVE - The regulator is switched on and the output is at the programmed level. The maximum load current is allowed.
• LOW POWER - The regulator is switched on and the outputs is at the programmed level. The load current is limited.
• TEST/TRIM - This is not a functional mode, thus requiring certain steps to prevent unintentional activation of this mode. During this mode, the device performs measurements and trimming. All LDOS are able to work in a low power mode, in which the bias current is reduced. The output drive capability and performance are limited in this mode. This mode occurs automatically when the load current decreases below the low power mode limit, except on VBG and VMM, in which this mode can only be set through SPI programming. All other LDOS can set the low power mode through SPI programming. Note: If low power mode is set through the SPI at a load current higher than the maximum allowed, the performance of the LDO is not guaranteed. Table 30 is a summary of LDO characteristics

Table 30. 900844 LDO Power Supplies Summary

Description

VBG 1.25 V 2.0 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VCCA 1.5 V 150 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VCC180 1.8 V 390 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VPNL18 1.8 V 225 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VPMIC 1.8 V 50 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VYMXYFI18 1.8 V 200 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VCCPAOAC 1.05 V 155 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VCCPDDR 1.05 V 60 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VAON 1.2 V 250 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VMM 1.2 V 5.0 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VCCP 1.05 V 445 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VIMG25 2.5 V 80 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VIMG28 1.5 - 2.9 V 225 mA Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VSDIO 1.8 or 3.3 V 215 mA VSDIO is a combo Low Dropout (LDO) and power switch. It uses an external P-CH Pass FET, applicable only in power switch mode. VSDIO serves as an LDO when its output voltage is set to 1.8 V, and as a switch when its output voltage is set to 3.3 V.

PSRR, with a low quiescent current and fast transient response. VBG is actively discharged during shutdown. Figure 34. VBG Detailed Internal Block Diagram

• Uses VDDQ or V21 as the main power supply
• 2 . 0 mA maximum continuous output current
• Optimized for a 1.0 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VBG Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers. VCCA VCCA is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCA is actively discharged during shutdown.

Table 31. VBG Control Register Structure and Bits Description by the system SPI controller after power up.

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Figure 35. VCCA Detailed Internal Block Diagram

• Uses VDDQ or V21 as the main power supply
• 150 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VCC180 VCC180 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCC180 is actively discharged during shutdown. VCC180 shares an input voltage pin (PVIN2P1) and a reference ground pin (GND2P1) with VPNL18 and VPMIC regulators, yet each has independent control. PVIN2P1 is supplied from the V21 voltage. The output current for VCC180 is measured and reported through the ADC. Reference ADC Subsystem for more information.

Table 32. VCCA Control Register Structure and Bits Description by the system SPI controller after power up.

Figure 36. VCC180 Detailed Internal Block Diagram

• Uses V21 as the main power supply
• 390 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VPNL18 VPNL18 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VPNL18 is actively discharged during shutdown. VPNL18 shares an input voltage pin (PVIN2P1) and a reference ground pin (GND2P1) with VCC180 and VPMIC regulators, yet each has independent control. PVIN2P1 is supplied from the V21 voltage.

Table 33. VCC180CNT Register Structure and Bits Description initialized by the system SPI controller after power up.

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Figure 37. VPNL18 Detailed Internal Block Diagram

• Uses V21 as the main power supply
• 225 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VPMIC VPMIC is a low drop-out (LDO) fully integrated regulator with a P-CH pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VPMIC is actively discharged during shutdown. VPMIC shares an input voltage pin (PVIN2P1) and a reference ground pin (GND2P1) with VCC180 and VPNL18 regulators, yet each has independent control. PVIN2P1 is supplied from the V21 voltage.

Table 34. VPNL18 Control Register Structure and Bits Description initialized by the system SPI controller after power up.

Figure 38. VPMIC Detailed Internal Block Diagram

• Uses V21 as the main power supply
• 100 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VYMXYFI18 VYMXYFI18 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VYMXYFI18 is actively discharged during shutdown. VYMXYFI18 can be supplied by either the V21 output voltage (V21) or directly from the VPWR node. Using V21 as the input voltage supply offers enhanced thermal performance and higher efficiency. Using the VPWR node can offer enhanced performance against noise coupling from an output of a DC/DC regulator. Users are encouraged to take the resulting thermal dissipation in account when supplying VYMXYFI18 directly from VPWR. For more information about package thermal capabilities, reference Thermal Management.

Table 35. VPMIC Register Structure and Bits Description initialized by the system SPI controller after power up.

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Figure 39. VYMXYFI18 Detailed Internal Block Diagram

• Uses V21 or VPWR as the main power supply
• 200 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VCCPAOAC VCCPAOAC is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCPAOAC is actively discharged during shutdown. VCCPAOAC shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with VCCPDDR, VAON, VMM, and the VCCP regulator. Each has independent control. PVIN1P5 is supplied from the V15 voltage.

Table 36. VYMXYFI18 Register Structure and Bits Description be initialized by the system SPI controller after power up.

Figure 40. VCCPAOAC Detailed Internal Block Diagram

• Uses V15 as the main power supply.
• 155 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VCCPDDR VCCPDDR is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCPDDR is actively discharged during shutdown. VCCPDDR shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VAON, VMM, and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from the V15 voltage.

Table 37. VCCPAOACCNT Register Structure and Bits Description will be initialized by the system SPI controller after power up.

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Figure 41. VCCPDDR Detailed Internal Block Diagram

• Uses V15 as the main power supply
• 6 0 mA maximum continuous output current
• Optimized for a 1.0 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VAON VAON is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VAON is actively discharged during shutdown. VAON shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VMM, and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from the V15 voltage.

Table 38. VCCPDDR Control Register Structure and Bits Description initialized by the system SPI controller after power up.

Figure 42. VAON Detailed Internal Block Diagram

• Uses V15 as the main power supply
• 250 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VMM VMM is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VMM will be actively discharged during shutdown. VMM shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VAON, and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from V15 voltage.

Table 39. VAON Control Register Structure and Bits Description by the system SPI controller after power up.

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Figure 43. VMM Detailed Internal Block Diagram

• Uses V15 as the main power supply
• 5 . 0 mA maximum continuous output current
• Optimized for a 1.0 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VCCP VCCP is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCP is actively discharged during shutdown. VCCP shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VAON, and VMM regulators, yet each has independent control. PVIN1P5 is supplied from V15 voltage.

Table 40. VMM control Register Structure and Bits Description by the system SPI controller after power up.

Figure 44. VCCP Detailed Internal Block Diagram

• Uses V15 as the main power supply
• 445 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VIMG25 VIMG25 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VIMG25 is actively discharged during shutdown. VIMG25 shares an input voltage pin (PVINIMG) and a reference ground pin (GNDIMG) with the VIMG28 regulator, yet each has independent control. Both can be supplied by the VPWR (3.3 V) node.

Table 41. VCCP Control Register Structure and Bits Description initialized by the system SPI controller after power up.

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Figure 45. VIMG25 Detailed Internal Block Diagram

• Uses VPWR (3.3V) as the main power supply
• 8 0 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VIMG28 VIMG28 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VIMG28 is actively discharged during shutdown. VIMG28 shares an input voltage pin (PVINIMG) and a reference ground pin (GNDIMG) with the VIMG25 regulator, yet each has independent control. Both can be supplied by the VPWR (3.3 V) node. This LDO is optimized to work with 300 mV headroom, which leaves enough margin between the input and the highest output of this LDO. For more information about package thermal capabilities, reference Thermal Management.
• Note: At high VIMG28 output voltage selections, the output will start tracking the battery voltage when VBAT decreases below VOIMG28 + 300 mV.

Table 42. VIMG25 Register Structure and Bits Description initialized by the system SPI controller after power up.

Figure 46. VIMG28 Detailed Internal Block Diagram

• Uses 3.3 V or VPWR as the main power supply
• 225 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses internal pass FET
• The output for each LDO is monitored for ov er-current conditions and under-voltage events VSDIO VSDIO is a combo low drop-out (LDO) and power switch. It uses an external P-CH pass FET in Switch mode, and internal pass FET on LDO mode. VSDIO serves as an LDO when its output voltage is set to 1.8 V, and as a switch when its output voltage is set to 3.3 V. It takes its input voltage directly from the 3.3 V output voltage node. VSDIO supplies the SDIO card module. The card is initially powered up to 3.3 V. If the card is detected to be a low voltage card, then the rail will be shutdown, configured as 1.8 V, and then turned on. VSDIO will be actively discharged during shutdown.

Table 43. VIMG28 Control Register Structure and Bits Description initialized by the system SPI controller after power up.

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Figure 47. VSDIO Detailed Internal Block Diagram

• Uses 3.3 V as the main power supply
• 215 mA maximum continuous output current
• Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR
• Uses an internal pass FET on LDO mode, and external pass FET on Switch mode.
• The output is monitored for under-voltage an d over-current conditions in LDO mode. POWER SWITCHES Freescale’s power management solution for the Ultra-mobile platform for Netbooks, Tablets and Slates, includes 1 dedicated power switch, housed in the 900844 PMIC. Table 45 shows its power characteristics. VPNL33 uses an internal switch and are supplied from the 3.3 V output voltage. VPNL33 uses an internal switch and are supplied from the 3.3 V output voltage.

Table 44. VSDIO Control Register Structure and Bits Description by the system SPI controller after power up. Table 45. 900844 Power Switch Voltage Rail VPNL33 3.3 V 100 mA Power Switch with integrated MOSFET and less than 1% voltage drop.

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communicate to the system controller. can be read out via the ADC for precise temperature readouts. See ADC Subsystem. the system controller of a system event. the application design should execute a thermal shutdown under normal conditions. Table 49. Thermal Warning/Shutdown Thresholds Table 48. Ramp Rate Control Registers (Freescale Defined)

• Output under-voltage
• Output over-voltage
• Over-current
• Short-circuit Reference each power supply’s section for more information on what faults are included, and how the supply protects itself and the load in response to the fault. All of the xxxFAULT signals from all power supplies are ORed together into the BATOCP interrupt signal, which if unmasked, sets the VRFAULT 1st level interrupt that causes the PMICINT pin to assert, notifying the SC of a system event. The SC can service the VRFAULT register and access the FAULTx registers for more information on which supply caused the fault. The SC can then take different measures, depending on the supply in question. The xxxFAULT signals are stored in the Freescale defined registers section (Addr 0x180 - 0x1FF), which is meant for extended functionality.

Table 50. FSLFAULT1 Fault Status Register Structure and Table 51. FSLFAULT2 Fault Status Register Structure and

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0 VYMXYFI18 Regulator Fault Signal

3 VCCPAOAC Regulator Fault Signal

4 VCCPDDR Regulator Fault Signal

Table 53. FSLFAULT4 Fault Status Register Structure and Table 54. Fault Management Status and Control Register

goes below VPWRUVF. Reference Power Path Manager SPI Registers for a more detailed description of the coin cell related bits. currents from external components or by the 900844, the COINCHGEN bit should always remain set. Table 55. Input Power Interrupt/Mask Registers Structure and Bits Description

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ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. Table 56. FSL Charger Control Register Structure and Bits Description

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will convert over the entire scaled version of the input channel, so always from a 2.40 V, full scale. Table 3. In that case, the readout value will be lower than expected due to the dynamic input impedance of the ADC converter. 100 nF bypass capacitor at the ADIN input concerned.

1. Equivalent to -3.0 to +3.0 A of current with a 20 mOhm sense resistor

Table 57. ADC Inputs

• VPWRCON for channel 22
• LICON for channel 25 CONTROL The ADC block consists of a 5-bit wide, 32-entry register file, which stores the address of the analog input for sampling. The 10-bit result is then stored in a separate register file 10+1 bits wide and 32 entries deep. In order to operate the ADC, it has to be enabled first by setting the ADEN bit high in the ADCCNTL1 register. When the register ADCCNTL1 ADSTRT bit is enabled, the PMIC will cycle through the 3 + 5 bit selector addresses in registers ADCADDRx. The high 3-bits control the touch screen bias FETs, as described in Touch Screen Interface. The lower 5-bits address the ADC selector to connect one of 32 channels to the ADC. The result of the ADC conversion is stored into the result registers (ADCSNSx), along with the input gain setting (1 MSB). An address in the selector table of 0x1F designates the stop location of the selection loop. At which point the interrupt flag bit 0 (RND), which can be masked through the MRND bit in the MADCINT register, is set in register ADCINT, bit 1 of the INTERRUPT register (ADC) is set, and the external PMICINT signal is asserted, if bit 1 of the INTMASK register is clear. The ADC sleeps for 0 to 27 ms as set by ADC register ADCCNTL1 through the ADSLP[2:0] bits and then repeats the selector cycle. The new data overwrites the old in the result registers. At most, all 32 result registers will be filled within 15.625 ms (2048/32 = 1/64 Hz). The result registers will not be read until the RND flag is set. DEDICATED CHANNELS READING Two different LSB value settings are possible by using the LSBSEL bit in the FSLADCCNTL register. LSBSEL = 0 is the default setting. See Table 59 for more information

Table 58. Possible Reserved Channels Usage

23 Reserved Reserved Reserved Reserved

24 Reserved Reserved Reserved Reserved

26 Reserved Reserved Reserved Reserved

27 Reserved Reserved Reserved Reserved

28 Reserved Reserved Reserved Reserved

29 Reserved Reserved Reserved Reserved

30 Reserved Reserved Reserved Reserved

31 Reserved Reserved Reserved Reserved

Table 59. ADC LSB Settings

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The load current sourced by a select set of regulators can be measured and recorded by the ADC on channels 1 through 5. Table 61 shows a summary of these regulators, type, and their current ranges. scaling factor of 10 (for an input range of 200 mV). Table 60. PMIC Die Temperature Voltage Reading Table 61. Regulators Current Sensing Table 62. Battery Voltage Reading Coding Table 63. General Purpose Analog Inputs Reading Coding

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(X-), while the Y plate is connected to ADIN12(Y+) and ADIN13(Y-). A local supply, TSREF, of 1.2 V will serve as a reference. the bias control will always be programmed to no bias. Figure 50 is a touch screen representation. Figure 50. Touch Screen Configuration Example Table 64. Application Supply Voltage Reading Coding Table 65. Backup (Coin Cell) Voltage Reading Coding

system, because a touch screen pen touch has been detected at the next ADC cycle, unless the interrupt is masked. touch screen conversions, the ADC does not rely on TSREF and the reference can be disabled. 10-bit ADC reading represents the voltage drop over the contact resistance created by the known current source multiplied by 2. Table 66. Touch Screen System Requirements Table 67. ADC Interrupt/Mask Registers Structure and Bits Description

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Table 68. ADC Control Registers Structure and Bits Description

Table 69. ADC Channel Selector/Configuration Structure and bit Description

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION GPIOS ADC STATUS/CONTROL REGISTERS AND BIT DESCRIPTION GPIOS The 900844 has eight GPIOs, and eight GPOs for platform control. As outputs, the GPIOs support CMOS/OD signaling levels, based on the voltage level on the GPIOVCC. The GPOs support CMOS signaling levels, based on the voltage level on the GPOVCC pin. As inputs, they are 3.6 V tolerant and are de-bounced for a period of no more than 10 ms minimum. The 900844 provides one bank of eight configurable GPIO inputs/outputs, GPIO[7:0] for general purpose sensing and platform control. Only GPIOs support an input function. GPIOs switch between a high-impedance (>1.0 MΩ) state and a low-impedance (20 Ω nominal) state when operating in open drain mode. When operating in CMOS mode, the outputs drive from the voltage supplied on the GPIOVCC pin with a 20 Ω output drive capability (for GPIOs). The electrical characteristics of the output buffer will therefore be specified as relative percentages of the driving supply. Any unused GPIO pin should be tied to ground on the board. When any GPIO is configured as an open drain, the pull-up voltage cannot exceed that of the GPIOVCC Voltage level. Table 71 shows the default state of the different GPIOs and their capabilities. Table 70. Extended ADC Control Register Structure and Bits Description Table 71. GPIOs Capabilities and Default States

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GPIO module has a single 8-bit status and control register assigned to it. See Table 72 for details. The “x” in the bit names in the tables is from 0 to 7 for the GPIOs. Table 72. GPIO Register Structure and Bits Description to be invalid by the system controller. The PMIC should de-bounce the inputs over 1-10 ms to insure a clean transition.

1. See GPIOs electrical characteristics on Table 3
2. An unintended interrupt is caused if interrupt settings are re configured in the middle of an application, e.g. re-setting interrupt detection

GPIO interrupt detection to the new configuration, then clear Level 1 and level 2 interrupts, finally unmask the GPIO Interrupt.

sections for application guidance. Table 73. GPO Register Structure and Bits Description

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• Block: This corresponds directly to the chapter, section or topic in which the detailed register description is included.
• Address: The register memory map address allocation in HEX format
• Register Name
• R/W: Defines if the register is a Read /Write register or only a Read register
• D7-D0: The 8-bit data included in the register with each bit's name and location within the field included
• Initial: The register's default value after power up
• Function: A short description of the register's function Some important notes about data in the table:
• Reserved registers/bits are not implemented in the design and they will always read as a 0
• Registers under the "FSL" block are Freescale dedicated register s and are not defined in the customer specifications. These registers represent additional functionality that Freescale is offering to enhance the performance of the overall system
• Registers under the "VD2" and "VD3" blocks are blocked from being used by Freescale
• The table only displays up to address 0x2FF. Address space between 0x300 and 0x3FF is reserved for future application use. Freescale is currently using the 0x300 to 0x3FF space for test and debug register implementation. This will not effect the application or any future use plans for this address space. The details of this space implementation are not discussed in this document.

Table 74. SPI Register Map

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1. RSVD: Reserved registers, not for customer use.
2. FSL: Freescale dedicated Registers for special PMIC control

Table 75. External Components BOM (23)

1 SC900844JVK Freescale

1 XPL4020-681MLB Coilcraft

1. Throughout this document, there are references to non-Freescal e components. Freescale does not assume liability, endorse, or warrant

recommendations in this configuration, it is the customer’s responsibility to validate their application.

1. To operate the VDDQ as a 1.5 V buck regulator, the recommended resistors, RFBDDQ15_1 and RFBDDQ15_2 are needed in the

feedback path, as shown in Figure 28.

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1. This is a recommended resistor when required by a specific GPIO.

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For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. JVK SUFFIX 338-PIN 98ASA10841D REVISION 0

Analog Integrated Circuit Device Data Freescale Semiconductor 115 900844 PACKAGING PACKAGE DIMENSIONS JVK SUFFIX 338-PIN 98ASA10841D REVISION 0

Analog Integrated Circuit Device Data

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PACKAGE MECHANICAL OUTLINE DRAWING The package style is an 11x11 fine interstitial pitch, thin profile PBGA. The package has a semi populated matrix that includes 338 balls. The ball count includes 322 assigned signal pins and four sets of 4 corner balls. PACKAGE ASSEMBLY RECOMMENDATIONS For improved protection against mechanical shock, Freescale recommends applying corner glue to the mounted 900844 MAPBGA package. This corner glue application is described in the AN3954 - "PCB Layout Guidelines for SC900841 and SCCSP900842" application note. Freescale’s preferred material for the corner glue application is the Loctite 3128 board level adhesive, applied at a 0° or 45° dispense angle in a continuous motion, and with the fillet length extended to a minimum of 3 ball rows and columns, at each corner.

Analog Integrated Circuit Device Data Freescale Semiconductor 117 900844

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 1.0 8/2010 • Initial release

• Ball map updates
• Fix Default Values for Various VR control registers.
• Fix Package Suffix to “JVK”
• Freescale format, form and style corrections. 2.0 5/2011 • No parametrics were altered. Only various adjus tments, corrections, and clarifications were made to text, tables, and images, for improved accuracy.

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+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2010-2011. All rights reserved. SC900844 Rev. 2.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.