STL8NH3LL_06 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

N-channel 30V - 0.012Ω - 8A - PowerFLAT™ Ultra low gate charge STripFET™ Power MOSFET General features ■ Improved die-to-footprint ratio ■ Very low profile package (1mm max) ■ Very low thermal resistance ■ Very low gate charge ■ Low threshold device ■ In compliance with the 2002/95/EC Europen directive

Description

This application specific Power MOSFET is the latest generation of STMicroelectronics unique “STripFET™” technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The Chip-scaled PowerFLAT™ package allows a significant board space saving, still boosting the performance.

Applications

■ Switching application Internal schematic diagram Type V DSS R DS(on) ID STL8NH3LL 30V <0.015 Ω 8A (1) PowerFLAT™(3.3x3.3) (Chip Scale Package) TOP VIEW Order codes Sales Type Marking Package Packaging STL8NH3LL 8NH3L PowerFLAT™ (3.3 x 3.3) Tape & reel

Contents: STL8NH3LL Contents:

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. The value is rated according Rthj-pcb
  2. Pulse width limited by safe operating area.
  3. The vaule is rated according Rthj-c

Table 2. Thermal resistance

  1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec

2 Electrical characteristics

Table 3. On/off states Table 4. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%

Table 5. Switching times Table 6. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration=300µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

3 Test circuit

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A1 0.02 0.05 0.0007 0.0019 A3 0.20 0.0007 C 0.328 0.012 C1 0.12 0.004 D3 . 3 0 0 . 1 3 E3 . 3 0 0 . 1 3 F 1.325 0.052 F1 0.975 0.038 G 0.850 0.033 G1 0.250 0.009 PowerFLAT™ (3.3 x 3.3) MECHANICAL DATA

5 Revision history

Table 7. Revision history 18-Apr-2005 6 Modified Figure 3, Figure 5., Figure 8.,Figure 9.