IDT8N3S270 RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Fourth generation FemtoClock® NG technology
- Factory-programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz
- Frequency programming resolution is 218Hz and better
- One 2.5V or 3.3V LVPECL clock output
- Output enable control (positive polarity), LVCMOS/LVTTL compatible
- RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.24ps (typical), integer PLL feedback configuration
- RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.27ps (typical), integer PLL feedback configuration
- 2.5V or 3.3V supply
- -40°C to 85°C ambient operating temperature
- Available in a lead-free (RoHS 6) 6-pin ceramic package OE DNU VEE VCC nQ Q IDT8N3S270 6-lead ceramic 5mm x 7mm x 1.55mm package body Top View Pin AssignmentBlock Diagram Q nQOSC fXTAL ÷MINT, MFRAC PFD LPF FemtoClock® NG VCO 1950-2600MHz Configuration Register (ROM) 25 7 OE Pullup
IDT8N3S270CCD REVISION A MAY 15, 2012 2 ©2012 Integrated Device Technology, Inc. NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. 0 Outputs Q, nQ are in hi gh-impedance state. 1 (default) Outputs are enabled. NOTE: OE is an asynchronous control. Table 1. Pin Descriptions 1 OE Input Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 2D N U Do not use (factory use only). 3V EE Power Negative power supply. 4, 5 Q, nQ Output Differential clock output. LVPECL interface levels. 6 VCC Power Positive power supply. Table 2. Pin Characteristics
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 3 ©2012 Integrated Device Technology, Inc. Principles of Operation The block diagram consists of the internal 3RD overtone crystal and oscillator which provide the reference clock fXTAL of either 114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference. The feedback divider is fractional supporting a huge number of output frequencies. The configuration of the feedback divider to integer-only values results in an improved output phase noise characteristics at the expense of the range of output frequencies. Internal registers are used to hold one factory pre-set P, M, and N configuration setting. The P, M, and N frequency configuration supports an output frequency range from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz. The devices use the fractional feedback divider with a delta-sigma modul ator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determine d by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: fOUT fXTAL Frequency Configuration An order code is assigned to each frequency configuration programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. For more information on programming cababilities of the device for custom fre quency and pull-range configurations, see the FemtoClock NG Ceramic 5x7 Module Programming Guide.
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 4 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 49.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Table 4D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.8 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Item Rating Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 123 148 mA Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 119 143 mA Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.8 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Symbol Parameter
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 5 ©2012 Integrated Device Technology, Inc. Table 4E. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.3V 2 V CC + 0.3 V VCC = 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = VIN = 3.465V -0.3 0.8 V VCC = VIN = 2.5V -0.3 0.7 V IIH Input High Current OE V CC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE V CC = 3.465V or 2.625V, VIN = 0V -150 µA
IDT8N3S270CCD REVISION A MAY 15, 2012 6 ©2012 Integrated Device Technology, Inc. Table 5. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions.
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 7 ©2012 Integrated Device Technology, Inc. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Refer to the phase noise plot. NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes. NOTE 4: Integration range: 12kHz - 20MHz. NOTE 5: Integration range: 1kHz - 40MHz.
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 8 ©2012 Integrated Device Technology, Inc. Typical Phase Noise at 156.25MHz (12kHz - 20MHz) Noise Power dBc Hz Offset Frequency (Hz)
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 9 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Period Jitter Cycle-to-Cycle Jitter SCOPE Qx nQx VEE VCC -1.3V±0.165V Offset Frequencyf1 f2 Phase Noise Plot Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter = Noise Power 2 * * ƒ 1 * 20% 80% 80% 20% tR tF VSWING nQ Q SCOPE Qx nQx VEE VCC -0.5V± 0.125V VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nQ Q ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 10 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Applications Information Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 1A. 3.3V LVPECL Output Termination Figure 1B. 3.3V LVPECL Output Termination tPW tPERIOD tPW tPERIOD odc = x 100% nQ Q 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V
IDT8N3S270CCD REVISION A MAY 15, 2012 13 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the IDT8N3S270. Equations and example calculations are also provided. The total power dissipation for the IDT8N3S27 0 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 6 Lead Ceramic 5mm x 7mm Package, Forced Convection
IDT8N3S270CCD REVISION A MAY 15, 2012 14 ©2012 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
IDT8N3S270CCD REVISION A MAY 15, 2012 15 ©2012 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 16 ©2012 Integrated Device Technology, Inc. Package Outline and Package Dimensions
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270CCD REVISION A MAY 15, 2012 17 ©2012 Integrated Device Technology, Inc. Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequen- cies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. The table below specifies the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2.5V, a LVPECL output, a ±50ppm crystal frequency accuracy, contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and to the VCXO pull range of minimum ±100ppm. Other default frequencies and order codes are available from IDT on requ est. For more information on available default frequencies, see the FemtoClock N Ceramic-Package XO and VCXO Ordering Product Information document. Shipping Package 8: Tape & Reel (no letter): Tray Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Die Revision C Option Code (Supply Voltage and Frequency-Stability) A: VCC = 3.3V±5%, ±100ppm B: VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm F: VCC = 2.5V±5%, ±50ppm K: VCC = 3.3V±5%, ±20ppm L: VCC = 2.5V±5%, ±20ppm Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. Last digit = L: configuration pre-programmed and not changeable dddd f XTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO 1000 to 1999 100.000 Integer XO 2000 to 2999 Fractional XO FemtoClock NG I/O Identifier 0: LVCMOS 3: LVPECL 4: LVDS Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin
001 XO 10 OE@2
003 XO 10 OE@1
V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 —
085 XO 6 OE@1
270 XO 6 OE@1
271 XO 6 OE@2
272 XO 6 nOE@2
273 XO 6 nOE@1
8N X X XXX X X - dddd XX X X Part/Order Number
IDT8N3S270CCD REVISION A MAY 15, 2012 18 ©2012 Integrated Device Technology, Inc. Table 8. Device Marking
IDT8N3S270 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change without notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of IDT’s products for any particular purpose, an im plied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.
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