IDT8N3S270EC-1103 RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Fourth Generation FemtoClock® NG technology
  • Factory-programmable clock output frequency of 240MHz
  • One 3.3V LVPECL clock output
  • Output enable control (positive polarity), LVCMOS/LVTTL compatible
  • RMS phase jitter @ 240MHz (12kHz - 20MHz): 0.23ps (typical)
  • RMS phase jitter @ 240MHz (1kHz - 40MHz): 0.26ps (typical)
  • 3.3V supply
  • -40°C to 85°C ambient operating temperature
  • Available in a lead-free (RoHS 6) 6-pin ceramic package OE DNU VEE VCC nQ Q IDT8N3S270EC-1103 6-lead ceramic 5mm x 7mm x 1.55mm package body Top View Pin AssignmentBlock Diagram

IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 2 ©2012 Integrated Device Technology, Inc. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: OE is an asynchronous control. Table 1. Pin Descriptions 1 OE Input Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 2D N U Do not use (factory use only). 3V EE Power Negative power supply. 4, 5 Q, nQ Output Differential clock output. LVPECL interface levels. 6 VCC Power Positive power supply. Table 2. Pin Characteristics Table 3. OE Configuration 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled.

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 3 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 49.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 148 mA Table 4B. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CC – 1.3 V CC – 0.8 V VOL Output Low Voltage; NOTE 1 V CC – 2.0 V CC – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Table 4C. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage V CC = 3.3V 2 V CC + 0.3 V VIL Input Low Voltage V CC = VIN = 3.465V -0.3 0.8 V IIH Input High Current OE V CC = VIN = 3.465V 5 µA IIL Input Low Current OE V CC = 3.465V, VIN = 0V -150 µA

IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 4 ©2012 Integrated Device Technology, Inc. Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Refer to the phase noise plot.

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 5 ©2012 Integrated Device Technology, Inc. Typical Phase Noise at 240MHz Noise Power dBc Offset Frequency (Hz)

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 6 ©2012 Integrated Device Technology, Inc. Typical Phase Noise at 240MHz continued Noise Power dBc Hz Offset Frequency (Hz)

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 7 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Rise/Fall Time Cycle-to-Cycle Jitter RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Period Jitter SCOPE Qx nQx VEE -1.3V ± 0.165 VCC 20% 80% 80% 20% tR tF VSWING nQ Q ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power tPW tPERIOD tPW tPERIOD odc = x 100% nQ Q VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10 -7)% of all measurements Histogram

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 8 ©2012 Integrated Device Technology, Inc. Applications Information Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low imped ance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 1A. 3.3V LVPECL Output Termination Figure 1B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Z o = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 10 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the IDT8N3S270EC-1103. Equations and example calculations are also provided. The total power dissipation for the IDT8N3S270EC-1103 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 6 Lead Ceramic VFQFN, Forced Convection

IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 11 ©2012 Integrated Device Technology, Inc.

  1. Calculations and Equations.

LVPECL output driver circuit and termination are shown in Figure 3. Figure 3. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 12 ©2012 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package

6 Terminal

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 13 ©2012 Integrated Device Technology, Inc.

Ordering Information

Table 8. Ordering Information

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR IDT8N3S270EC-1103 REVISION A APRIL 27, 2012 14 ©2012 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A T6 Absolute Maximum Rating - corrected Package Thermal Impedance. Power Considerations - corrected Thermal Resistance table, updated Junction Temperture calculation. Corrected Air Flow table. 4/27/12

IDT8N3S270EC-1103 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change without notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of IDT’s products for any particular purpose, an im plied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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