8N3S001AG-0000CDI8 | DigiCamel IC Datasheet

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IDT8N3Q001 IDT | Alldatasheet

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Technical content

Features

Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order codes), re-programmable by I2C
I2C programming interface for the output clock frequency and internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVPECL clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.244ps (typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.265ps (typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package IDT8N3Q001 10-lead Ceramic 5mm x 7mm x 1.55mm package body Top View

8 VCC

10 SCLK

9 SDATA

Pin AssignmentBlock Diagram Q  nQOSC fXTAL ÷MINT, MFRAC PFD LPF FemtoClock® NG VCO 1950-2600MHz I2C Control Configuration Register (ROM) (Frequency, APR, Polarity) 25 7 FSEL1 FSEL0 SCLK SDATA OE Pulldown Pulldown Pullup Pullup Pullup

IDT8N3Q001GCD REVISION A MARCH 6, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: OE is an asynchronous control. 3V EE Power Negative power supply. section. LVCMOS/LVTTL interface levels. 6, 7 Q, nQ Output Differential clock outpu t. LVPECL interface levels. 8 VCC Power Power supply pin. 9 SDATA Input/Output Pullup I2C Data Input/Output. Input: LVCMOS/LVTTL compatible interface levels. 10 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL compatible interface levels. 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled.

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 3 ©2012 Integrated Device Technology, Inc. Block Diagram with Programming Registers Q  nQOSC fXTAL PFD LPF FemtoClock® NG VCO 1950-2600MHz ÷ N I2C Control SCLK SDATA FSEL[1:0] OE Pullup Pullup Pulldown Pullup Feedback Divider M (25 Bit) MINT  (7 bits) MFRAC  (18 bits) Programming Registers P0 MINT0 MFRAC0 N0 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P1 MINT1 MFRAC1 N1 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P2 MINT2 MFRAC2 N2 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P3 MINT3 MFRAC3 N3 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits7 bits 18 bits 7 bits Def (default): Power-up default register setting for I2C registers Output Divider N Pn, MINTn, MFRACn and Nn

“n” denominates one of the four possible configurations.

XO and VCXO Ordering Product Information document. Table 4. Frequency Selection

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 5 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  extended periods may affect product reliability. Table 5A. Power Supply DC Characteristics,VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5C. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (SDATA) Outputs, IO (LVPECL) Continuous Current Surge Current 10mA  50mA  100mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 140 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 136 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage FSEL[1:0], OE V CC =3.3V +5% 1.7 V CC +0.3 V FSEL[1:0], OE V CC =2.5V +5% 1.7 V CC +0.3 V VIL Input Low Voltage FSEL[1:0] V CC =3.3V +5% -0.3 0.5 V OE V CC =3.3V +5% -0.3 0.8 V FSEL[1:0] V CC =2.5V +5% -0.3 0.5 V OE V CC =2.5V +5% -0.3 0.8 V IIH Input High Current OE V CC = VIN = 3.465V or 2.625V 10 µA SDATA, SCLK V CC = VIN = 3.465V or 2.625V 5 µA FSEL0, FSEL1 V CC = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current OE V CC = 3.465V or 2.625V, VIN = 0V -500 µA SDATA, SCLK V CC = 3.465V or 2.625V, VIN = 0V -150 µA FSEL0, FSEL1 V CC = 3.465V or 2.625V, VIN = 0V -5 µA

IDT8N3Q001GCD REVISION A MARCH 6, 2012 6 ©2012 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50 to VCC – 2V. Table 6. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

17 MHz fOUT 1300MHz,

500 MHz fOUT 1300MHz,

125 MHz fOUT 500MHz,

17 MHz fOUT 125MHz,

17 MHz fOUT 1300 MHz,

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 7 ©2012 Integrated Device Technology, Inc. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Please refer to the phase noise plots. NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes and configures DSM_ENA = 0 and ADC_EN = 0. NOTE 4: Integration range: 12kHz-20MHz. NOTE 5: Integration range: 1kHz-40MHz. N (100k) Single-side band phase noise,  100kHz from Carrier 156.25MHz -137.3 dBc/Hz N (1M) Single-side band phase noise,  1MHz from Carrier 156.25MHz -139.0 dBc/Hz N (10M) Single-side band phase noise,  10MHz from Carrier 156.25MHz -154.9 dBc/Hz PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise 1kHz - 50kHz -54 dB tR / tF Output Rise/Fall Time 20% to 80% 100 425 ps odc Output Duty Cycle 45 55 % tSTARTUP Oscillator Start-Up Time 20 ms tSET Output frequency settling time after FSEL0 and FSEL1 values are changed 470 µs Symbol Parameter Test Conditions Minimum Typical Maximum Units

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 8 ©2012 Integrated Device Technology, Inc. Typical Phase Noise at 156.25MHz (12kHz - 20MHz) Noise Power dBc Hz Offset Frequency (Hz) NOTE: RMS Phase Noise (Random) for Integer PLL Feedback and fXTAL =100.000MHz.

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 9 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Period Jitter Cycle-to-Cycle Jitter SCOPE Qx nQx VEE VCC -1.3V±0.165V Offset Frequencyf1 f2 Phase Noise Plot R MS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power 20% 80% 80% 20% tR tF VSWING nQ Q SCOPE Qx nQx VEE VCC -0.5V± 0.125V VOH VRE F VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nQ Q ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 10 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Select Pins The FSEL[1:0] pins have internal pulldowns and OE control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. SCLK and SDATA should be left floating if not used. tPW tPERIOD tPW tPERIOD odc = x 100% nQ Q

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 11 ©2012 Integrated Device Technology, Inc. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 1A. 3.3V LVPECL Output Termination Figure 1B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL ) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Inp ut 3.3V 3.3V

IDT8N3Q001GCD REVISION A MARCH 6, 2012 14 ©2012 Integrated Device Technology, Inc. Equations and example calculations are also provided. The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
Power (outputs)MAX = 34.2mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 34.2mW = 519.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination

For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V (VCC_MAX – VOH_MAX ) = 0.8V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V (VCC_MAX – VOL_MAX ) = 1.5V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX ) = [(2V – (VCC_MAX – VOH_MAX ))/RL] * (VCC_MAX – VOH_MAX ) = Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX ) = [(2V – (VCC_MAX – VOL_MAX ))/RL] * (VCC_MAX – VOL_MAX ) = Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW VOUT VCC VCC - 2V RL 50Ω

IDT8N3Q001GCD REVISION A MARCH 6, 2012 16 ©2012 Integrated Device Technology, Inc. Table 8. JA vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package NOTE: For proper thermal dissipation, the PCB layout for the pin pad should at minimum equal the package pin dimensions.

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 18 ©2012 Integrated Device Technology, Inc. Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequen- cies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. Shown below are the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy, contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 10-lead Ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and to the VCXO pull range of minimum 100 ppm. Other default frequencies and order codes are available from IDT on request. For more information on available default frequencies, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Shipping Package 8: Tape & Reel (no letter): Tray Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) Package Code CD : Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Die Revision G Option Code (Supply Voltage and Frequency-Stability) A : VCC = 3.3V±5%, ±100ppm B : VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm  F: VCC = 2.5V±5%, ±50ppm  K : VCC = 3.3V±5%, ±20ppm  L: VCC = 2.5V±5%, ±20ppm Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. Last digit = L: configuration pre-programmed and not changable dddd f XTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO 1000 to 1999 100.000 Integer XO 2000 to 2999 Fractional XO FemtoClock NG I/O Identifier 0: LVCMOS  3: LVPECL 4: LVDS Number of Default Frequencies S: 1: Single D : 2: Dual Q : 4: Quad Part Number Function #pins OE fct. at pin

001 XO 10 OE@2

003 XO 10 OE@1

V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 —

085 XO 6 OE@1

270 XO 6 OE@1

271 XO 6 OE@2

272 XO 6 nOE@2

273 XO 6 nOE@1

8N X X XXX X X - dddd XX X X Part Order/Number

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO IDT8N3Q001GCD REVISION A MARCH 6, 2012 20 ©2012 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A 9 19 Table 9 Device Marking, corrected marking. 3/6/12

IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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Product Information

8N3S001AG-0000CDI8 specifications and overview.

Summary

Quad-Frequency Programmable XO

Description

Quad-Frequency Programmable XO

Source title 8N3S001AG-0000CDI8 Datasheet(PDF) - Integrated Device Technology

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