8N3PG10MBKI-161LF

8N3PG10MBKI-161 IDT | Alldatasheet

Document overview

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Technical content

Features

• Fourth Generation FemtoClock® Next Generation (NG) technology
• Footprint compatible with 5mm x 7mm differential oscillators
• One differential LVPECL output pair
• CLK, nCLK input pair can accept the following levels: HCSL, LVDS, LVPECL, LVHSTL
• Output frequency: 161.1328125MHz
• RMS phase jitter, 12kHz – 20MHz = 0.567ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging Block Diagram Pin Assignment FSEL[1:0] Input (MHz) Output Frequency (MHz) 00 156.25 161.1328125 01 156.25 161.1328125 10 156.25 161.1328125 11 156.25 161.1328125 (default) Q Pullup PFD FemtoClock ® NG VCO Pullup Control Logic CLK nCLK FSEL0 FSEL1 OE Pullup Pulldown PU/PD 1 OE nc VEE FSEL0 FSEL1nCLK CLK 4 5 10 9 nQ VCC Q 8N3PG10MBKI-161 10-Lead VFQFN 5mm x 7mm x 1mm package body K Package Top View 8N3PG10MBKI-161 Data Sheet FemtoClock® NG Differential-to-3.3V, 2.5V LVPECL Synthesizer

Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. P, M, N Divider Function Table 1O E P ullup Output enable. External pullup required for normal operation. LVCMOS/LVTTL interface levels. 2 Reserved Reserve Reserved pin. 3V EE Power Negative supply pin. 5 CLK Input Pulldown Non-inverting differential clock input. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V CC Power Power supply pin. 9 FSEL0 Input Pullup Feedback control input. Sets the output divider value to one of four values. Frequency Select Table on page 1. 10 FSEL1 Input Pullup Feedback control input. Sets the output divider value to one of four values. LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.

3©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 39.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 151 189 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 146 182 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

4©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Table 4D. Differential DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as the crossing point. Table 4E. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Outputs termination with 50 to VCC – 2V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK, nCLK V CC = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK VIN = 0V, VCC = 3.465V or 2.625V -5 µA nCLK VIN = 0V, VCC = 3.465V or 2.625V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE VCC – 0.85 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC – 1.4 V CC – 0.8 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 V CC – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

5©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Table 5A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Refer to the Phase Noise plots. NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks. Table 5B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Refer to the Phase Noise plots. NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 161.1328125 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 18 30 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2, 3 fOUT = 161.1328125MHz, Integration Range: 12kHz – 20MHz 0.567 ps tR / tF Output Rise/Fall Time 20% to 80% 150 450 ps odc Output Duty Cycle 49 51 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 161.1328125 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 18 30 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2, 3 fOUT = 161.1328125MHz, Integration Range: 12kHz – 20MHz 0.567 ps tR / tF Output Rise/Fall Time 20% to 80% 100 500 ps odc Output Duty Cycle 49 51 %

6©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Typical Phase Noise at 161.1328125MHz Noise Power (dBc / Hz) Offset Frequency (Hz)

7©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Parameter Measurement Information 3.3V LVPECL Output Load Test Circuit Differential Input Level Cycle-to-Cycle Jitter 2.5V LVPECL Output Load Test Circuit Output Duty Cycle/Pulse Width/Period RMS Phase Jitter SCOPE Qx nQx VEE VCC -1.3V± 0.165V VCC VEE nCLK CLK tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q SCOPE Qx nQx VEE VCC -0.5V± 0.125V nQ Q

8©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Parameter Measurement Information, continued Output Rise/Fall Time nQ Q

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale

13©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible signals. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50  transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

15©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Schematic Example Figure 7 shows an example IDT8N3PG10MBKI-161 application schematic in which the device is operated at V CC = +3.3V. The schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For example OE, FSEL0 and FSEL1 can be configured from an FPGA instead of pull up and pull down resistors as shown. The input is driven by a DC coupled LVDS driver, though HCSL and LVPECL are also compatible with the IDT CLK, nCLK differential inputs. There are two LVPECL termination options shown; the simple three resistor termination of R5, R6 and R7 and an AC termination, used when coupling the IDT8N3PG10MBKI-161 LVPECL output stage to a different logic family receiver. Note that the pull down resistors R8 and R9 that bias the LVPECL output stage are to be placed on the IDT8N3PG10MBKI-161 side of the PCB directly adjacent to pins 6 and 7 for best signal integrity. Most often each output of a 3.3V LVPECL driver will be DC terminated with a 130  pull up and an 82  pull down resistor at the 3.3V LVPECL receiver. This is also a valid option with the IDT8N3PG10MBKI-161, though the three resistor termination is simpler in regard to component count and layout as well as lower in power dissipation. NOTE: This device package has an ePAD that is connected to ground internally. The ePAD should be connected to GND on the PCB through vias in order to improve heat dissipation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the V CC pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor on the V CC pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.

Figure 7. 8N3PG10MBKI-161 Schematic Layout Example and on the component side of the circuit board. mode center of t he Receiver.

This section provides information on power dissipation and junction temperature for the 8N3PG10MBKI-161. Equations and example calculations are also provided. The total power dissipation for the 8N3PG10MBKI-161 is the sum of the core power plus the power dissipation due to loading. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation due to loading. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 39.2°C/W per Table 6 below. Table 6. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection

Table 7. JA vs. Air Flow Table for a 10 Lead VFQFN Table 8. Package Dimensions for 10-Lead VFQFN

20©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet Package Outline Package Outline - K Suffix for 10-Lead VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8. ccc C PLANE SEATING 0.08 C A B C bbb C A B INDEX AREA (D/2 xE/2) (D/2 xE/2) INDEX AREA aaa C 2x TOP VIEW9 aaa C 2x SIDE VIEW BOTTOM VIEW PIN#1 ID D E NX b1 NX b2 bbb C A B A NX L1 NX L2 0.1mm→ → 0.1mm N-1N CHAMFER N-1 N RADIUS Bottom View w/Type C IDBottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1)

21©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet

Ordering Information

Table 9. Ordering Information

22©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-161 Data Sheet

Revision History

Revision Date Description of Change January 28, 2016 ▪ Removed ICS in the part number where needed. ▪ Updated header and footer.

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