8N3PG10MBKI-062LFT

8N3PG10MBKI-062 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Integrated Device Technology
• PDF pages: 22

Technical content

Features

• Fourth Generation FemtoClock® Next Generation (NG) technology
• Footprint compatible with 5mm x 7mm differential oscillators
• One differential LVPECL output pair
• CLK, nCLK input pair can accept the following levels: HCSL, LVDS, LVPECL and LVHSTL
• Output frequencies: 150MHz, 125MHz, 155.52MHz and 311.04MHz
• RMS phase jitter, 12kHz – 20MHz: 0.295ps (typical) @ 3.3V
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging Pin Assignment 8N3PG10MBKI-062 10-Lead VFQFN 5mm x 7mm x 1mm package body K Package Top View Block Diagram FSEL[1:0] Input (MHz) Output Frequency (MHz) 00 200 150 01 100 125 10 100 155.52 11 100 311.04 (default) OE Reserved VEE FSEL0 FSEL1nCLK CLK 10 9 nQ VCC Q Q nQ Phase Detector Pre-divider FemtoClock VCO ÷N Pullup PullupFSEL[1:0] OE CLK nCLK Pulldown Pullup/Pulldown 8N3PG10MBKI-062 Data Sheet Programmable FemtoClock® NG Differential-to-3.3V, 2.5V LVPECL Synthesizer

Table 2. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 3. Pin Characteristics Table 4. P, M, N Divider Function Table 1 OE Pullup Output enable. External pullup required for normal operation. LVCMOS/LVTTL interface levels. 2 Reserved Reserve Reserved pin. EE Power Negative supply pin. 5 CLK Input Pulldown Non-inverting differential clock input.

6 Q Output

Differential output pair. LVPECL interface levels. 8V CC Power Power supply pin. 9 FSEL0 Input Pullup Feedback control input. Sets the output divider value to one of four values. LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1. 10 FSEL1 Input Pullup Feedback control input. Sets the output divider value to one of four values. LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.

3©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Junction Temperature, TJ 125C Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 189 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 182 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

4©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Table 5D. Differential DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. VIH should not be higher than VCC. NOTE 2: Common mode input voltage is defined as the crossing point. Table 5E. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Outputs termination with 50 to VCC – 2V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK, nCLK VCC = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK VIN = 0V, VCC = 3.465V or 2.625V -5 µA nCLK VIN = 0V, VCC = 3.465V or 2.625V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE VCC – 0.85 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CC – 1.4 V CC – 0.9 V VOL Output Low Voltage; NOTE 1 V CC – 2.0 V CC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

5©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Table 6A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Refer to the Phase Noise plots. NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks. Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Refer to the Phase Noise plots. NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency 125 311.04 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 18 30 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2, 3 fOUT = 150MHz, Integration Range: 12kHz – 20MHz 0.295 ps tR / tF Output Rise/Fall Time 20% to 80% 100 500 ps odc Output Duty Cycle 49 51 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 125 311.04 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 18 30 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2, 3 fOUT = 150MHz, Integration Range: 12kHz – 20MHz 0.3 ps tR / tF Output Rise/Fall Time 20% to 80% 100 500 ps odc Output Duty Cycle 49 51 %

6©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Typical Phase Noise at 150MHz, (3.3V) Noise Power (dBc/Hz) Offset Frequency (Hz)

7©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Typical Phase Noise at 150MHz, (2.5V) Noise Power (dBc/Hz) Offset Frequency (Hz)

8©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter Differential Input Level Cycle-to-Cycle Jitter Output Rise/Fall Time 2.5V LVPECL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period Differential Input Level SCOPE Qx nQx VEE VCC -1.3V± 0.165V tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q nQ Q SCOPE Qx nQx VEE VCC -0.5V± 0.125V nQ Q VCC VEE nCLK CLK

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale

This section provides information on power dissipation and junction temperature for the 8N3PG10MBKI-062. Equations and example calculations are also provided. The total power dissipation for the 8N3PG10MBKI-062 is the sum of the core power plus the power dissipation due to loading. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation due to loading. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below. Table 7. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection

1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. The LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination To calculate power dissipation due to loading, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 8. JA vs. Air Flow Table for a 10 Lead VFQFN Table 9. Package Dimensions for 10-Lead VFQFN

18©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet Package Outline Package Outline - K Suffix for 10-Lead VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in T able 9. ccc C PLANE SEATING 0.08 C A B C bbb C A B INDEX AREA (D/2 xE/2) (D/2 xE/2) INDEX AREA aaa C 2x TOP VIEW9 aaa C 2x SIDE VIEW BOTTOM VIEW PIN#1 ID D E NX b1 NX b2 bbb C A B A NX L1 NX L2 0.1mm→ → 0.1mm N-1N CHAMFER N-1 N RADIUS Bottom View w/Type C IDBottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1)

19©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet

Ordering Information

Table 10. Ordering Information

20©2016 Integrated Device Technology, Inc Revision A January 28, 2016 8N3PG10MBKI-062 Data Sheet

Revision History

Revision Date Description of Change January 28, 2016 ▪ Removed ICS from the part number where needed. ▪ Updated header and footer.

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