8N3PF10VA-159NRGI

IDT8N3PF10VA-159I IDT | Alldatasheet

Document overview

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Technical content

Features

• Fourth Generation FemtoClock® NG technology • Footprint compatible with 5mm x 7mm differential oscillators • Generates 100MHz or 156.25MHz from a 25MHz crystal, or 212.5MHz or 106.25MHz from a 26.5625MHz mode crystal • One differential LVPECL output pair • Crystal oscillator interface which can also be overdriven using a single-ended reference clock • RMS phase jitter @ 156.25MHz, 10kHz – 1MHz: 0.201ps (typical) • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package FSEL0 FSEL1 Pullup Pullup Pullup Q nQ OSC PFD LPF FemtoClock® NG VCO 2 - 2.5GHz XTAL_IN XTAL_OUT FSEL0 FSEL1 OE Control Logic Pin Assignment IDT8N3PF10VA-159I 10-Lead VFQFN 5mm x 7mm x 1mm package body ePAD size: 1.70mm x 3.70mm Top View Block Diagram

IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions Pullup refers to internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Divider Function Table 1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels. 2 RESERVED Reserved Reserved pin. Do not connect. 3V EE Power Negative supply pin. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V CC Power Power supply pin. Table 3. LVCMOS/LVTTL interface levels. Table 3. LVCMOS/LVTTL interface levels

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 3 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 36.8°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 118 140 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 115 135 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current OE, FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE, FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA

IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 4 ©2012 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Table 5. Crystal Characteristics Table 6. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. NOTE: Characterized using a 25MHz, 12pF resonant crystal. NOTE 1: Please refer to the Phase Noise plots. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

25 MHz

26.5625 MHz

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 5 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V LVPECL Output Load Test Circuit Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SCOPE Q nQ LVPECL VEE VCC -1.3V±0.165V Offset Frequencyf1 f2 Phase Noise Plot Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter = Noise Power 2 * * ƒ 1 * 20% 80% 80% 20% tR tF VSWING nQ Q SCOPE Q nQ LVPECL VEE VCC -0.5V±0.125V ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q tPW tPERIOD tPW tPERIOD odc = x 100% nQ Q

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 6 ©2012 Integrated Device Technology, Inc. Phase Jitter Plot at 156.25MHz (3.3V) Noise PowerdBc / Hz Offset Frequency (Hz)

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 8 ©2012 Integrated Device Technology, Inc. Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 11 ©2012 Integrated Device Technology, Inc. Schematic Layout Figure 5 (next page) shows an example of IDT8N3PF10VA-159I application schematic in which the device is operated at VCC = 3.3V. The schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For example OE, FSET0 and FSEL1 can be configured from an FPGA instead of pull up and pull down resistors as shown. There are two LVPECL termination options shown; the simple three resistor termination of R5, R6 and R7 and an AC termination, used when coupling the IDT8N3PF10VA-159I LVPECL output stage to a different logic family receiver. Note that the pull down resistors R8 and R9 that bias the LVPECL output stage are to be placed on the IDT8N3PF10VA-159I side of the PCB directly adjacent to pins 6 and 7 for best signal integrity. Most often each output of a 3.3V LVPECL driver will be DC terminated with a 130Ω pull up and an 82 ohm pull down resistor at the 3.3V LVPECL receiver. This is also a valid option with the IDT8N3PF10VA-159I, though the three resistor termination is simpler in regard to component count and layout as well as lower in power dissipation. NOTE: This device package has an ePAD that is connected to ground internally. Though not necessary, the ePAD should be connected to GND on the PCB through vias in order to improve heat dissipation. If not connected, the area below the ePAD must be treated as a keep-out region. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the VCC pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor on the VCC pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.

IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 12 ©2012 Integrated Device Technology, Inc. Figure 5. IDT8N3PF10VA-159I Application Schematic VCC pin and on the component side. mode center of the Receiver.

IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 13 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the IDT8N3PF10VA-159I. Equations and example calculations are also provided. The total power dissipation for the IDT8N3PF10VA-159I is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 36.8°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 10 Lead VFQFN, Forced Convection

IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 15 ©2012 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 10 Lead VFQFN

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 16 ©2012 Integrated Device Technology, Inc.

10 Lead VFQFN, NR Suffix Package Outline

5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch Page 1 O f 4 PAC KAG E O UTLINE MLP Q UAD 0.08 C A B C bbb C A B INDEX AREA (D/ 2 xE/ 2) (D/ 2 xE/ 2) INDEX AREA aaa C 2x TO P VIEW9 aaa C 2x SIDE VIEW BO TTO M VIEW PIN# 1 ID FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8 D E NX b1 NX b2 bbb C A B A NX L1 NX L2

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 17 ©2012 Integrated Device Technology, Inc.

10 Lead VFQFN, NR Suffix Package Outline, continued

PAG E: 2 of 4 aaa 0.1 5 bbb 0.1 0 ccc 0.1 0 TO LERANC E O F FO RM AND PO SITIO N C O MMO N DIMENSIO N 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch PAC KAG E O UTLINE MLP Q UAD FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8 Size Body 5.00X7.00 Pit ch (e1 & e2) 1 .00/ 2.54 Lead C ount 1 0 Lead Summar y Table Var iat ion VNJR- 1 Ver y Ver y Thin R0.30 Pin # 1 ID NO MMIN MAX 1 .00 0.05 1 , 2NO TES A 1 , 2 0.00 0.80 1 , 2 0.02 0.90 C O MMO N DIMENSIO N SYMBO L V : Ver y t hin

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 18 ©2012 Integrated Device Technology, Inc. PAG E: 3 of 4 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch PAC KAG E O UTLINE MLP Q UAD NO TE: 1 . Dimensioning and t oler ancing conf or m t o ASME Y1 4.5M- 1 994. 2. All dimensions ar e in millimet er s, angles ar e in degr ees(°). 3. N is t he t ot al number of t er minals. 4. The locat ion of t he t er minal # 1 ident if ier and ter minal number ing convent ion conf or ms t o JEDEC publicat ion 95 SPP- 002. 5. ND and NE r ef er t o t he number of t er minals on each D and E side r espect ively. 6. NJR r ef er s t o NO N JEDEC REG ISTERED 7. Dimension b applies t o met allized t er minal and is measur ed bet ween 0.1 0mm and 0.30mm f r om t he t er minal t ip. If t he t er minal has t he opt ional r adius on t he ot her end of t he t er minal, t he dimension b should not be measur ed in t hat r adius ar ea. 8. C oplanar it y applies t o t he t er minals and all ot her bot t om sur f ace met allizat ion. 9. Dr awing shown ar e f or illust r at ion only. FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 19 ©2012 Integrated Device Technology, Inc. 5.00x7.00 MLPQ 1 0LD 1 .00/ 2.54 Pit ch PAC KAG E O UTLINE MLP Q UAD PAG E: 4 of 4 PAD DESIG N NE NO TES N ND 1 0 Symbol Var iat ion 0.65 0.55 0.45 3.80 3.70 3.55 1 .80 1 .70 1 .55 MIN NO ML1 MAX NO M MIN MAX E BSC MIN NO M MAX Not e MIN NO M MAX 0.45 0.40 0.35 5.00 7.00 D BSC FO R REVISIO N UPDATE PLEASE REFER TO HISTO RY O F C HANG ES. ENG INEERING MANAG ER DATE TO O LING MANAG ER TEC H. SALES MANAG ER O RIG INATO R DWG . NO : PKG ML00305 DRAFT ZAHRUL ARAVEN KANDA 2007- APR- 1 8 VNJR- 1 1 .40NO M MAX 1 .45 MIN 1 .35 1 .1 0NO ML2 MAX 1 .20 MIN 1 .00

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012 20 ©2012 Integrated Device Technology, Inc.

Ordering Information

Table 9. Ordering Information

IDT8N3PF10VA-159I Data Sheet Universal Frequency Synthesizer DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’ s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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