IDT8N4QV01_14 IDT | Alldatasheet
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Fourth generation FemtoClock® NG technology Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz Four power-up default frequencies (see part number order codes), re-programmable by I2C I2C programming interface for the output clock frequency , APR and internal PLL control registers Frequency programming resolution is 435.9Hz ÷ N Absolute pull-range (APR) programmable from ±4.5ppm to ±754.5ppm One 2.5V or 3.3V L VDS differential clock output T wo control inputs for the power-up default frequency L VCMOS/L VTTL compatible control inputs RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.494ps (typical) RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.594ps (typical) 2.5V or 3.3V supply voltage modes -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) packaging IDT8N4QV01 REV G DA T A SHEET 10-lead ceramic 5mm x 7mm x 1.55mm package body T op View 8V DD 7n Q FSEL0 4 FSEL1 5
10 SCLK
Pin AssignmentBlock Diagram Q nQ OSC
114.285 MHz
÷MINT , MFRAC PFD LPF FemtoClock® NG VCO 1950-2600MHz I2C Control Configuration Register (ROM) (Frequency , APR, Polarity) 25 7 VC FSEL1 FSEL0 SCLK SDA T A OE Pulldown Pulldown Pullup Pullup Pullup A/D
IDT8N4QV01GCD REVISION A MARCH 11, 2014 2 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO T able 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See T able 2,Pin Characteristics, for typical values. T able 2. Pin Characteristics Number Name Type Description 1 VC Input VCXO Control Voltage. The control voltage versus frequency characteristics are set by the ADC_GAIN[5:0] register bits. 2 OE Input Pullup Output enable pin. See Table 3B for function. LVCMOS/LVTTL interface levels. 3 GND Power Power supply ground. 4, 5 FSEL0, FSEL1 Input Pulldown Default frequency select pins. See Table 3A for function and Table 8 for the default frequency order codes. LVCMOS/LVTTL interface levels. 6, 7 Q, nQ Output Differential clock output. LVDS interface levels. 8 VDD Power Power supply pin. 9 SDA T A Input Pullup I2C Data Input. LVCMOS/LVTTL interface levels. 10 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels. Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance FSEL[1:0], SDA T A, SCLK 5.5 pF VC 10 pF RPULLUP Input Pullup Resistor 50 k RPULLDOWN Input Pulldown Resistor 50 k
IDT8N4QV01GCD REVISION A MARCH 11, 2014 3 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Function Tables T able 3A. Default Frequency Selection NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See programming section for details. T able 3B. OE Configuration NOTE: OE is an asynchronous control. Input OperationFSEL1 FSEL0 0 (default) 0 (default) Default frequency 0 0 1 Default frequency 1 1 0 Default frequency 2 1 1 Default frequency 3 Input Output EnableOE 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled.
IDT8N4QV01GCD REVISION A MARCH 11, 2014 4 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Block Diagram with Programming Registers Q nQ OSC FemtoClock® NG VCO 1950-2600MHz ÷ N I2C Control VC SCLK SDA T A FSEL[1:0] OE Pullup Pullup Pulldown, Pulldown Pullup Feedback Divider M (25 Bit) MINT (7 bits) MFRAC (18 bits) Programming Registers ADC_GAIN ADC_POL I2C: 6 bits 1 bit Def: 6 bits 1 bit P0 MINT0 MFRAC0 N0 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P1 MINT1 MFRAC1 N1 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P2 MINT2 MFRAC2 N2 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P3 MINT3 MFRAC3 N3 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits Def: Power-up default register setting for I2C registers Output Divider N A/D ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn
IDT8N4QV01GCD REVISION A MARCH 11, 2014 5 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Principles of Operation The block diagram consists of the internal 3rd overtone crystal and oscillator which provide the reference clock fXT ALof either 114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO along with the Pre-divider ( P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXT ALreference and must be configured correctly for proper operation. The feedback divider is fractional supporting a huge number of output frequencies. The configuration of the feedback divider to integer-only values results in an improved output phase noise characteristics at the expense of the range of output frequencies. In addition, internal registers are used to hold up to four different factory pre-set P, M, and N configuration settings. These default pre-sets are stored in the I2C registers at power-up. Each configuration is selected via the FSEL[1:0] pins and can be read back using the SCLK and SDA T A pins. The user may choose to operate the device at an output frequency different than that set by the factory . After power-up, the user may write new P , N and M settings into one or more of the four configuration registers and then use the FSEL[1:0] pins to select the newly programmed configuration. Note that the I2C registers are volatile and a power supply cycle will reload the pre-set factory default conditions. If the user does choose to write a different P, M, and N configuration, it is recommended to write to a configuration which is not currently selected by FSEL[1:0] and then change to that configuration after the I2C transaction has completed. Changing the FSEL[1:0] controls results in an immediate change of the output frequency to the selected register values. The P, M, and N frequency configurations support an output frequency range 15.476MHz to 866.67MHz and 975MHz to 1,300MHz. The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability . The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determined by the 2-bit pre-divider ( P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: f OUT f XTAL The four configuration registers for theP , M (MINT & MFRAC)and N dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to 3. “n” denominates one of the four possible configurations. As identified previously , the configurations of P, M (MINT & MFRAC) and N divider settings are stored the I2C register, and the configuration loaded at power-up is determined by the FSEL[1:0] pins. Input Selects RegisterFSEL1 FSEL0 0 (def.) 0 (def.) Frequency 0 P0, MINT0, MFRAC0, N0 0 1 Frequency 1 P1, MINT1, MFRAC1, N1 1 0 Frequency 2 P2, MINT2, MFRAC2, N2 1 1 Frequency 3 P3, MINT3, MFRAC3, N3 Frequency Configuration An order code is assigned to each frequency configuration programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information Section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. For more information and guidelines on programming of the device for custom frequency configurations, the register description, the pull-range programming and the serial interface description, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. T able 4. Frequency Selection
IDT8N4QV01GCD REVISION A MARCH 11, 2014 6 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only . Functional operation of product at these conditions or any conditions beyond those listed in theDC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability . Supply Voltage, VDD 3.63V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (SDATA) Outputs, IO (LVDS) Continuous Current Surge Current 10mA 10mA 15mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65Ct o1 5 0C T able 5A. Power Supply DC Characteristics,VDD = 3.3V ±5%, TA = -40°C to 85°C T able 5B. Power Supply DC Characteristics,VDD = 2.5V ±5%, TA = -40°C to 85°C Item Rating Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 160 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 155 mA
IDT8N4QV01GCD REVISION A MARCH 11, 2014 7 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO T able 5C. L VCMOS/L VTTL DC Characteristic,VDD = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C T able 5D. L VDS DC Characteristics,VDD = 3.3V ±5% or 2.5V ±5%, T A = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage SEL [1:0], OE V CC =3.3V +5% 1.7 V CC +0.3 V SEL [1:0], OE V CC =2.5V +5% 1.7 V CC +0.3 V VIL Input Low Voltage OE V CC =3.3V +5% -0.3 0.8 V OE V CC =2.5V +5% -0.3 0.8 V IIH Input High Current OE 10 µA SDATA, SCLK VDD =V IN = 3.465V or 2.625V 5 µA FSEL0, FSEL1 VDD =V IN = 3.465V or 2.625V 150 µA IIL Input Low Current OE -500 µA SDATA, SCLK VDD = 3.465V or 2.625V , VIN =0 V -150 µA FSEL0, FSEL1 VDD = 3.465V or 2.625V , VIN =0 V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 247 350 454 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.0 1.20 1.375 V VOS VOS Magnitude Change 50 mV
IDT8N4QV01GCD REVISION A MARCH 11, 2014 8 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO T able 6A. VCXO Control V oltage Input (VC) Characterisitics, VDD = 3.3V ±5% or 2.5V ±5%, T A = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: VC =0 Vt oV DD. NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V . NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application. NOTE 4: BSL = Best Straight Line Fit: V ariation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VDD. NOTE 5: Incremental slope is defined as the linearity in percent of the raw data (not relative to BSL) from 10% to 90% VDD. Symbol Parameter Test Conditions Minimum Typical Maximum Units KV Oscillator Gain, NOTE 1, 2, 3 VDD = 3.3V ADC_GAIN[5:0] = 000001 7.57 ppm/V ADC_GAIN[5:0] = 000010 15.15 ppm/V ADC_GAIN[5:0] = XXXXXX 2·12.5 ÷ VDD ADC_GAIN ppm/V ADC_GAIN[5:0] = 111110 469.69 ppm/V ADC_GAIN[5:0] = 111111 477.27 ppm/V Oscillator Gain, NOTE 1, 2, 3 VDD = 2.5V ADC_GAIN[5:0] = 000001 10 ppm/V ADC_GAIN[5:0] = 000010 20 ppm/V ADC_GAIN[5:0] = XXXXXX 2·12.5 ÷ VDD ADC_GAIN ppm/V ADC_GAIN[5:0] = 111110 620 ppm/V ADC_GAIN[5:0] = 111111 630 ppm/V LVC Control Voltage Linearity BSL V ariation; NOTE 4 -5 ±1 +5 % Incremental; NOTE 5 -10 ±5 +10 % BW Modulation Bandwidth 100 kHz ZVC VC Input Impedance 500 k VCNOM Nominal Control Voltage VDD÷2 V VC Control Voltage Tuning Range; NOTE 4 0V DD V
IDT8N4QV01GCD REVISION A MARCH 11, 2014 9 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO T able 6B. AC Characteristics,VDD = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All AC parameters are characterized with P=1 and pull range ±250 ppm. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Please refer to the phase noise plots. NOTES continued on next page. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency Q, nQ Output Divider, N = 3 to126 15.476 866.67 MHz Output Divider, N = 2 975 1,300 MHz fVCO VCO Frequency 1980 2600 MHz fI Initial Accuracy Measured at 25°C ±10 ppm fS Temperature Stability Option code=Ao rB ±100 ppm Option code=Eo rF ± 5 0 p p m Option code=Ko rL ± 2 0 p p m fA Aging Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm fT Total Stability Option code A or B (10 year life) ±113 ppm Option code E or F (10 year life) ±63 ppm Option code K or L (10 year life) ±33 ppm tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 20 ps tjit(per) Period Jitter; NOTE 1 2.85 4 ps tjit(Ø) RMS Phase Jitter (Random) Fractional PLL feedback and fXTAL=114.285MHz (0xxx order codes) 17MHz fOUT 1300MHz, NOTE 2,3,4 0.475 0.990 ps fOUT 156.25MHz, NOTE 2, 3, 4 0.494 0.757 ps fOUT 156.25MHz, NOTE 2, 3, 5 0.594 ps N(100) Single-side band phase noise, 100 Hz from Carrier 156.25MHz -73.8 dBc/Hz N(1k) Single-side band phase noise, 1kHz from Carrier 156.25MHz -99.8 dBc/Hz N(10k) Single-side band phase noise, 10kHz from Carrier 156.25MHz -126.1 dBc/Hz N(100k) Single-side band phase noise, 100kHz from Carrier 156.25MHz -129.3 dBc/Hz N(1M) Single-side band phase noise, 1MHz from Carrier 156.25MHz -140.3 dBc/Hz N(10M) Single-side band phase noise, 10MHz from Carrier 156.25MHz -144.3 dBc/Hz PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise 1kHz - 50MHz -54 db tR /t F Output Rise/Fall Time 20% to 80% 100 425 ps odc Output Duty Cycle 45 55 % tOSC Oscillator Start-Up Time 20 ms tSET Output Frequency Settling Time after FSEL0 and FSEL1 Values are Changed 470 µs
IDT8N4QV01GCD REVISION A MARCH 11, 2014 10 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on finding the optimum configuration for phase noise. NOTE 4: Integration range: 12kHz-20MHz. NOTE 5: Integration range: 1kHz-40MHz. Typical Phase Noise at 156.25MHz (12kHz - 20MHz) Noise Power dBc Hz Offset Frequency (Hz)
IDT8N4QV01GCD REVISION A MARCH 11, 2014 11 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Parameter Measurement Information 3.3V L VDS Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period 2.5V L VDS Output Load AC Test Circuit Period Jitter Cycle-to-Cycle Jitter SCOPE Q nQ 3.3V±5% POWER SUPPL + Float GND VDD t PW t PERIOD t PW t PERIOD odc = x 100% nQ Q SCOPE Q nQ 2.5V±5% POWER SUPPL + Float GND VDD VOH VREF VOL Mean Period (First edge after trigger) Reference Point (T rigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram nQ Q ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n tcycle n+1
1000 Cycles
IDT8N4QV01GCD REVISION A MARCH 11, 2014 12 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Parameter Measurement Information (continued) Output Rise/Fall Time Differential Output V oltage Setup Start-Up Offset V oltage Setup 20% 80% 80% 20% t R t F VOD nQ Q t startup Not to Scale VDDMIN VDD Output Correct Frequency
IDT8N4QV01GCD REVISION A MARCH 11, 2014 14 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Power Considerations This section provides information on power dissipation and junction temperature for the IDT8N4QV01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N4QV01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V , which gives worst case results. Power (core) MAX =V DD_MAX *I DD_MAX = 3.465V * 160mA = 554.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction T emperature JA = Junction-to-Ambient Thermal Resistance Pd_total = T otal Device Power Dissipation (example calculation is in section 1 above) TA = Ambient T emperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistanceJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per T able 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). T able 7. Thermal ResistanceJA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection JA by Velocity Meters per Second 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41°C/W
IDT8N4QV01GCD REVISION A MARCH 11, 2014 15 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Reliability Information Ta b l e 8 .JA vs. Air Flow T able for a 10-lead Ceramic 5mm x 7mm Package T ransistor Count The transistor count for IDT8N4QV01 is: 47,372 JA vs. Air Flow Meters per Second 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41°C/W
IDT8N4QV01GCD REVISION A MARCH 11, 2014 16 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Package Outline and Package Dimensions
IDT8N4QV01GCD REVISION A MARCH 11, 2014 17 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequen- cies, internal crystal frequency , power supply voltage, ambient temperature range and the frequency accuracy . The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. The table below specifies the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2.5V , a L VPECL output, a50 ppm crystal frequency accuracy , contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 10-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100, 122.88, 125 and 156.25MHz and to the VCXO pull range of min. 100 ppm. Other default frequencies and order codes are available from IDT on request. For more information on available default frequencies, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Shipping Package 8: T ape & Reel (no letter): T ray Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (T A = 0°C to 70°C) Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Die Revision G (opt. 207) Option Code (Supply V oltage and Frequency-Stability) A:V CC = 3.3V±5%, ±100ppm B:V CC = 2.5V±5%, ±100ppm E:V CC = 3.3V±5%, ±50ppm F:V CC = 2.5V±5%, ±50ppm K:V CC = 3.3V±5%, ±20ppm L:V CC = 2.5V±5%, ±20ppm Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. Last digit = L: configuration pre-programmed and not changeable dddd f XTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO 1000 to 1999 100.000 Integer XO 2000 to 2999 Fractional XO FemtoClock NG I/O Identifier 0: L VCMOS 3: L VPECL 4: L VDS Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin
001 XO 10 OE@2
003 XO 10 OE@1
V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 —
085 XO 6 OE@1
270 XO 6 OE@1
271 XO 6 OE@2
272 XO 6 nOE@2
273 XO 6 nOE@1
8N X X XXX X X - dddd XX X X Part/Order Number
IDT8N4QV01GCD REVISION A MARCH 11, 2014 18 ©2014 Integrated Device Technology, Inc. Table 9. Device Marking
IDT8N4QV01GCD REVISION A MARCH 11, 2014 19 ©2014 Integrated Device Technology, Inc. IDT8N4QV01 REV G DATA SHEET QUAD-FREQUENCY PROGRAMMABLE-VCXO Revision History Sheet Rev T able Page Description of Change Date A T9 18 Table 9 Device Marking, corrected marking. 3/6/12 A T1 T6A Deleted “(see table 3C)” from the first table row, description column. NOTE 2; Deleted “from table 3C”. 3/13/14
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved.
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