89HPES4T4G2

89HPES4T4G2 IDT | Alldatasheet

Document overview

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Technical content

Features

 High Performance PCI Express Switch – Four Gen2 PCI Express lanes supporting 5 Gbps and

2.5 Gbps operations

– Four switch ports

• One x1 upstream port
• Three x1 downstream ports – Low latency cut-through switch architecture – Support for Max Payload Size up to 2Kbytes – Supports one virtual channel and eight traffic classes – PCI Express Base Specification Revision 2.0 compliant  Flexible Architecture with Numerous Configuration Options – Automatic lane reversal on all ports – Automatic polarity inversion – Ability to load device conf iguration from serial EEPROM  Legacy Support – PCI compatible INTx emulation – Bus locking  Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates four 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed)
• Receive equalization (RxEQ)  Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protecti on on all TLPs ensures data integrity even in systems t hat do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – All internal data and control RAMs are SECDED ECC protected – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC mother- boards – Supports Hot-Swap Block Diagram Figure 1 Internal Block Diagram 4-Port Switch Core / 4 Gen2 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer (Port 0) (Port 1) SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer (Port 2) (Port 3) SerDes Phy Logical Layer Transaction Layer Data Link Layer Mux / Demux 89HPES4T4G2 Data Sheet 4-Lane 4-Port Gen2 PCI Express® Switch

3 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES4T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PE S4T4G2 utilizes an external I/O expander, such as that used on PC mother boards, connected to the SMBus mast er interface. Following res et and configura- tion, whenever the state of a Hot-Plug output needs to be modified, the PES4T4G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES4T4G2. In response to an I/O expander interrupt, the PES4T4G2 generates an SMBus transac tion to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES4T4G2 provides 7 General Purpose Inpu t/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Most GPIO pins are shared with other on-chip functions. These alter- nate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Processor PES4T4G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM Processor PES4T4G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses

4 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES4T4G2. Some of the functions listed may be multiplexed o nto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE0RP[0] PE0RN[0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for port 0. Port 0 is the upstream port. PE0TP[0] PE0TN[0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pair for port 0. Port 0 is the upstream port. PE1RP[0] PE1RN[0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pair for port 1. PE1TP[0] PE1TN[0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans- mit pair for port 1. PE2RP[0] PE2RN[0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for port 2. PE2TP[0] PE2TN[0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pair for port 2. PE3RP[0] PE3RN[0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PE3TP[0] PE3TN[0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans- mit pair for port 3. PEREFCLKP PEREFCLKN I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is set at 100MHz. Table 1 PCI Express Interface Pins Signal Type Name/Description MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus which operates at 400 KHz. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus which operates at 400 KHz. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 2 SMBus Interface Pins

5 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O expander interrupt 0 input. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 3 General Purpose I/O Pins

6 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each down- stream port’s PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES4T4G2 and initiates a PCI Express fundamental reset. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES4T4G2 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. Table 4 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 5 Test Pins

7 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Signal Type Name/Description REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES1 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES3 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. V DDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V). VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS I Ground. Table 6 Power, Ground, and SerDes Resistor Pins

8 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Pin Characteristics Note: Some input pads of the PES4T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[0] I PCIe differential2 Serial Link PE0RP[0] I PE0TN[0] O PE0TP[0] O PE1RN[0] I PE1RP[0] I PE1TN[0] O PE1TP[0] O PE2RN[0] I PE2RP[0] I PE2TN[0] O PE2TP[0] O PE3RN[0] I PE3RP[0] I PE3TN[0] O PE3TP[0] O PEREFCLKN I HCSL Diff. Clock Input Refer to Table 8 PEREFCLKP I SMBus MSMBCLK I/O STI 3 pull-up on board MSMBDAT I/O STI pull-up on board SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[10:7, 2:0] I/O LVTTL STI, High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I Input pull-up PERSTN I STI SWMODE[2:0] I Input pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up Table 7 Pin Characteristics (Part 1 of 2)

9 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet SerDes Reference Resistors REFRES0 I/O Analog Input REFRES1 I/O REFRES2 I/O REFRES3 I/O 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. 3. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 7 Pin Characteristics (Part 2 of 2)

10 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Logic Diagram — PES4T4G2 Figure 4 PES4T4G2 Logic Diagram PE0TP[0] Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[10:7,2:0]

7 General Purpose

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[2:0] CCLKDS PERSTN PE0RP[0] PE0RN[0] PCI Express Switch SerDes Input PE0TN[0] PCI Express Switch SerDes Output Port 0 Port 0 PE1RP[0] PE1RN[0] PCI Express Switch SerDes Input PE1TP[0] PE1TN[0] PCI Express Switch SerDes Output Port 1 Port 1 PE2RP[0] PE2RN[0] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PCI Express Switch SerDes Output Port 2 Port 2 PE3RP[0] PE3RN[0] PCI Express Switch SerDes Input PE3TP[0] PE3TN[0] PCI Express Switch SerDes Output Port 3 Port 3 PES4T4G2 REFRES0 SerDes Reference Resistors REFRES1 REFRES2 REFRES3 VDDPEHA VDDPETA

11 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 14. AC Timing Characteristics Parameter Description Condition Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 100 1 1. The input clock frequency is set at 100 MHz. MHz TC-RISE Rising edge rate Differential 0.6 4 V/ns TC-FALL Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 mV VIL Differential input low voltage Differential -150 mV voltage Single-ended +250 +550 mV VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended +140 mV VRB Ring back voltage margin Differential -100 +100 mV TSTABLE Time before VRB is allowed Differential 500 ps TPERIOD-AVG Average clock period accuracy -300 2800 ppm trum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps Duty Cycle Duty cycle 40 60 % Rise/Fall Matching Single ended rising Refclk edge rate ver- sus falling Refclk edge rate 20 % ZC-DC Clock source output DC impedance 40 60 Ω Table 8 Input Clock Requirements Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 PCIe Transmit UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps T TX-EYE Minimum Tx Eye Width 0.75 0.75 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.125 UI TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI TTX- IDLE-MIN Minimum time in idle 20 20 UI TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 88 n s Table 9 PCIe AC Timing Characteristics (Part 1 of 2)

12 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 8 8 ns TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI PCIe Receive UI Unit Interval 399.88 400 400.12 199.94 200.06 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-SKEW Lane to lane input skew 20 8 ns TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[10:7,2:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 10 GPIO AC Timing Characteristics Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 Table 9 PCIe AC Timing Characteristics (Part 2 of 2)

13 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 11 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

14 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Recommended Operating Supply Voltages Absolute Maximum Voltage Rating Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages in Table 12. The absolute maximum operating voltages in Table 13 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability. Power-Up/Power-Down Sequence During power supply ramp-up, V DDCORE must remain at least 1.0V below V DDI/O at all times. There are no other power-up sequence require- ments for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerD es LVPECL/CML 3.135 3.3 3.465 V VDDPEA1 1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. PCI Express Analog Power 0.95 1.0 1.1 V VDDPEHA2 2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA1 PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 12 PES4T4G2 Operating Voltages Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Table 13 PES4T4G2 Absolute Maximum Voltage Rating Grade Temperature Commercial 0 °C to +70°C Ambient Industrial -40 °C to +85°C Ambient Table 14 PES4T4G2 Operating Temperatures

15 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Am bient, 35% total link usage on all ports, typical voltages def ined in Table 12 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 12 (and also listed below). Thermal Considerations This section describes thermal cons iderations for the PES4T4G2 (19mm2 FCBGA324 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES4T4G2 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. Number of active Lanes per Port Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.1V Typ 3.3V Max 3.465V Typ Power Max Power 1/1/1/1 Full Swing mA 375 700 703 752 74 83 360 429 2 3 1/1/1/1 Half Swing mA 375 700 703 752 74 83 180 215 2 3 Table 15 PES4T4G2 Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oCM a x i m u m θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 16.8 oC/W Zero air flow 10.1 oC/W 1 m/S air flow 9.2 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 4.1 oC/W θJC Thermal Resistance, Junction-to-Case 0.3 oC/W P Power Dissipation of the Device 2.31 Watts Maximum Table 16 Thermal Specifications for PES4T4G2, 19x19 mm FCBGA324 Package

16 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- 3.5dB De-emphasized differential output voltage VTX-DE-RATIO- 6.0dB De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC-active- idle-delta Abs delta of DC common mode voltage between L0 and idle 100 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 66 d B ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120 Ω VTX-CM-ACpp Peak-Peak AC Common NA 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 0 3.6 0 3.6 V VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detec- tion 600 600 mV ITX-SHORT Transmitter Short Circuit Current Limit 09 0 9 0 m A Table 17 DC Electrical Characteristics (Part 1 of 2)

17 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Serial Link (cont.) PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to- peak) 175 1200 120 1200 mV RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz 8 1.25 - 2.5GHz RLRX-CM Receiver Common Mode Return Loss 66 d B ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec Ω ZRX--DC DC common mode impedance 40 50 60 40 60 Ω ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 50k Ω ZRX-HIGH-IMP-DC- POS DC input CM input impedance for V>0 during reset or power down 50k 50k Ω ZRX-HIGH-IMP-DC- NEG DC input CM input impedance for V<0 during reset or power down 1.0k 1.0k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 65 175 mV VRX-CM-ACp Receiver AC common-mode peak voltage 150 150 mV V RX-CM-ACp PCIe REFCLK CIN Input Capacitance 1.5 — 1.5 — pF Other I/Os LOW Drive Output I OL —2 . 5— —2 . 5 — m A V OL = 0.4v IOH —- 5 . 5— —- 5 . 5 — m A V OH = 1.5V High Drive Output IOL — 12.0 — — 12.0 — mA V OL = 0.4v Schmitt Trig- ger Input (STI) VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Input V IL -0.3 — 0.8 -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Capacitance C IN —— 8 . 5 ——8 . 5p F — Leakage Inputs — — + 10 — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 — — + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 — — + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 17 DC Electrical Characteristics (Part 2 of 2)

18 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet The following table lists the pin numbers and signal names for the PES4T4G2 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B17 NC D15 V DDCORE F13 V SS A2 V DDI/O B18 NC D16 V SS F14 NC A3 V DDI/O C1 NC D17 V SS F15 NC A4 V DDI/O C2 NC D18 V SS F16 V SS A5 V SS C3 V SS E1 NC F17 NC A6 V DDI/O C4 NC E2 NC F18 NC A7 V SS C5 NC E3 V SS G1 V SS A8 JTAG_TDI C6 V SS E4 NC G2 V SS A9 MSMBDAT C7 JTAG_TCK E5 NC G3 V SS A10 V DDI/O C8 JTAG_TRST_N E6 V DDCORE G4 V DDCORE A11 V SS C9 SSMBDAT E7 V DDCORE G5 V DDCORE A12 GPIO_00 1 C10 CCLKDS E8 V DDCORE G6 V DDPEA A13 V DDI/O C11 SWMODE_2 E9 V SS G7 V DDPEA A14 V DDI/O C12 GPIO_02 1 E10 V DDCORE G8 V DDCORE A15 V SS C13 GPIO_09 1 E11 V DDCORE G9 V DDCORE A16 V SS C14 NC E12 V DDCORE G10 V DDCORE A17 V DDI/O C15 NC E13 V DDCORE G11 V SS A18 V DDI/O C16 V SS E14 NC G12 V DDPEA B1 NC C17 NC E15 NC G13 V DDPEA B2 NC C18 NC E16 V SS G14 V DDCORE B3 V SS D1 V SS E17 NC G15 V DDCORE B4 NC D2 V SS E18 NC G16 V SS B5 NC D3 V SS F1 PE3TP00 G17 V SS B6 V DDI/O D4 V DDCORE F2 PE3TN00 G18 V SS B7 V DDI/O D5 V DDCORE F3 V SS H1 NC B8 JTAG_TMS D6 V SS F4 PE3RP00 H2 NC B9 SSMBCLK D7 JTAG_TDO F5 PE3RN00 H3 V SS B10 V DDI/O D8 MSMBCLK F6 V SS H4 NC B11 SWMODE_1 D9 CCLKUS F7 V SS H5 NC B12 GPIO_01 D10 SWMODE_0 F8 V DDCORE H6 V DDPEA B13 GPIO_10 D11 PERSTN F9 V SS H7 V DDPEA B14 NC D12 GPIO_07 1 F10 V DDCORE H8 V DDCORE B15 NC D13 GPIO_08 1 F11 V SS H9 V DDCORE B16 V SS D14 V DDCORE F12 V SS H10 V DDCORE H11 V SS K13 V DDPETA M15 NC P17 V DDCORE H12 V DDPEA K14 V DDCORE M16 V SS P18 V SS Table 18 PES4T4G2 324-pin Signal Pin-Out (Part 1 of 3)

19 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet H13 V DDPEA K15 NC M17 NC R1 V SS H14 NC K16 V SS M18 NC R2 V DDCORE H15 NC K17 NC N1 V SS R3 V DDCORE H16 V SS K18 NC N2 V SS R4 NC H17 NC L1 NC N3 V SS R5 NC H18 NC L2 NC N4 V DDCORE R6 NC J1 NC L3 V SS N5 V DDCORE R7 NC J2 NC L4 NC N6 V SS R8 PE1RP00 J3 V SS L5 NC N7 V SS R9 V DDCORE J4 NC L6 V DDPETA N8 V DDPEA R10 NC J5 NC L7 V DDPETA N9 V DDPEHA R11 NC J6 V DDPEHA L8 V DDPEA N10 V DDPETA R12 V DDCORE J7 V DDPEHA L9 V DDPEHA N11 V DDPEA R13 NC J8 V DDCORE L10 V DDPETA N12 V DDPEHA R14 PE0RP00 J9 V SS L11 V DDPEA N13 V SS R15 V DDCORE J10 V DDCORE L12 V DDPEHA N14 V SS R16 V DDCORE J11 V SS L13 V DDPETA N15 V DDCORE R17 V DDCORE J12 V DDPEHA L14 NC N16 V SS R18 V SS J13 V DDPEHA L15 NC N17 V SS T1 V SS J14 NC L16 V SS N18 V SS T2 V SS J15 NC L17 NC P1 V SS T3 V SS J16 V SS L18 NC P2 V DDCORE T4 V SS J17 NC M1 PE2TP00 P3 V DDCORE T5 V SS J18 NC M2 PE2TN00 P4 NC T6 V SS K1 REFRES2 M3 V SS P5 NC T7 V SS K2 REFRES3 M4 PE2RP00 P6 V DDCORE T8 V SS K3 V SS M5 PE2RN00 P7 NC T9 V SS K4 V DDCORE M6 V DDPETA P8 PE1RN00 T10 V SS K5 V DDCORE M7 V DDPETA P9 V DDCORE T11 V SS K6 V DDPETA M8 V DDPEA P10 NC T12 V SS K7 V DDPETA M9 V DDPEHA P11 NC T13 V SS K8 V DDCORE M10 V DDPETA P12 V DDCORE T14 V SS K9 V SS M11 V DDPEA P13 NC T15 V SS K10 V DDCORE M12 V DDPEHA P14 PE0RN00 T16 V SS K11 V SS M13 V SS P15 V DDCORE T17 V SS K12 V DDPETA M14 NC P16 V DDCORE T18 V SS U1 V SS U10 NC V1 V SS V10 NC U2 PEREFCLKN U11 NC V2 PEREFCLKP V11 NC Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES4T4G2 324-pin Signal Pin-Out (Part 2 of 3)

20 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Alternate Signal Functions No Connection Pins U3 V SS U12 V SS V3 V SS V12 V SS U4 NC U13 NC V4 NC V13 NC U5 NC U14 PE0TN00 V5 NC V14 PE0TP00 U6 REFRES1 U15 V SS V6 REFRES0 V15 V SS U7 NC U16 V SS V7 NC V16 V SS U8 PE1TN00 U17 V SS V8 PE1TP00 V17 V SS U9 V SS U18 V SS V9 V SS V18 V SS Pin GPIO Alternate A12 GPIO_00 P2RSTN C12 GPIO_02 IOEXPINTN0 D12 GPIO_07 GPEN D13 GPIO_08 P1RSTN C13 GPIO_09 P3RSTN Table 19 PES4T4G2 Alternate Signal Functions NC Pins NC Pins NC Pins NC Pins NC Pins NC Pins B1 C18 H4 K17 P5 U10 B2 E1 H5 K18 P7 U11 B4 E2 H14 L1 P10 U13 B5 E4 H15 L2 P11 V4 B14 E5 H17 L4 P13 V5 B15 E14 H18 L5 R4 V7 B17 E15 J1 L14 R5 V10 B18 E17 J2 L15 R6 V11 C1 E18 J4 L17 R7 V13 C2 F14 J5 L18 R10 C4 F15 J14 M14 R11 C5 F17 J15 M15 R13 C 1 4F 1 8J 1 7M 1 7 U 4 C15 H1 J18 M18 U5 C17 H2 K15 P4 U7 Table 20 PES4T4G2 No Connection Pins Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES4T4G2 324-pin Signal Pin-Out (Part 3 of 3)

21 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Power Pins VDDCore V DDCore V DDCore V DDI/O V DDPEA V DDPEHA V DDPETA D4 G9 N15 A2 G6 J6 K6 D5 G10 P2 A3 G7 J7 K7 D14 G14 P3 A4 G12 J12 K12 D15 G15 P6 A6 G13 J13 K13 E6 H8 P9 A10 H6 L9 L6 E7 H9 P12 A13 H7 L12 L7 E8 H10 P15 A14 H12 M9 L10 E10 J8 P16 A17 H13 M12 L13 E11 J10 P17 A18 L8 N9 M6 E12 K4 R2 B6 L11 N12 M7 E13 K5 R3 B7 M8 M10 F8 K8 R9 B10 M11 N10 F10 K10 R12 N8 G4 K14 R15 N11 G5 N4 R16 G8 N5 R17 Table 21 PES4T4G2 Power Pins

22 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Ground Pins Vss Vss Vss Vss Vss Vss A1 D18 G17 M16 T3 U3 A5 E3 G18 N1 T4 U9 A7 E9 H3 N2 T5 U12 A11 E16 H11 N3 T6 U15 A15 F3 H16 N6 T7 U16 A16 F6 J3 N7 T8 U17 B3 F7 J9 N13 T9 U18 B16 F9 J11 N14 T10 V1 C3 F11 J16 N16 T11 V3 C6 F12 K3 N17 T12 V9 C16 F13 K9 N18 T13 V12 D1 F16 K11 P1 T14 V15 D2 G1 K16 P18 T15 V16 D3 G2 L3 R1 T16 V17 D6 G3 L16 R18 T17 V18 D16 G11 M3 T1 T18 D17 G16 M13 T2 U1 Table 22 PES4T4G2 Ground Pins

23 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I C10 System CCLKUS I D9 GPIO_00 I/O A12 General Purpose Input/Output GPIO_01 I/O B12 GPIO_02 I/O C12 GPIO_07 I/O D12 GPIO_08 I/O D13 GPIO_09 I/O C13 GPIO_10 I/O B13 JTAG_TCK I C7 JTAG JTAG_TDI I A8 JTAG_TDO O D7 JTAG_TMS I B8 JTAG_TRST_N I C8 MSMBCLK I/O D8 SMBus MSMBDAT I/O A9 NO CONNECTION See Table 20 PE0RN00 I P14 PCI Express PE0RP00 I R14 PE0TN00 O U14 PE0TP00 O V14 PE1RN00 I P8 PE1RP00 I R8 PE1TN00 O U8 PE1TP00 O V8 PE2RN00 I M5 PE2RP00 I M4 PE2TN00 O M2 PE2TP00 O M1 PE3RN00 I F5 PE3RP00 I F4 PE3TN00 O F2 PE3TP00 O F1 Table 23 89PES4T4G2 Alphabetical Signal List (Part 1 of 2)

24 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet PEREFCLKN I U2 PCI Express (cont.) PEREFCLKP I V2 PERSTN I D11 System REFRES0 I/O V6 SerDes Reference Resistors REFRES1 I/O U6 REFRES2 I/O K1 REFRES3 I/O K2 SSMBCLK I/O B9 SMBus SSMBDAT I/O C9 SWMODE_0 I D10 System SWMODE_1 I B11 SWMODE_2 I C11 V DDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA See Table 21 for a listing of power pins. VSS See Table 22 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 23 89PES4T4G2 Alphabetical Signal List (Part 2 of 2)

25 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet PES4T4G2 — Package Trace Length Signal Name Conductor Length (microns) PE0RN00 6476.76 PE0RP00 6852.44 PE0TN00 9779.14 PE0TP00 9830.77 PE1RN00 3844.19 PE1RP00 4219.88 PE1TN00 7518.88 PE1TP00 7605.87 PE2RN00 2227.99 PE2RP00 2600.58 PE2TN00 5462.64 PE2TP00 5576.55 PE3RN00 9181.06 PE3RP00 9541.52 PE3TN00 10606.88 PE3TP00 10747.72 PEREFCLKN 12558.62 PEREFCLKP 12641.05 Table 24 Signal Trace Length

26 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet PES4T4G2 Pinout — Top View 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 C D E F G H J K L M N P R T U V VDDPETA (Power) VDDPEA (Power) VDDPEHA (Power) Signals 12 3 4 5 6 7 89 1 0 1 1 1 2 1 3 1 4 1 5 1 6 17 18 A B C D E F G H J K L M N P R T U V x No Connect X X X X XX X XX X X X

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Revision History

January 15, 2009: Publication of final data sheet. February 11, 2009: Revised AC Timing Characteristics table and DC Electrical Characteristics table to correct typos. March 6, 2009: Added industrial temperature. April 7, 2009: In Valid Combinations, changed ZB to ZC silicon for commercial temperature. April 17, 2009: In Table 15, Power Dissipation value was changed to 2.31. February 2, 2010: Added new section Absolute Maximum Voltage Rating with table. September 13, 2010: In Table 7, changed Buffer type for PCI Express from CML to PCIe differential and changed reference clocks to HCSL. March 30, 2011: In Table 12, added VddPETA to footnote #1. May 23, 2013: In the Features section, added reference to SECDED ECC under Reliability, Availability, Serviceability bullet.

30 of 30 May 23, 2013 IDT 89HPES4T4G2 Data Sheet CORPORATE HEADQUARTERS

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Ordering Information

89HPES4T4G2ZCAL 324-ball FCBGA pac kage, Commercial Temperature 89HPES4T4G2ZCALG 324-ball Green FCBGA package, Commercial Temperature 89HPES4T4G2ZCALI 324-ball FCBGA pac kage, Industrial Temperature 89HPES4T4G2ZCALGI 324-ball Green FCBG A package, Industrial Temperature NN A AAA NAN AA A Operating Voltage Device Family Product Package Temp Range H Product Family

89 Serial Switching Product

4T4 4-lane, 4-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character 324-ball FCBGA, Green ALG AA Device Revision AN Generation Series G2 PCIe Gen 2 ZC ZC revision Blank Commercial Temperature (0°C to +70°C Ambient) I Industrial Temperature (-40° C to +85° C Ambient)