89HPES4T4

89HPES4T4 RENESAS | Alldatasheet

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 High Performance PCI Express Switch – Four 2.5 Gbps PCI Express lanes – Four switch ports – x1 Upstream port – Three x1 Downstream ports – Low latency cut-through switch architecture – Support for Max payload sizes up to 256 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant  Flexible Architecture with Numerous Configuration Options – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device conf iguration from serial EEPROM  Legacy Support – PCI compatible INTx emulation – Bus locking  Highly Integrated Solution Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates four 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed)  Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protec tion on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC mother- boards  Power Management – Utilizes advanced low-power desi gn techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI- PM 1.2) – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Speci- fication, Revision 2.0 (ACPI) supporting active link state  Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters Block Diagram Figure 1 Internal Block Diagram 4-Port Switch Core / 4 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer (Port 0) (Port 2) SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer SerDes Phy Logical Layer Mux / Demux Transaction Layer Data Link Layer (Port 3) (Port 4) SerDes Phy Logical Layer Transaction Layer Data Link Layer Mux / Demux 89HPES4T4 Data Sheet 4-Lane 4-Port PCI Express® Switch

2 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet  5 General Purpose Input/Output Pins – Each pin may be individually co nfigured as an input or output – Each pin may be individually co nfigured as an interrupt input – Each pin has a selectable alternate function  Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing  Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES4T4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low latency, and simple board layout with a minimum number of board la yers. Each lane provides 2.5 Gbps of bandwidth in both direct ions and is fully compliant with PCI Express Base specification 1.1. The PES4T4 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac- tion layers in compliance with PCI Expre ss Base specification Revision 1.1. The PES4 T4 can operate either as a store and forwar d or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity. Figure 2 I/O Expansion Application SMBus Interface The PES4T4 contains an SMBus master interface. This master interface allows the default configuration register values of the PES4T4 to be over- ridden following a reset with values programmed in an external se rial EEPROM. The master interfac e is also used by an external Hot-Plug I/O expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin. Hot-Plug Interface The PES4T4 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when- ever the state of a Hot-Plug output needs to be modified, the PES4T4 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN inpu t pin (alternate function of GPIO) of the PES4T4. In response to an I/O expander interrupt, the PES4T4 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. MemoryMemoryMemory Processor MemoryNorth Bridge PES4T4 Processor x1 x1 GE South Bridge GE 1394 LOM LOM

3 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet General Purpose Input/Output The PES4T4 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software c ontrol, and some GPIO pins are shared with another on-chip functions. These alternate functions may be enabled via software or serial configuration EEPROM. Pin Description The following tables lists the functions of the pins provided on the PES4T4. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE0RP[0] PE0RN[0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for port 0. PE0TP[0] PE0TN[0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pair for port 0. PE2RP[0] PE2RN[0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for port 2. PE2TP[0] PE2TN[0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pair for port 2. PE3RP[0] PE3RN[0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PE3TP[0] PE3TN[0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans- mit pair for port 3. PE4RP[0] PE4RN[0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair for port 4. PE4TP[0] PE4TN[0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pair for port 4. PEREFCLKP PEREFCLKN I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. Table 1 PCI Express Interface Pins Signal Type Name/Description MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. Table 2 SMBus Interface Pins

4 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 Table 3 General Purpose I/O Pins Signal Type Name/Description APWRDISN I Auxiliary Power Disable Input. When this pin is active, it disables the device from using auxiliary power supply. CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be override by modifying the SCLK bit in the downstream port’s PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS register. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES4T4 and initiates a PCI Express fundamental reset. Table 4 System Pins (Part 1 of 2)

5 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES4T4 executes the reset procedure and remains in a reset state with the Master SMBus active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by the SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES4T4 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved WAKEN I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN signal input/output selection can be made through WAKEDIR bit setting in the WAKEUPCNTL register. Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 5 Test Pins Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 6 Power and Ground Pins Signal Type Name/Description Table 4 System Pins (Part 2 of 2)

6 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Pin Characteristics Note: Some input pads of the PES4T4 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor Notes PCI Express Inter- face PE0RN[0] I CML Serial Link PE0RP[0] I PE0TN[0] O PE0TP[0] O PE2RN[0] I PE2RP[0] I PE2TN[0] O PE2TP[0] O PE3RN[0] I PE3RP[0] I PE3TN[0] O PE3TP[0] O PE4RN[0] I PE4RP[0] I PE4TN[0] O PE4TP[0] O PEREFCLKN I LVPECL/ CML Diff. Clock Input Refer toTable 8 PEREFCLKP I SMBus MSMBCLK I/O LVTTL STI 1. Schmitt Trigger Input (STI). MSMBDAT I/O General Purpose I/O GPIO[9,7,2:0] I/O LVTTL High Drive pull-up System Pins APWRDISN I LVTTL Input pull-down CCLKDS I pull-up CCLKUS I pull-up PERSTN I RSTHALT I pull-down SWMODE[2:0] I pull-down WAKEN I/O open-drain EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up Table 7 Pin Characteristics

7 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Logic Diagram — PES4T4 Figure 3 PES4T4 Logic Diagram Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[9,7,2:0]

5 General Purpose

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSSSWMODE[2:0] CCLKDS PERSTN VTTPE PE0RP[0] PE0RN[0] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PCI Express Switch SerDes Output Port 0 Port 0 PE2RP[0] PE2RN[0] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PCI Express Switch SerDes Output Port 2 Port 2 PE3RP[0] PE3RN[0] PCI Express Switch SerDes Input PE3TP[0] PE3TN[0] PCI Express Switch SerDes Output Port 3 Port 3 PES4T4 PE4RP[0] PE4RN[0] PCI Express Switch SerDes Input Port 4 PE4TP[0] PE4TN[0] PCI Express Switch SerDes Output Port 4 MSMBCLK MSMBDAT Master SMBus Interface WAKEN APWRDISN

8 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. AC Timing Characteristics Parameter Description Min Typical Max Unit PEREFCLK RefclkFREQ Input reference clock frequency range 100 MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 2 2. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing3 3. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps Table 8 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps T TX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps TBTEn Time from asserting Beacon TxEn to beacon being trans- mitted on the lane 30 80 ns PCIe Receive UI Unit Interval 399.88 400 400.12 ps TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI Table 9 PCIe AC Timing Characteristics (Part 1 of 2)

9 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Figure 4 GPIO AC Timing Waveform TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[9,7,2:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns See Figure 4. Table 10 GPIO AC Timing Characteristics Parameter Description Min 1 Typical1 Max1 Units Table 9 PCIe AC Timing Characteristics (Part 2 of 2) Tdo_13aTdo_13a Tpw_13b EXTCLK GPIO (synchronous output) GPIO (asynchronous input)

10 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 25.0 50.0 ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 11.3 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —1 1 . 3n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 11 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

11 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Recommended Operating Supply Voltages Power-Up/Power-Down Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES4T4, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence. Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 12. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 12. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for Se rDes LVPECL/CML 3 .135 3.3 3.465 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 12 PES4T4 Operating Voltages Grade Temperature Commercial 0 C to +70C Ambient Industrial -40 C to +85C Ambient Table 13 PES4T4 Operating Temperatures Number of Connected Lanes Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.465V Typ Power Max Power 1/1/1/1 mA 270 363 218 279 110 130 101 125 3 3.3 Table 14 PES4T4 Power Consumption

12 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Thermal Considerations — Option A Package This section describes thermal considerations for the PES4T4 (13mm2 BCG144 package). The data in Table 15 below contains information that is relevant to the thermal performance of the PES4T4 switch. Thermal Considerations — Option B Package This section describes thermal considerations for the PES4T4 (10mm2 NQG132 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES4T4 switch. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products TA(max) Ambient Temperature 85 oC Maximum for industrial-rated products JA(effective) Effective Thermal Resistance, Junction-to-Ambient 34.6 oC/W Zero air flow 30.3 oC/W 1 m/S air flow 28.4 oC/W 2 m/S air flow JB Thermal Resistance, Junction-to-Board 18.8 oC/W JC Thermal Resistance, Junction-to-Case 10 oC/W P Power Dissipation of the Device 1.06 Watts Maximum Table 15 Thermal Specifications for PES4T4, 13x13mm BCG144 Package Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products JA(effective) Effective Thermal Resistance, Junction-to-Ambient 23.5 oC/W Zero air flow 19.6 oC/W 1 m/S air flow 17.4 oC/W 2 m/S air flow JB Thermal Resistance, Junction-to-Board 0.2 oC/W JC Thermal Resistance, Junction-to-Case 7.6 oC/W P Power Dissipation of the Device 1.06 Watts Maximum Table 16 Thermal Specifications for PES4T4, 10x10mm NQG132 Package

13 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 10 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120  ZOSE Single ended TX Impedance 40 50 60  Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 10 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120  ZRX-COMM-DC Single-ended input impedance 40 50 60  ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k  VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 17 DC Electrical Characteristics (Part 1 of 2)

14 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 AV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 AV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 AV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 17 DC Electrical Characteristics (Part 2 of 2)

15 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Option A Package Pinout — 144-BGA Signal Pinout for PES4T4 The following table lists the pin numbers and signal names for the PES4T4 144-pin device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS C11 V DDCORE F9 V DDCORE J7 V SS A2 V DDI/O C12 V SS F10 V DDI/O J8 V DDCORE A3 APWRDISN D1 JTAG_TDO F11 V DDI/O J9 V SS A4 V TTPE D2 MSMBCLK F12 GPIO_01 1 J10 V SS A5 V TTPE D3 V DDCORE G1 V SS J11 V DDI/O A6 PE0TP00 D4 V SS G2 JTAG_TRST_N J12 GPIO_09 1 A7 V DDPE D5 V SS G3 V SS K1 V SS A8 PE0RP00 D6 V SS G4 V DDCORE K2 V DDCORE A9 V DDI/O D7 V DDCORE G5 V SS K3 V DDI/O A10 SWMODE_0 D8 V SS G6 V DDCORE K4 V DDCORE A11 SWMODE_1 D9 V SS G7 V SS K5 V DDPE A12 V SS D10 V SS G8 V DDCORE K6 V SS B1 V DDCORE D11 PERSTN G9 V SS K7 V DDPE B2 WAKEN D12 RSTHALT G10 V DDCORE K8 V SS B3 CCLKUS E1 JTAG_TDI G11 V SS K9 V DDCORE B4 V DDPE E2 MSMBDAT G12 GPIO_02 1 K10 V DDI/O B5 V DDPE E3 V DDI/O H1 PEREFCLKP K11 V SS B6 PE0TN00 E4 V DDCORE H2 V DDI/O K12 V SS B7 V DDPE E5 V SS H3 V DDAPE L1 PE2RN00 B8 PE0RN00 E6 V DDCORE H4 V SS L2 V SS B9 CCLKDS E7 V SS H5 V SS L3 PE2TP00 B10 SWMODE_2 E8 V SS H6 V SS L4 V SS B11 V SS E9 V SS H7 V DDCORE L5 PE3TN00 B12 V SS E10 V DDCORE H8 V SS L6 V DDAPE C1 JTAG_TMS E11 V SS H9 V SS L7 PE3RN00 C2 V SS E12 GPIO_00 1 H10 V DDCORE L8 V TTPE C3 V SS F1 JTAG_TCK H11 V SS L9 PE4RP00 C4 V DDCORE F2 V DDI/O H12 GPIO_07 1 L10 V SS C5 V DDAPE F3 V DDCORE J1 PEREFCLKN L11 PE4TN00 C6 V DDAPE F4 V SS J2 V SS L12 V DDCORE C7 V SS F5 V DDCORE J3 V SS M1 PE2RP00 C8 V DDCORE F6 V SS J4 V SS M2 V SS C9 V DDCORE F7 V DDCORE J5 V SS M3 PE2TN00 C10 V SS F8 V SS J6 V DDCORE M4 V TTPE Table 18 PES4T4 144-pin Signal Pin-Out (Part 1 of 2)

16 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package A Alternate Signal Functions Package A Power Pins M5 PE3TP00 M7 PE3RP00 M9 PE4RN00 M11 PE4TP00 M6 V SS M8 V DDAPE M10 V SS M12 V SS Pin GPIO Alternate E12 GPIO_00 P2RSTN F12 GPIO_01 P4RSTN G12 GPIO_02 IOEXPINTN0 H12 GPIO_07 GPEN J12 GPIO_09 P3RSTN Table 19 PES4T4 144-pin Alternate Signal Functions VDDCore V DDCore V DDI/O V DDPE V DDAPE V TTPE B1 F9 A2 A7 C5 A4 C4 G4 A9 B4 C6 A5 C8 G6 E3 B5 H3 L8 C9 G8 F2 B7 L6 M4 C11 G10 F10 K5 M8 D3 H7 F11 K7 D7 H10 H2 E4 J6 J11 E6 J8 K3 E10 K2 K10 F3 K4 F5 K9 F7 L12 Table 20 PES4T4 144-pin Power Pins Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES4T4 144-pin Signal Pin-Out (Part 2 of 2)

17 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package A Ground Pins Package A Pin Signals Listed Alphabetically Vss V ss V ss V ss A1 D10 G11 K1 A12 E5 H4 K6 B11 E7 H5 K8 B 1 2 E 8H 6K 1 1 C2 E9 H8 K12 C3 E11 H9 L2 C7 F4 H11 L4 C10 F6 J2 L10 C12 F8 J3 M2 D4 G1 J4 M6 D5 G3 J5 M10 D6 G5 J7 M12 D8 G7 J9 D9 G9 J10 Table 21 PES4T4 144-pin Ground Pins Signal Name I/O Type Location Signal Category APWRDISN I A3 System CCLKDS I B9 CCLKUS I B3 GPIO_00 I/O E12 General Purpose Input/Output GPIO_01 I/O F12 GPIO_02 I/O G12 GPIO_07 I/O H12 GPIO_09 I/O J12 JTAG_TCK I F1 JTAG JTAG_TDI I E1 JTAG_TDO I D1 JTAG-TMS O C1 JTAG-TRST_N I G2 MSMBCLK I/O D2 SMBus MSMBDAT I/O E2 Table 22 89PES4T4 144-pin Alphabetical Signal List (Part 1 of 2)

18 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet PE0RN00 I B8 PCI Express PE0RP00 I A8 PE0TN00 O B6 PE0TP00 O A6 PE2RN00 I L1 PE2RP00 I M1 PE2TN00 O M3 PE2TP00 O L3 PE3RN00 I L7 PE3RP00 I M7 PE3TN00 O L5 PE3TP00 O M5 PE4RN00 I M9 PE4RP00 I L9 PE4TN00 O L11 PE4TP00 O M11 PEREFCLKN I J1 PEREFCLKP I H1 PERSTN I D11 System RSTHALT I D12 SWMODE_0 I A10 SWMODE_1 I A11 SWMODE_2 I B10 WAKEN I/O B2 V DDCORE, VDDAPE, VDDI/O, VDDPE, VTTPE See Table 20 for a listing of power pins. VSS See Table 21 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 22 89PES4T4 144-pin Alphabetical Signal List (Part 2 of 2)

19 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package A Pinout — Top View 123 456 7 89 1 0 1 1 1 2 Vss (Ground)VDDCore (Power) VDDI/O (Power) VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals A B C D E F G H J K L M x A B C D E F G H J K L M 123 456 7 89 1 0 1 1 1 2 X X XX

20 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet 1.50 1.60 1.70

21 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package A Package Drawing — Page Two

22 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet The following table lists the pin numbers and signal names for the PES4T4 132-pin device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 NC A34 V DDCORE A67 V DDPE B28 V DDPE A2 NC A35 NC A68 V DDCORE B29 V DDPE A3 V DDI/O A36 NC A69 V DDI/O B30 V DDCORE A4 V DDI/O A37 NC A70 WAKEN B31 V DDCORE A5 V DDCORE A38 NC A71 NC B32 V SS A6 V DDCORE A39 GPIO_09 1 A72 NC B33 V DDCORE A7 MSMBDAT A40 V DDCORE B1 V SS B34 V SS A8 MSMBCLK A41 V DDCORE B2 V SS B35 V DDI/O A9 V SS A42 GPIO_07 1 B3 V DDI/O B36 V SS A10 JTAG_TRST_N A43 V SS B4 V SS B37 V DDCORE A11 JTAG_TMS A44 NC B5 V DDCORE B38 V DDI/O A12 JTAG_TDO A45 NC B6 V SS B39 V DDCORE A13 JTAG_TDI A46 V SS B7 V SS B40 V DDCORE A14 JTAG_TCK A47 V DDI/O B8 V DDCORE B41 V DDI/O A15 PEREFCLKP A48 GPIO_02 1 B9 V DDI/O B42 V DDCORE A16 PEREFCLKN A49 GPIO_01 1 B10 V DDCORE B43 V SS A17 NC A50 GPIO_00 1 B11 V SS B44 RSTHALT A18 NC A51 V DDI/O B12 V DDCORE B45 PERSTN A19 NC A52 V DDCORE B13 V SS B46 SWMODE_2 A20 NC A53 NC B14 V DDAPE B47 V SS A21 V DDCORE A54 NC B15 V SS B48 V DDCORE A22 PE2RP00 A55 NC B16 V DDI/O B49 CCLKDS A23 PE2TP00 A56 NC B17 PE2RN00 B50 V SS A24 PE2TN00 A57 SWMODE_1 B18 V SS B51 V DDPE A25 PE3TN00 A58 SWMODE_0 B19 V DDPE B52 V DDPE A26 PE3TP00 A59 V DDI/O B20 V TTPE B53 V TTPE A27 PE3RP00 A60 PE0RN00 B21 V DDPE B54 V DDAPE A28 PE3RN00 A61 PE0RP00 B22 V SS B55 V DDAPE A29 V DDAPE A62 PE0TP00 B23 V SS B56 V DDAPE A30 PE4RN00 A63 PE0TN00 B24 V DDAPE B57 V SS A31 PE4RP00 A64 V DDPE B25 V SS B58 APWRDISN A32 PE4TP00 A65 V DDAPE B26 V SS B59 V DDCORE A33 PE4TN00 A66 V DDAPE B27 V TTPE B60 CCLKUS Table 23 PES4T4 132-pin Signal Pin-Out

23 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package B Alternate Signal Functions Package B Power Pins Pin GPIO Alternate A50 GPIO_00 P2RSTN A49 GPIO_01 P4RSTN A48 GPIO_02 IOEXPINTN0 A42 GPIO_07 GPEN A39 GPIO_09 P3RSTN Table 24 PES4T4 132-pin Alternate Signal Functions V DDCore V DDCore V DDI/O V DDPE V DDAPE V TTPE A5 B12 A3 A64 A29 B20 A6 B30 A4 A67 A65 B27 A21 B31 A47 B19 A66 B53 A34 B33 A51 B21 B14 A40 B37 A59 B28 B24 A41 B39 A69 B29 B54 A52 B40 B3 B51 B55 A68 B42 B9 B52 B56 B5 B48 B16 B8 B59 B35 B10 — B38 B41 Table 25 PES4T4 132-pin Power Pins

24 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package B Ground Pins Package B No Connection Pins Package B Pin Signals Listed Alphabetically Vss V ss V ss V ss A9 B6 B22 B36 A 4 3B 7B 2 3B 4 3 A46 B11 B25 B47 B1 B13 B26 B50 B2 B15 B32 B57 B4 B18 B34 — Table 26 PES4T4 132-pin Ground Pins NC NC A1 A38 A2 A44 A17 A45 A18 A53 A19 A54 A20 A55 A35 A56 A36 A71 A37 A72 Table 27 PES4T4 132-pin No Connection Pins Signal Name I/O Type Location Signal Category APWRDISN I B58 System CCLKDS I B49 CCLKUS I B60 GPIO_00 I/O A50 General Purpose Input/Output GPIO_01 I/O A49 GPIO_02 I/O A48 GPIO_07 I/O A42 GPIO_09 I/O A39 Table 28 89PES4T4 132-pin Alphabetical Signal List (Part 1 of 2)

25 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet JTAG_TCK I A14 JTAG JTAG_TDI I A13 JTAG_TDO I A12 JTAG-TMS O A11 JTAG-TRST_N I A10 MSMBCLK I/O A8 SMBus MSMBDAT I/O A7 NC See Table 27 for a listing of no connection pins. PE0RN00 I A60 PCI Express PE0RP00 I A61 PE0TN00 O A63 PE0TP00 O A62 PE2RN00 I B17 PE2RP00 I A22 PE2TN00 O A24 PE2TP00 O A23 PE3RN00 I A28 PE3RP00 I A27 PE3TN00 O A25 PE3TP00 O A26 PE4RN00 I A30 PE4RP00 I A31 PE4TN00 O A33 PE4TP00 O A32 PEREFCLKN I A16 PEREFCLKP I A15 PERSTN I B45 System RSTHALT I B44 SWMODE_0 I A58 SWMODE_1 I A57 SWMODE_2 I B46 WAKEN I/O A70 V DDCORE, VDDAPE, VDDI/O, VDDPE, VTTPE See Table 25 for a listing of power pins. VSS See Table 26 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 28 89PES4T4 132-pin Alphabetical Signal List (Part 2 of 2)

26 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package B Pinout — Top View A72 B60 A57 A56 A54 A53 A52 A51 B59 B58 B57 B46 B44 A71 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 A50 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 B45 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 A35A34A33A32 B30B29 A31A30A29A28A27A26A25A24A23A22A21A20A19 B28B27B26B25B24B23B22B21B20B19B18B17B16 B15 B14 B13 B12 B11 B10 A18 A17 A16 A15 A14 A13 A12 A11 A10 Vss (Ground) VDDCore (Power) VDDI/O (Power) VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signalsx No Connection X XX A36 A55

27 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet

28 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet Package B Package Drawing — Page Two : 6.5mm x 6.5mm

29 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet

Revision History

March 31, 2008: Publication of final data sheet. June 4, 2008: For the 132-QFN package, changed pins A44 and A45 from GPIO to No Connect and changed pin B6 from VDDCORE to VSS. August 6, 2008: Added industrial temperature information to Tables 13 and 15 and to Ordering Information section. Revised Package B Pinout Top View graphic to match page 3 of the Package B drawing. May 7, 2009: Revised labels in Table 14, Power Consumption, for greater clarification. October 8, 2010: Added package height data to Note 10 on Page Two of Package B drawing and removed page 3 of Package B drawing. January 25, 2011: In Table 8, deleted reference to 125MHz as max value for RefclkFREQ. June 12, 2014: Changed symbol A in Package A Package Drawing — 144-Pin BC144/BCG144 to match the package characteristics of the part. The new definition for the symbol is 1.50 minimum, 1.60 nominal, and 1.70 maximum.

30 of 30 June 12, 2014 IDT 89HPES4T4 Data Sheet CORPORATE HEADQUARTERS

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San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208

Ordering Information

89HPES4T4ZBBC 144-pin BC144 pac kage, Commercial Temperature 89HPES4T4ZBBCG 144-pin Green BC144 package, Comm ercial Temperature 89HPES4T4ZBBCI 144-pin BC144 package, Industrial Temperature 89HPES4T4ZBBCGI 144-pin Green BC144 package, Industrial Temperature 89HPES4T4ZBNQ 132-pin NQ132 package, Commercial Temperature 89HPES4T4ZBNQG 132-pin Green NQ132 package, Commercial Temperature NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

4T4 4-lane, 4-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BCG144 144-ball CABGA, Green BCG AA Device Revision ZB ZB revision NQ132 132-ball QFN NQ NQG132 132-ball QFN, Green NQG I Industrial Temperature (-40° C to +85° C Ambient)

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