89HPES48H12AG2

Integrated Device Techn...

Low latency cut-through architecture

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Features

 High Performance Non-Blocking Switch Architecture – 48-lane 12-port PCIe switch

Six x8 ports switch ports each of which can bifurcate to two x4 ports (total of twelve x4 ports) – Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation – Delivers up to 48 GBps (384 Gbps) of switching capacity – Supports 128 Bytes to 2 KB maximum payload size – Low latency cut-through architecture – Supports one virtual channel and eight traffic classes  Standards and Compatibility – PCI Express Base Specification 2.0 compliant – Implements the following optional PCI Express features
Advanced Error Reporting (AER) on all ports
End-to-End CRC (ECRC)
Access Control Services (ACS)
Power Budgeting Enhanced Capability
Device Serial Number Enhanced Capability
Sub-System ID and Sub-System Vendor ID Capability
Internal Error Reporting ECN
Multicast ECN
VGA and ISA enable
L0s and L1 ASPM
A R I E C N  Port Configurability – x4 and x8 ports
Ability to merge adjacent x4 ports to create a x8 port – Automatic per port link width negotiation – Crosslink support – Automatic lane reversal – Autonomous and software managed link width and speed control – Per lane SerDes configuration
De-emphasis
Receive equalization
Drive strength  Switch Partitioning – IDT proprietary feature that creates logically independent switches in the device – Supports up to 12 fully independent switch partitions – Configurable downstream port device numbering – Supports dynamic reconfiguration of switch partitions
Dynamic port reconfigur ation — downstream, upstream
Dynamic migration of ports between partitions
Movable upstream port within and between switch partitions  Initialization / Configuration – Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization – Common switch configurations are supported with pin strap- ping (no external components) – Supports in-system Serial EEPR OM initialization/program- ming  Quality of Service (QoS) – Port arbitration
Round robin – Request metering
IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput – High performance switch core architecture
Combined Input Output Queued (CIOQ) switch architecture with large buffers  Multicast – Compliant to the PCI-SIG multicast ECN – Supports arbitrary multicasting of Posted transactions – Supports 64 multicast groups – Multicast overlay mechanism support – ECRC regeneration support  Clocking – Supports 100 MHz and 125 MHz reference clock frequencies – Flexible port clocking modes
Common clock
Non-common clock
Local port clock with SSC and port reference clock input  Hot-Plug and Hot Swap – Hot-plug controller on all ports
Hot-plug supported on all downstream switch ports – All ports support hot-plug us ing low-cost external I 2C I/O expanders 89HPES48H12AG2 Datasheet 48-Lane 12-Port PCIe® Gen2 System Interconnect Switch

2 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet – Direct package pin support for hot-plug on 5 ports – Configurable presence detect supports card and cable appli- cations – GPE output pin for hot-plug event notification

Enables SCI/SMI generation for legacy operating system support – Hot-swap capable I/O  Power Management – Supports D0, D3hot and D3 power management states – Active State Power Management (ASPM)
Supports L0, L0s, L1, L2/L3 Ready and L3 link states
Configurable L0s and L1 entry timers allow performance/ power-savings tuning – Supports PCI Express Power Budgeting Capability – SerDes power savings
Supports low swing / half-swing SerDes operation
SerDes optionally turned-off in D3hot
SerDes associated with unused ports are turned-off
SerDes associated with unused lanes are placed in a low power state  54 General Purpose I/O  Reliability, Availability and Serviceability (RAS) – ECRC support – AER on all ports – SECDED ECC protection on all internal RAMs – End-to-end data path parity protection – Checksum Serial EEPROM content protected – Autonomous link reliability (preserves system operation in the presence of faulty links) – Ability to generate an interrupt (INTx or MSI) on link up/down transitions  Test and Debug – On-chip link activity and status outputs available for several ports including the upstream ports – Per port link activity and status outputs available using external I2C I/O expander for all remaining ports – SerDes test modes – Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG  Power Supplies – Requires only two power supply voltages (1.0 V and 2.5 V) Note that a 3.3V is preferred for VDDI/O – No power sequencing requirements  Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES48H12AG2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 48 GBps (384 Gbps) of aggregated, full-duplex switching capacity through 48 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 GT/s of band- width in both directions and is full y compliant with PCI Express Base Specification, Revision 2.0. The PES48H12AG2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base spec- ification Revision 2.0. The PES48H12AG2 can operate either as a store and forward or cut-through switch. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient swit ching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. The PES48H12AG2 is a partitionable PCIe switch. This means that in addition to operating as a standard PCI express switch, the PES48H12AG2 ports may be partitioned into groups that logically operate as completely independent PCIe switches. Figure 2 illustrates a three partition PES48H12AG2 configuration.

3 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Block Diagram Figure 1 Internal Block Diagram Figure 2 Example of Usage of Switch Partitioning SMBus Interface The PES48H12AG2 contains two SMBus interfaces . The slave interface provides full access to the configuration registers in the P ES48H12AG2, allowing every configuration regi ster in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES48H12AG2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander.

48 PCI Express Lanes

Up to 6 x8 ports or 12 x4 Ports 12-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 Partition 1 – Virtual PCI Bus P2P Bridge Partition 1 Upstream Port P2P Bridge P2P Bridge P2P Bridge P2P Bridge Partition 2 – Virtual PCI Bus P2P Bridge P2P Bridge P2P Bridge Partition 3 – Virtual PCI Bus P2P Bridge P2P Bridge P2P Bridge Partition 1 Downstream Ports Partition 2 Downstream Ports Partition 3 Downstream Ports Partition 2 Upstream Port Partition 3 Upstream Port

4 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master in terface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corr esponding address pins. When the pins are sa mpled, the resulting address is assigned as shown in Table 1. As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration. Figure 3 Split SMBus Interface Configuration The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM and I/O expander slav es. In the split configuration, the master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. Hot-Plug Interface The PES48H12AG2 supports PCI Express Hot-Pl ug on each downstream port. To reduce the num ber of pins required on the device, the PES48H12AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. F ollowing reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12AG2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt w hich is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12AG2. In response to an I/O expander interrupt, the PES48H12 AG2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment Processor Switch SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM ... Hot-Plug I/O Expander

5 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet General Purpose Input/Output The PES48H12AG2 provides 54 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. So me GPIO pins are shared with other on-chi p functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Pin Description The following tables list the functions of the pins provided on the PES48H12AG2. Some of the functions listed may be multiplexe d onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE00RP[3:0] PE00RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. PE00TP[3:0] PE00TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. PE01RP[3:0] PE01RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PE01TP[3:0] PE01TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PE02RP[3:0] PE02RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE02TP[3:0] PE02TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE03RP[3:0] PE03RN[3:0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. PE03TP[3:0] PE03TN[3:0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 3. When port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. PE04RP[3:0] PE04RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE04TP[3:0] PE04TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 4. PE05RP[3:0] PE05RN[3:0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. PE05TP[3:0] PE05TN[3:0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. PE06RP[3:0] PE06RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE06TP[3:0] PE06TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 6. Table 2 PCI Express Interface Pins (Part 1 of 2)

6 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PE07RP[3:0] PE07RN[3:0] I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. PE07TP[3:0] PE07TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. PE08RP[3:0] PE08RN[3:0] I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for port 8. PE08TP[3:0] PE08TN[3:0] O PCI Express Port 8 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 8. PE09RP[3:0] PE09RN[3:0] I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs for lanes 4 through 7. PE09TP[3:0] PE09TN[3:0] O PCI Express Port 9 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs for lanes 4 through 7. PE10RP[3:0] PE10RN[3:0] I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for port 10. PE10TP[3:0] PE10TN[3:0] O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs for port 10. PE11RP[3:0] PE11RN[3:0] I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for port 11. When port 10 is merged with port 11, these sig- nals become port 10 receive pairs for lanes 4 through 7. PE11TP[3:0] PE11TN[3:0] O PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs for port 11. When port 10 is merged with port 11, these sig- nals become port 10 transmit pairs for lanes 4 through 7. Signal Type Name/Description GCLKN[1:0] GCLKP[1:0] I Global Reference Clock. Differential reference clock input pair. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic. The frequency of the differential reference clock is determined by the GCLKFSEL signal. P[11:0]CLKN P[11:0]CLKP I Port [11:0] Reference Clocks. Differential reference clock pairs associated with ports. Table 3 Reference Clock Pins Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. Table 4 SMBus Interface Pins (Part 1 of 2) Signal Type Name/Description Table 2 PCI Express Interface Pins (Part 2 of 2)

7 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PART0PERSTN Alternate function pin type: Input/Output Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PART1PERSTN Alternate function pin type: Input/Output Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PART2PERSTN Alternate function pin type: Input/Output Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PART3PERSTN Alternate function pin type: Input/Output Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition. GPIO[4] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function — Reserved 2nd Alternate function pin name: P0LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 0 Link Up Status output. GPIO[5] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: GPEN 1st Alternate function pin type: Output 1st Alternate function: Hot-plug general purpose even output. 2nd Alternate function pin name: P0ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 0 Link Active Status Output. GPIO[6] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 5 General Purpose I/O Pins (Part 1 of 7) Signal Type Name/Description Table 4 SMBus Interface Pins (Part 2 of 2)

8 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO[8] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN Alternate function pin type: Input Alternate function: IO expander interrupt. GPIO[9] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0APN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 0 Attention Push Button Input. GPIO[10] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0PDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 0 Presence Detect Input. GPIO[11] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0PFN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 0 Power Fault Input. GPIO[12] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0PWRGDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 0 Power Good Input. GPIO[13] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0MRLN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 0 Manually Operated Retention latch Input. GPIO[14] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0AIN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 0 Attention Indicator Output. GPIO[15] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0PIN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 0 Power Indicator Output. GPIO[16] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0PEP Alternate function pin type: Output Alternate function: Hot Plug Signal Group 0 Power Enable Output. GPIO[17] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP0RSTN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 0 Reset Output. Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 2 of 7)

9 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO[18] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP1APN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 1 Attention Push Button Input. GPIO[19] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP1PDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 1 Presence Detect Input. GPIO[20] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP1PFN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 1 Power Fault Input. GPIO[21] I General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP1PWRGDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 1 Power Good Input. GPIO[22] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP1MRLN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 1 Manually Operated Reten- tion. 2nd Alternate function pin name: P1LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 1 Link Up Status Output. GPIO[23] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP1AIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 1 Attention Indicator Output. 2nd Alternate function pin name: P1ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 1 Link Active Status Output. GPIO[24] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP1PIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 1 Power Indicator Output. 2nd Alternate function pin name: P2LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 2 Link Up Status Output. GPIO[25] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP1PEP 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 1 Power Enable Output. 2nd Alternate function pin name: P2ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 2 Link Active Status Output. Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 3 of 7)

10 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO[26] O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP1RSTN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 1 Reset Output. 2nd Alternate function pin name: P3LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 3 Link Up Status Output. GPIO[27] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2APN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 2 Attention Push Button Input. 2nd Alternate function pin name: P3ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 3 Link Active Status Output. GPIO[28] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2PDN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 2 Presence Detect Input. 2nd Alternate function pin name: P4LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 4 Link Up Status Output. GPIO[29] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2PFN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 2 Power Fault Input. 2nd Alternate function pin name: P4ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 4 Link Active Status Output. GPIO[30] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2PWRGDN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 2 Power Good Input. 2nd Alternate function pin name: P5LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 5 Link Up Status Output. GPIO[31] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2MRLN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 2 Manually Operated Reten- tion Latch Input. 2nd Alternate function pin name: P5ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 5 Link Active Status Output. Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 4 of 7)

11 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO[32] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2AIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 2 Attention Indicator Output. 2nd Alternate function pin name: P6LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 6 Link Up Status Output. GPIO[33] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2PIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 2 Power Indicator Output. 2nd Alternate function pin name: P6ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 6 Link Active Status Output. GPIO[34] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2PEP 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 2 Power Enable Output. 2nd Alternate function pin name: P7LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 7 Link Up Status Output. GPIO[35] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP2RSTN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 2 Reset Output. 2nd Alternate function pin name: P7ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 7 Link Active Status Output. GPIO[36] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3APN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 3 Attention Push Button Input. 2nd Alternate function pin name: P8LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 8 Link Up Status Output. GPIO[37] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3PDN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 3 Presence Detect Input. 2nd Alternate function pin name: P8ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 8 Link Active Status Output. GPIO[38] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3PFN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 3 Power Fault Input. 2nd Alternate function pin name: P9LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 9 Link Up Status Output. Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 5 of 7)

12 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO[39] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3PWRGDN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 3 Power Good Input. 2nd Alternate function pin name: P9ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 9 Link Active Status Output. GPIO[40] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3MRLN 1st Alternate function pin type: Input 1st Alternate function: Hot Plug Signal Group 3 Manually Operated Reten- tion Latch Input. 2nd Alternate function pin name: P10LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 10 Link Up Status Output. GPIO[41] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3AIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 3 Attention Indicator Output. 2nd Alternate function pin name: P10ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 10 Link Active Status Output. GPIO[42] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3PIN 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 3 Power Indicator Output. 2nd Alternate function pin name: P11LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 11 Link Up Status Output. GPIO[43] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: HP3PEP 1st Alternate function pin type: Output 1st Alternate function: Hot Plug Signal Group 3 Power Enable Output. 2nd Alternate function pin name: P11ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 11 Link Active Status Output. GPIO[44] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP3RSTN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 3 Reset Output. GPIO[45] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4APN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 4 Attention Push Button Input. GPIO[46] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4PDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 4 Presence Detect Input. Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 6 of 7)

13 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO[47] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4PFN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 4 Power Fault Input. GPIO[48] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4PWRGDN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 4 Power Good Input. GPIO[49] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4MRLN Alternate function pin type: Input Alternate function: Hot Plug Signal Group 4 Manually Operated Retention Latch Input. GPIO[50] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4AIN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 4 Attention Indicator Output. GPIO[51] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4PIN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 4 Power Indicator Output. GPIO[52] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4PEP Alternate function pin type: Output Alternate function: Hot Plug Signal Group 4 Power Enable Output. GPIO[53] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: HP4RSTN Alternate function pin type: Output Alternate function: Hot Plug Signal Group 4 Reset Output. Signal Type Name/Description CLKMODE[2:0] Clock Mode. These signals determine the port clocking mode used by ports of the device. GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of the GCLKP and GCLKN signals. 0x0 100 MHz 0x1 125 MHz MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Table 6 System Pins (Part 1 of 3) Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 7 of 7)

14 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each operates as a single x4 port. P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 2 is merged with port 3 to form a single x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7 of port 2. When this pin is high, port 2 and port 3 are not merged, and each operates as a single x4 port. P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4. When this pin is high, port 4 and port 5 are not merged, and each operates as a single x4 port. P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 6 is merged with port 7 to form a single x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7 of port 6. When this pin is high, port 6 and port 7 are not merged, and each operates as a single x4 port. P89MERGEN I Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 8 is merged with port 9 to form a single x8 port. The Serdes lanes associated with port 9 become lanes 4 through 7 of port 8. When this pin is high, port 8 and port 9 are not merged, and each operates as a single x4 port. P1011MERGEN I Port 10 and 11 Merge. P1011MERGEN is an active low signal. It is pulled low internally. When this pin is low, port 10 is merged with port 11 to form a single x8 port. The Serdes lanes associated with port 11 become lanes 4 through 7 of port 10. When this pin is high, port 10 and port 11 are not merged, and each operates as a single x4 port. Signal Type Name/Description Table 6 System Pins (Part 2 of 3)

15 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PERSTN I Global Reset. Assertion of this signal resets all logic inside PES48H12AG2. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES48H12AG2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES48H12AG2 switch operating mode. Note: These pins should be static and not change following the negation of PERSTN. 0x0 - Single partition 0x1 - Single partition with Serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - Single partition with port 0 selected as the upstream port (port 2 dis- abled) 0x9 - Single partition with port 2 selected as the upstream port (port 0 dis- abled) 0xA - Single partition with Serial EEPROM initialization and port 0 selected as the upstream port (port 2 disabled) 0xB - Single partition with Serial EEPROM initialization and port 2 selected as the upstream port (port 0 disabled) 0xC - Multi-partition 0xD - Multi-partition with Serial EEPROM initialization 0xE - Reserved 0xF - Reserved Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 7 Test Pins Signal Type Name/Description Table 6 System Pins (Part 3 of 3)

16 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Signal Type Name/Description REFRES00 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES01 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES02 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES03 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES04 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES05 I/O Port 5 External Reference Resistor. Provides a reference for the Port 5 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES06 I/O Port 6 External Reference Resistor. Provides a reference for the Port 6 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES07 I/O Port 7 External Reference Resistor. Provides a reference for the Port 7 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES08 I/O Port 8 External Reference Resistor. Provides a reference for the Port 8 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES09 I/O Port 9 External Reference Resistor. Provides a reference for the Port 9 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES10 I/O Port 10 External Reference Resistor. Provides a reference for the Port 10 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES11 I/O Port 11 External Reference Resistor. Provides a reference for the Port 11 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRESPLL I/O PLL External Reference Resistor. Provides a reference for the PLL bias currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be connected from this pin to ground. VDDCORE I Core VDD. Power supply for core logic (1.0V). VDDI/O I I/O VDD. LVTTL I/O buffer power supply (2.5V or preferred 3.3V). VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V). Table 8 Power, Ground, and SerDes Resistor Pins (Part 1 of 2)

17 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS I Ground. Signal Type Name/Description Table 8 Power, Ground, and SerDes Resistor Pins (Part 2 of 2)

18 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any of these pins left floating can cause a slight increase in power consumption. Finally, unused Serdes (Rx and Tx) pins should be left floating. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Interface PE00RN[3:0] I PCIe differential2 Serial Link PE00RP[3:0] I PE00TN[3:0] O PE00TP[3:0] O PE01RN[3:0] I PE01RP[3:0] I PE01TN[3:0] O PE01TP[3:0] O PE02RN[3:0] I PE02RP[3:0] I PE02TN[3:0] O PE02TP[3:0] O PE03RN[3:0] I PE03RP[3:0] I PE03TN[3:0] O PE03TP[3:0] O PE04RN[3:0] I PE04RP[3:0] I PE04TN[3:0] O PE04TP[3:0] O PE05RN[3:0] I PE05RP[3:0] I PE05TN[3:0] O PE05TP[3:0] O PE06RN[3:0] I PE06RP[3:0] I PE06TN[3:0] O PE06TP[3:0] O PE07RN[3:0] I PE07RP[3:0] I PE07TN[3:0] O PE07TP[3:0] O PE08RN[3:0] I PE08RP[3:0] I PE08TN[3:0] O Table 9 Pin Characteristics (Part 1 of 3)

19 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PCI Express Interface (Cont.) PE08TP[3:0] O PCIe differential Serial Link PE09RN[3:0] I PE09RP[3:0] I PE09TN[3:0] O PE09TP[3:0] O PE10RN[3:0] I PE10RP[3:0] I PE10TN[3:0] O PE10TP[3:0] O PE11RN[3:0] I PE11RP[3:0] I PE11TN[3:0] O PE11TP[3:0] O GCLKN[1:0] I HCSL Diff. Clock Input Refer to Table 10 GCLKP[1:0] I P[11:0]CLKN I P[11:0]CLKP I SMBus MSMBADDR[4:1] I LVTTL Input pull-down MSMBCLK I/O STI 3 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[53:0] I/O LVTTL STI, High Drive pull-up System Pins CLKMODE[1:0] I LVTTL Input pull-up CLKMODE[2] I pull-down GCLKFSEL I pull-down MSMBSMODE I pull-down P01MERGEN I pull-down P23MERGEN I pull-down P45MERGEN I pull-down P67MERGEN I pull-down P89MERGEN I pull-down P1011MERGEN I pull-down PERSTN I STI RSTHALT I Input pull-down SWMODE[3:0] I pull-down Function Pin Name Type Buffer I/O Type Internal Resistor

1 Notes

Table 9 Pin Characteristics (Part 2 of 3)

20 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up SerDes Reference Resistors REFRES00 I/O Analog REFRES01 I/O REFRES02 I/O REFRES03 I/O REFRES04 I/O REFRES05 I/O REFRES06 I/O REFRES07 I/O REFRES08 I/O REFRES09 I/O REFRES10 I/O REFRES11 I/O REFRESPLL I/O 1. Internal resistor values under typical operating conditions are 92K  for pull-up and 91K for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. 3. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 9 Pin Characteristics (Part 3 of 3)

21 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Logic Diagram — PES48H12AG2 Figure 4 PES48H12AG2 Logic Diagram PE00TP[3:0] Global Reference Clocks GCLKN[1:0] GCLKP[1:0] JTAG_TCK GPIO[53:0]

54 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface GCLKFSEL RSTHALT System Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[3:0] CLKMODE[2:0] PERSTN MSMBSMODE PE00RP[3:0] PE00RN[3:0] PCI Express Switch SerDes Input PE00TN3:[0] PCI Express Switch SerDes Output Port 0 Port 0 PE01RP[3:0] PE01RN[3:0] PCI Express Switch SerDes Input PE01TP[3:0] PE01TN[3:0] PCI Express Switch SerDes Output Port 1 Port 1 PE11RP[3:0] PE11RN[3:0] PCI Express Switch SerDes Input PE11TP[3:0] PE11TN[3:0] PCI Express Switch SerDes OutputPort 11 Port 11 PES48H12AG2 REFRES[11:0] SerDes Reference Resistors VDDPEHA VDDPETA P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN REFRESPLL P00CLKP P00CLKN P01CLKP P01CLKN P11CLKP P11CLKN

22 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 14 and 15. AC Timing Characteristics Parameter Description Condition Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal GCLKFSEL. MHz TC-RISE Rising edge rate Differential 0.6 4 V/ns TC-FALL Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 mV VIL Differential input low voltage Differential -150 mV voltage Single-ended +250 +550 mV VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended +140 mV VRB Ring back voltage margin Differential -100 +100 mV TSTABLE Time before VRB is allowed Differential 500 ps TPERIOD-AVG Average clock period accuracy -300 2800 ppm trum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps Duty Cycle Duty cycle 40 60 % Rise/Fall Matching Single ended rising Refclk edge rate ver- sus falling Refclk edge rate 20 % Z C-DC Clock source output DC impedance 40 60  Table 10 Input Clock Requirements Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 PCIe Transmit UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps T TX-EYE Minimum Tx Eye Width 0.75 0.75 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.125 UI TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI TTX- IDLE-MIN Minimum time in idle 20 20 UI Table 11 PCIe AC Timing Characteristics (Part 1 of 2)

23 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 88 n s TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 8 8 ns TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI PCIe Receive UI Unit Interval 399.88 400 400.12 199.94 200.06 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-SKEW Lane to lane input skew 20 8 ns TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[53:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 12 GPIO AC Timing Characteristics Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 Table 11 PCIe AC Timing Characteristics (Part 2 of 2)

24 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 13 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

25 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Recommended Operating Supply Voltages Power-Up/Power-Down Sequence During power supply ramp-up, V DDCORE must remain at least 1.0V below V DDI/O at all times. There are no other power-up sequence require- ments for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes 2.25 2.5 2.75 V 3.125 3.3 3.465 V VDDPEA1 1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. PCI Express Analog Power 0.95 1.0 1.1 V VDDPEHA2 2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA1 PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 14 PES48H12AG2 Operating Voltages Grade Temperature Commercial 0 C to +70C Ambient Industrial -40 C to +85C Ambient Table 15 PES48H12AG2 Operating Temperatures

26 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Power Consumption Typical power is measured under the followi ng conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages def ined in Table 14 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14 (and also listed below). Note 1: I/O supply of 3.3V is preferred. Note 2: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in VDDPEA, VDDPEHA, and VDDPETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned- off port is close to zero. For example, if 2 ports out of 12 are turned off, then the power savings for each of the above three power rails can be calculated quite simply as 2/12 multiplied by the power consumption indicated in the above table. Note 3: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: VDDPEA, VDDPEHA, and VDDPETA. Number of Active Lanes per Port Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ Power Max Power 8/8/8/8/8/8 (Full Swing) mA 3360 5529 2313 2705 816 825 845 898 24 29 8/8/8/8/8/8 (Half Swing) mA 3360 5529 1989 2327 816 825 439 467 24 29 Table 16 PES48H12AG2 Power Consumption — 2.5V I/O Number of Active Lanes per Port Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.1V Typ 3.3V Max 3.465V Typ Power Max Power 8/8/8/8/8/8 (Full Swing) mA 3360 5529 2313 2705 816 825 845 898 30 35 8/8/8/8/8/8 (Half Swing) mA 3360 5529 1989 2327 816 825 439 467 30 35 Table 17 PES48H12AG2 Power Consumption — 3.3V I/O

27 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Thermal Considerations This section describes t hermal considerations for the PES48H12AG2 (35mm2 FCBGA1156 package). The data in Table 18 below contains infor- mation that is relevant to the thermal performance of the PES48H12AG2 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 18. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be main- tained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 18), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products 85 oC Maximum for industrial-rated products JA(effective) Effective Thermal Resistance, Junction-to-Ambient 13.0 oC/W Zero air flow 6.8 oC/W 1 m/S air flow 5.8 oC/W 2 m/S air flow JB Thermal Resistance, Junction-to-Board 2.5 oC/W JC Thermal Resistance, Junction-to-Case 0.15 oC/W P Power Dissipation of the Device 12.44 Watts Maximum Table 18 Thermal Specifications for PES48H12AG2, 35x35 mm FCBGA1156 Package

28 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Values based on systems running at recommended supply voltages, as shown in Table 14. Note: See Table 9, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- 3.5dB De-emphasized differential output voltage VTX-DE-RATIO- 6.0dB De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC-active- idle-delta Abs delta of DC common mode voltage between L0 and idle 100 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 66 d B ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120  VTX-CM-ACpp Peak-Peak AC Common NA 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 0 3.6 0 3.6 V VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detec- tion 600 600 mV I TX-SHORT Transmitter Short Circuit Current Limit 09 0 9 0 m A Table 19 DC Electrical Characteristics (Part 1 of 2)

29 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Serial Link (cont.) PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to- peak) 175 1200 120 1200 mV RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz 8 1.25 - 2.5GHz RLRX-CM Receiver Common Mode Return Loss 66 d B ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec  ZRX--DC DC common mode impedance 40 50 60 40 60  ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 50k  ZRX-HIGH-IMP-DC- POS DC input CM input impedance for V>0 during reset or power down 50k 50k  ZRX-HIGH-IMP-DC- NEG DC input CM input impedance for V<0 during reset or power down 1.0k 1.0k  VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 65 175 mV VRX-CM-ACp Receiver AC common-mode peak voltage 150 150 mV V RX-CM-ACp PCIe REFCLK CIN Input Capacitance 1.5 — 1.5 — pF Other I/Os LOW Drive Output I OL —2 . 5— —2 . 5 — m A V OL = 0.4v IOH —- 5 . 5— —- 5 . 5 — m A V OH = 1.5V High Drive Output IOL — 12.0 — — 12.0 — mA V OL = 0.4v Schmitt Trig- ger Input (STI) VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Input V IL -0.3 — 0.8 -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Capacitance C IN —— 8 . 5 ——8 . 5p F — Leakage Inputs — — + 10 — — + 10 AV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 — — + 10 AV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 — — + 80 AV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 19 DC Electrical Characteristics (Part 2 of 2)

30 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Absolute Maximum Voltage Rating Warning: For proper and reliable operation in adherence with this datas heet, the device should not exceed the recommended operating volt ages in Table 14. The absolute maximum operating voltages in Table 20 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability. SMBus Characterization Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Table 20 PES48H12AG2 Absolute Maximum Voltage Rating Symbol Parameter SMBus 2.0 Char. Data1 1. Data at room and hot temperature. Unit 3V 3.3V 3.6V DC Parameter for SDA Pin VIL Input Low 1.16 1.26 1.35 V VIH Input High 1.56 1.67 1.78 V VOL@350uA Output Low 15 15 15 mV IOL@0.4V 23 24 25 mA IPullup Current Source — — — A IIL_Leak Input Low Leakage 0 0 0 A IIH_Leak Input High Leakage 0 0 0 A DC Parameter for SCL Pin VIL (V) Input Low 1.11 1.2 1.31 V VIH (V) Input High 1.54 1.65 1.76 V IIL_Leak Input Low Leakage 0 0 0 A IIH_Leak Input High Leakage 0 0 0 A Table 21 SMBus DC Characterization Data

31 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Symbol Parameter SMBus @3.3V ±10%1 1. Data at room and hot temperature. Unit Min Max FSCL Clock frequency 5 600 KHz TBUF Bus free time between Stop and Start 3.5 — s THD:STA Start condition hold time 1 — s TSU:STA Start condition setup time 1 — s TSU:STO Stop condition setup time 1 — s THD:DAT Data hold time 1 — ns TSU:DAT Data setup time 1 — ns TTIMEOUT Detect clock low time out — 74.7 ms TLOW Clock low period 3.7 — s THIGH Clock high period 3.7 — s TF Clock/Data fall time — 72.2 ns TR Clock/Data rise time — 68.3 ns TPOR@10kHz Time which a device must be operational after power-on reset 20 — ms Table 22 SMBus AC Timing Data

32 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet The following table lists the pin numbers and signal names for the PES48H12AG2 35x35mm device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B1 V SS C1 GPIO_29 2 D1 GPIO_28 2 A2 V SS B2 V DDI/O C2 GPIO_27 2 D2 GPIO_26 2 A3 GPIO_19 1 B3 GPIO_18 1 C3 GPIO_21 1 D3 V DDI/O A4 V DDI/O B4 GPIO_17 1 C4 GPIO_16 1 D4 GPIO_23 2 A5 V SS B5 V SS C5 V SS D5 V SS A6 PE09TP3 B6 PE09TN3 C6 V SS D6 PE09RN3 A7 PE09TP2 B7 PE09TN2 C7 V SS D7 PE09RN2 A8 V SS B8 V SS C8 V SS D8 V SS A9 PE09TP1 B9 PE09TN1 C9 V SS D9 PE09RN1 A10 PE09TP0 B10 PE09TN0 C10 V SS D10 PE09RN0 A11 V SS B11 V SS C11 V SS D11 V SS A12 PE08TP3 B12 PE08TN3 C12 V SS D12 PE08RN3 A13 PE08TP2 B13 PE08TN2 C13 V SS D13 PE08RN2 A14 V SS B14 V SS C14 V SS D14 V SS A15 PE08TP1 B15 PE08TN1 C15 V SS D15 PE08RN1 A16 PE08TP0 B16 PE08TN0 C16 V SS D16 PE08RN0 A17 V SS B17 V SS C17 V SS D17 V SS A18 PE03TP3 B18 PE03TN3 C18 V SS D18 PE03RN3 A19 PE03TP2 B19 PE03TN2 C19 V SS D19 PE03RN2 A20 V SS B20 V SS C20 V SS D20 V SS A21 PE03TP1 B21 PE03TN1 C21 V SS D21 PE03RN1 A22 PE03TP0 B22 PE03TN0 C22 V SS D22 PE03RN0 A23 V SS B23 V SS C23 V SS D23 V SS A24 PE02TP3 B24 PE02TN3 C24 V SS D24 PE02RN3 A25 PE02TP2 B25 PE02TN2 C25 V SS D25 PE02RN2 A26 V SS B26 V SS C26 V SS D26 V SS A27 PE02TP1 B27 PE02TN1 C27 V SS D27 PE02RN1 A28 PE02TP0 B28 PE02TN0 C28 V SS D28 PE02RN0 A29 V SS B29 V SS C29 V SS D29 V SS A30 V DDI/O B30 MSMBADDR3 C30 MSMBADDR4 D30 JTAG_TMS A31 MSMBADDR1 B31 MSMBADDR2 C31 JTAG_TDI D31 V DDI/O A32 MSMBSMODE B32 PERSTN C32 JTAG_TRST_N D32 SSMBADDR5 A33 V SS B33 V DDI/O C33 SSMBADDR2 D33 SSMBADDR3 A34 V SS B34 V SS C34 SSMBADDR1 D34 V DDI/O Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 1 of 9)

33 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet E1 V DDI/O F1 V SS G1 PE10TP0 H1 PE10TP1 E2 GPIO_30 2 F2 V SS G2 PE10TN0 H2 PE10TN1 E3 GPIO_31 2 F3 V SS G3 V SS H3 V SS E4 GPIO_24 2 F4 V SS G4 PE10RN0 H4 PE10RN1 E5 V SS F5 V SS G5 PE10RP0 H5 PE10RP1 E6 PE09RP3 F6 V SS G6 V SS H6 V SS E7 PE09RP2 F7 V SS G7 GPIO_46 1 H7 GPIO_48 1 E8 V SS F8 V SS G8 GPIO_45 1 H8 GPIO_20 1 E9 PE09RP1 F9 V SS G9 V SS H9 V DDI/O E10 PE09RP0 F10 REFRES09 G10 V SS H10 GPIO_47 1 E11 V SS F11 P09CLKP G11 P09CLKN H11 V SS E12 PE08RP3 F12 V SS G12 NC H12 V SS E13 PE08RP2 F13 V SS G13 V SS H13 V DDPEHA E14 V SS F14 P08CLKP G14 P08CLKN H14 V SS E15 PE08RP1 F15 V SS G15 NC H15 V DDPETA E16 PE08RP0 F16 V SS G16 V SS H16 V SS E17 V SS F17 REFRESPLL G17 GCLKN0 H17 V SS E18 PE03RP3 F18 V SS G18 GCLKP0 H18 V SS E19 PE03RP2 F19 REFRES03 G19 NC H19 V SS E20 V SS F20 P03CLKP G20 P03CLKN H20 V DDPETA E21 PE03RP1 F21 V SS G21 V SS H21 REFRES02 E22 PE03RP0 F22 V SS G22 NC H22 V DDPEHA E23 V SS F23 P02CLKP G23 P02CLKN H23 V SS E24 PE02RP3 F24 V SS G24 V SS H24 V SS E25 PE02RP2 F25 V SS G25 V SS H25 V SS E26 V SS F26 V SS G26 GPIO_33 2 H26 MSMBDAT E27 PE02RP1 F27 V SS G27 MSMBCLK H27 V DDI/O E28 PE02RP0 F28 V SS G28 GPIO_32 2 H28 SSMBCLK E29 V SS F29 V SS G29 V SS H29 V SS E30 V SS F30 PE01RP3 G30 PE01RP2 H30 V SS E31 V SS F31 PE01RN3 G31 PE01RN2 H31 V SS E32 V SS F32 V SS G32 V SS H32 V SS E33 V SS F33 PE01TN3 G33 PE01TN2 H33 V SS E34 V SS F34 PE01TP3 G34 PE01TP2 H34 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 2 of 9)

34 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet J1 V SS K1 PE10TP2 L1 PE10TP3 M1 V SS J2 V SS K2 PE10TN2 L2 PE10TN3 M2 V SS J3 V SS K3 V SS L3 V SS M3 V SS J4 V SS K4 PE10RN2 L4 PE10RN3 M4 V SS J5 V SS K5 PE10RP2 L5 PE10RP3 M5 V SS J6 GPIO_50 1 K6 V SS L6 V SS M6 V SS J7 GPIO_51 1 K7 GPIO_53 1 L7 V SS M7 V SS J8 V SS K8 GPIO_52 1 L8 V SS M8 V SS J9 GPIO_25 2 K9 V DDI/O L9 V SS M9 V SS J10 GPIO_49 1 K10 GPIO_22 2 L10 V SS M10 V SS J11 V SS K11 V SS L11 V SS M11 V SS J12 V SS K12 V SS L12 V SS M12 V SS J13 V SS K13 V DDPEHA L13 V DDPEA M13 V DDPEA J14 V DDPEA K14 V SS L14 V DDPEA M14 V SS J15 REFRES08 K15 V DDPETA L15 V DDPEA M15 V DDPEA J16 V SS K16 V SS L16 V SS M16 V SS J17 V DDPEHA K17 V DDPEHA L17 V DDPEA M17 V DDPEA J18 V DDPEHA K18 V DDPEHA L18 V DDPEA M18 V DDPEA J19 V SS K19 V SS L19 V SS M19 V SS J20 V SS K20 V DDPETA L20 V DDPEA M20 V DDPEA J21 V DDPEA K21 V SS L21 V DDPEA M21 V SS J22 V SS K22 V DDPEHA L22 V DDPEA M22 V DDPEA J23 V SS K23 V SS L23 V SS M23 V SS J24 V SS K24 V SS L24 V SS M24 V SS J25 JTAG_TDO K25 CLKMODE1 L25 V SS M25 V SS J26 V DDI/O K26 JTAG_TCK L26 V SS M26 V SS J27 SSMBDAT K27 GPIO_36 2 L27 V SS M27 V SS J28 GPIO_34 2 K28 GPIO_35 2 L28 V SS M28 REFRES01 J29 V SS K29 V SS L29 V SS M29 V SS J30 PE01RP1 K30 PE01RP0 L30 V SS M30 PE00RP3 J31 PE01RN1 K31 PE01RN0 L31 V SS M31 PE00RN3 J32 V SS K32 V SS L32 V SS M32 V SS J33 PE01TN1 K33 PE01TN0 L33 V SS M33 PE00TN3 J34 PE01TP1 K34 PE01TP0 L34 V SS M34 PE00TP3 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 3 of 9)

35 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet N1 PE11TP0 P1 PE11TP1 R1 V SS T1 PE11TP2 N2 PE11TN0 P2 PE11TN1 R2 V SS T2 PE11TN2 N3 V SS P3 V SS R3 V SS T3 V SS N4 PE11RN0 P4 PE11RN1 R4 V SS T4 PE11RN2 N5 PE11RP0 P5 PE11RP1 R5 V SS T5 PE11RP2 N6 V SS P6 V SS R6 V SS T6 NC N7 NC P7 P10CLKP R7 REFRES10 T7 P11CLKP N8 V DDPEHA P8 P10CLKN R8 V DDPETA T8 P11CLKN N9 V SS P9 V DDPEA R9 V SS T9 REFRES11 N10 V DDPEHA P10 V SS R10 V DDPETA T10 V SS N11 V DDPEA P11 V DDPEA R11 V DDPEA T11 V SS N12 V DDPEA P12 V SS R12 V DDPEA T12 V SS N13 V DDCORE P13 V DDCORE R13 V DDCORE T13 V SS N14 V DDCORE P14 V SS R14 V DDCORE T14 V SS N15 V DDCORE P15 V DDCORE R15 V SS T15 V DDCORE N16 V SS P16 V SS R16 V DDCORE T16 V SS N17 V DDCORE P17 V DDCORE R17 V SS T17 V DDCORE N18 V SS P18 V SS R18 V DDCORE T18 V SS N19 V DDCORE P19 V DDCORE R19 V SS T19 V DDCORE N20 V DDCORE P20 V SS R20 V DDCORE T20 V SS N21 V DDCORE P21 V DDCORE R21 V SS T21 V DDCORE N22 V DDCORE P22 V DDCORE R22 V DDCORE T22 V DDCORE N23 V DDPEA P23 V SS R23 V DDPEA T23 V SS N24 V DDPEA P24 V DDPEA R24 V DDPEA T24 V SS N25 V DDPEHA P25 V SS R25 V DDPETA T25 V SS N26 V SS P26 V DDPEA R26 V SS T26 V SS N27 V DDPEHA P27 P01CLKN R27 V DDPETA T27 P00CLKN N28 NC P28 P01CLKP R28 V SS T28 P00CLKP N29 V SS P29 V SS R29 REFRES00 T29 NC N30 PE00RP2 P30 V SS R30 PE00RP1 T30 PE00RP0 N31 PE00RN2 P31 V SS R31 PE00RN1 T31 PE00RN0 N32 V SS P32 V SS R32 V SS T32 V SS N33 PE00TN2 P33 V SS R33 PE00TN1 T33 PE00TN0 N34 PE00TP2 P34 V SS R34 PE00TP1 T34 PE00TP0 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 4 of 9)

36 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet U1 PE11TP3 V1 V SS W1 PE04TP0 Y1 PE04TP1 U2 PE11TN3 V2 V SS W2 PE04TN0 Y2 PE04TN1 U3 V SS V3 V SS W3 V SS Y3 V SS U4 PE11RN3 V4 V SS W4 PE04RN0 Y4 PE04RN1 U5 PE11RP3 V5 V SS W5 PE04RP0 Y5 PE04RP1 U6 V SS V6 V SS W6 V SS Y6 NC U7 NC V7 NC W7 P04CLKP Y7 REFRES04 U8 V SS V8 V SS W8 P04CLKN Y8 V DDPETA U9 V DDPEHA V9 V DDPEHA W9 V SS Y9 V SS U10 V DDPEHA V10 V DDPEHA W10 V SS Y10 V DDPETA U11 V DDPEA V11 V DDPEA W11 V SS Y11 V DDPEA U12 V DDPEA V12 V DDPEA W12 V SS Y12 V DDPEA U13 V DDCORE V13 V SS W13 V DDCORE Y13 V DDCORE U14 V DDCORE V14 V SS W14 V DDCORE Y14 V SS U15 V SS V15 V DDCORE W15 V SS Y15 V DDCORE U16 V DDCORE V16 V SS W16 V DDCORE Y16 V SS U17 V SS V17 V DDCORE W17 V SS Y17 V DDCORE U18 V DDCORE V18 V SS W18 V DDCORE Y18 V SS U19 V SS V19 V DDCORE W19 V SS Y19 V DDCORE U20 V DDCORE V20 V SS W20 V DDCORE Y20 V SS U21 V SS V21 V DDCORE W21 V SS Y21 V DDCORE U22 V SS V22 V DDCORE W22 V SS Y22 V DDCORE U23 V DDPEA V23 V DDPEA W23 V SS Y23 V DDPEA U24 V DDPEA V24 V DDPEA W24 V SS Y24 V DDPEA U25 V DDPEHA V25 V DDPEHA W25 V SS Y25 V DDPETA U26 V DDPEHA V26 V DDPEHA W26 NC Y26 V SS U27 V SS V27 V SS W27 V SS Y27 V DDPETA U28 NC V28 NC W28 V SS Y28 V SS U29 V SS V29 V SS W29 V SS Y29 NC U30 V SS V30 NC W30 NC Y30 V SS U31 V SS V31 NC W31 NC Y31 V SS U32 V SS V32 V SS W32 V SS Y32 V SS U33 V SS V33 NC W33 NC Y33 V SS U34 V SS V34 NC W34 NC Y34 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 5 of 9)

37 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet AA1 V SS AB1 PE04TP2 AC1 PE04TP3 AD1 V SS AA2 V SS AB2 PE04TN2 AC2 PE04TN3 AD2 V SS AA3 V SS AB3 V SS AC3 V SS AD3 V SS AA4 V SS AB4 PE04RN2 AC4 PE04RN3 AD4 V SS AA5 V SS AB5 PE04RP2 AC5 PE04RP3 AD5 V SS AA6 V SS AB6 REFRES05 AC6 V SS AD6 V SS AA7 P05CLKP AB7 NC AC7 V SS AD7 V SS AA8 P05CLKN AB8 V DDPEHA AC8 V SS AD8 V SS AA9 V DDPEA AB9 V SS AC9 V SS AD9 NC AA10 V SS AB10 V DDPEHA AC10 V SS AD10 NC AA11 V DDPEA AB11 V DDPEA AC11 V SS AD11 V SS AA12 V SS AB12 V DDPEA AC12 V SS AD12 V SS AA13 V DDCORE AB13 V DDCORE AC13 V DDPEA AD13 V DDPEA AA14 V DDCORE AB14 V DDCORE AC14 V SS AD14 V DDPEA AA15 V SS AB15 V DDCORE AC15 V DDPEA AD15 V DDPEA AA16 V DDCORE AB16 V DDCORE AC16 V SS AD16 V SS AA17 V SS AB17 V SS AC17 V DDPEA AD17 V DDPEA AA18 V DDCORE AB18 V DDCORE AC18 V DDPEA AD18 V DDPEA AA19 V SS AB19 V SS AC19 V SS AD19 V SS AA20 V DDCORE AB20 V DDCORE AC20 V DDPEA AD20 V DDPEA AA21 V SS AB21 V DDCORE AC21 V SS AD21 V DDPEA AA22 V DDCORE AB22 V DDCORE AC22 V DDPEA AD22 V DDPEA AA23 V SS AB23 V DDPEA AC23 V SS AD23 V SS AA24 V DDPEA AB24 V DDPEA AC24 V SS AD24 V SS AA25 V SS AB25 V DDPEHA AC25 V SS AD25 GPIO_39 2 AA26 V DDPEA AB26 V SS AC26 V SS AD26 GPIO_38 2 AA27 V SS AB27 V DDPEHA AC27 V SS AD27 GPIO_37 2 AA28 V SS AB28 V SS AC28 V SS AD28 V SS AA29 V SS AB29 V SS AC29 V SS AD29 V SS AA30 NC AB30 NC AC30 V SS AD30 NC AA31 NC AB31 NC AC31 V SS AD31 NC AA32 V SS AB32 V SS AC32 V SS AD32 V SS AA33 NC AB33 NC AC33 V SS AD33 NC AA34 NC AB34 NC AC34 V SS AD34 NC Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 6 of 9)

38 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet AE1 PE05TP0 AF1 PE05TP1 AG1 V SS AH1 PE05TP2 AE2 PE05TN0 AF2 PE05TN1 AG2 V SS AH2 PE05TN2 AE3 V SS AF3 V SS AG3 V SS AH3 V SS AE4 PE05RN0 AF4 PE05RN1 AG4 V SS AH4 PE05RN2 AE5 PE05RP0 AF5 PE05RP1 AG5 V SS AH5 PE05RP2 AE6 V SS AF6 V SS AG6 V SS AH6 V SS AE7 V SS AF7 V SS AG7 CLKMODE0 AH7 CLKMODE2 AE8 V DDI/O AF8 V SS AG8 V DDI/O AH8 GCLKFSEL AE9 V DDI/O AF9 V DDI/O AG9 V DDI/O AH9 V SS AE10 V SS AF10 V DDI/O AG10 V SS AH10 V SS AE11 V SS AF11 V SS AG11 V SS AH11 V SS AE12 V SS AF12 V SS AG12 V SS AH12 P06CLKN AE13 V DDPEHA AF13 V SS AG13 V DDPEHA AH13 V SS AE14 V SS AF14 V DDPEA AG14 V SS AH14 REFRES06 AE15 V DDPETA AF15 V SS AG15 V DDPETA AH15 P07CLKN AE16 V SS AF16 V SS AG16 V SS AH16 NC AE17 V DDPEHA AF17 V DDPEHA AG17 V SS AH17 GCLKP1 AE18 V DDPEHA AF18 V DDPEHA AG18 V SS AH18 GCLKN1 AE19 V SS AF19 V SS AG19 V SS AH19 V SS AE20 V DDPETA AF20 V SS AG20 V DDPETA AH20 V SS AE21 V SS AF21 V DDPEA AG21 NC AH21 V SS AE22 V DDPEHA AF22 V SS AG22 V DDPEHA AH22 NC AE23 V SS AF23 V SS AG23 V SS AH23 V SS AE24 V SS AF24 V SS AG24 V SS AH24 V SS AE25 GPIO_06 AF25 GPIO_42 2 AG25 GPIO_44 1 AH25 V SS AE26 V DDI/O AF26 GPIO_09 1 AG26 V DDI/O AH26 V SS AE27 GPIO_40 2 AF27 GPIO_41 2 AG27 GPIO_04 1 AH27 V SS AE28 V SS AF28 V SS AG28 GPIO_43 2 AH28 V SS AE29 V SS AF29 V SS AG29 V SS AH29 V SS AE30 NC AF30 V SS AG30 NC AH30 NC AE31 NC AF31 V SS AG31 NC AH31 NC AE32 V SS AF32 V SS AG32 V SS AH32 V SS AE33 NC AF33 V SS AG33 NC AH33 NC AE34 NC AF34 V SS AG34 NC AH34 NC Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 7 of 9)

39 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet AJ1 PE05TP3 AK1 V SS AL1 V DDI/O AM1 P23MERGEN AJ2 PE05TN3 AK2 V SS AL2 P01MERGEN AM2 P67MERGEN AJ3 V SS AK3 V SS AL3 P45MERGEN AM3 V DDI/O AJ4 PE05RN3 AK4 V SS AL4 V DDI/O AM4 P1011MERGEN AJ5 PE05RP3 AK5 V SS AL5 P89MERGEN AM5 SWMODE3 AJ6 V SS AK6 V SS AL6 V SS AM6 V SS AJ7 V SS AK7 PE06RP0 AL7 PE06RN0 AM7 V SS AJ8 V SS AK8 PE06RP1 AL8 PE06RN1 AM8 V SS AJ9 V SS AK9 V SS AL9 V SS AM9 V SS AJ10 V SS AK10 PE06RP2 AL10 PE06RN2 AM10 V SS AJ11 V SS AK11 PE06RP3 AL11 PE06RN3 AM11 V SS AJ12 P06CLKP AK12 V SS AL12 V SS AM12 V SS AJ13 V SS AK13 PE07RP0 AL13 PE07RN0 AM13 V SS AJ14 NC AK14 PE07RP1 AL14 PE07RN1 AM14 V SS AJ15 P07CLKP AK15 V SS AL15 V SS AM15 V SS AJ16 REFRES07 AK16 PE07RP2 AL16 PE07RN2 AM16 V SS AJ17 V SS AK17 PE07RP3 AL17 PE07RN3 AM17 V SS AJ18 V SS AK18 V SS AL18 V SS AM18 V SS AJ19 V SS A K 1 9 N CA L 1 9 N CA M 1 9 V SS AJ20 V SS A K 2 0 N CA L 2 0 N CA M 2 0 V SS AJ21 V SS AK21 V SS AL21 V SS AM21 V SS AJ22 V SS A K 2 2 N CA L 2 2 N CA M 2 2 V SS AJ23 V SS A K 2 3 N CA L 2 3 N CA M 2 3 V SS AJ24 V SS AK24 V SS AL24 V SS AM24 V SS AJ25 V SS A K 2 5 N CA L 2 5 N CA M 2 5 V SS AJ26 V SS A K 2 6 N CA L 2 6 N CA M 2 6 V SS AJ27 V SS AK27 V SS AL27 V SS AM27 V SS AJ28 V SS A K 2 8 N CA L 2 8 N CA M 2 8 V SS AJ29 V SS A K 2 9 N CA L 2 9 N CA M 2 9 V SS AJ30 V SS AK30 V SS AL30 V SS AM30 V SS AJ31 V SS AK31 GPIO_08 1 AL31 GPIO_07 AM31 GPIO_00 1 AJ32 V SS AK32 GPIO_15 1 AL32 V DDI/O AM32 GPIO_05 2 AJ33 V SS AK33 GPIO_14 1 AL33 GPIO_10 1 AM33 GPIO_11 1 AJ34 V SS AK34 V DDI/O AL34 GPIO_12 1 AM34 GPIO_13 1 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 8 of 9)

40 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet AN1 V SS AN18 V SS AP1 V SS AP18 V SS AN2 V DDI/O AN19 NC AP2 V SS AP19 NC AN3 V DDI/O AN20 NC AP3 RSTHALT AP20 NC AN4 SWMODE0 AN21 V SS AP4 SWMODE1 AP21 V SS AN5 SWMODE2 AN22 NC AP5 V DDI/O AP22 NC AN6 V SS AN23 NC AP6 V SS AP23 NC AN7 PE06TN0 AN24 V SS AP7 PE06TP0 AP24 V SS AN8 PE06TN1 AN25 NC AP8 PE06TP1 AP25 NC AN9 V SS AN26 NC AP9 V SS AP26 NC AN10 PE06TN2 AN27 V SS AP10 PE06TP2 AP27 V SS AN11 PE06TN3 AN28 NC AP11 PE06TP3 AP28 NC AN12 V SS AN29 NC AP12 V SS AP29 NC AN13 PE07TN0 AN30 V SS AP13 PE07TP0 AP30 V SS AN14 PE07TN1 AN31 GPIO_01 1 AP14 PE07TP1 AP31 V DDI/O AN15 V SS AN32 GPIO_02 1 AP15 V SS AP32 GPIO_03 1 AN16 PE07TN2 AN33 V DDI/O AP16 PE07TP2 AP33 V SS AN17 PE07TN3 AN34 V SS AP17 PE07TP3 AP34 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 23 PES48H12AG2 1156-pin Signal Pin-Out (Part 9 of 9)

41 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Alternate Signal Functions Pin GPIO 1st Alternate 2nd Alternate Pin GPIO 1st Alternate 2nd Alternate AM31 GPIO_00 PART0 PERSTN — D1 GPIO_28 HP2PDN P4LINKUPN AN31 GPIO_01 PART1PERSTN — C1 GPIO_29 HP2PFN P4ACTIVEN AN32 GPIO_02 PART2PERSTN — E2 GP IO_30 HP2PWRGDN P5LINKUPN AP32 GPIO_03 PART3PERSTN E3 GPIO_31 HP2MRLN P5ACTIVEN AG27 GPIO_04 — P0LINKUPN G28 GPIO_32 HP2AIN P6LINKUPN AM32 GPIO_05 GPEN P0ACTIVEN G26 GPIO_33 HP2PIN P6ACTIVEN AK31 GPIO_08 IOEXPINTN — J28 G PIO_34 HP2PEP P7LINKUPN AF26 GPIO_09 HP0APN — K28 GP IO_35 HP2RSTN P7ACTIVEN AL33 GPIO_10 HP0PDN — K27 GPIO_36 HP3APN P8LINKUPN AM33 GPIO_11 HP0PFN — AD27 GPIO_37 HP3PDN P8ACTIVEN AL34 GPIO_12 HP0PWRGDN — AD26 GPIO_38 HP3PFN P9LINKUPN AM34 GPIO_13 HP0MRLN — AD25 G PIO_39 HP3PWRGDN P9ACTIVEN AK33 GPIO_14 HP0AIN — AE27 G PIO_40 HP3MRLN P10LINKUPN AK32 GPIO_15 HP0PIN — AF27 GPIO_41 HP3AIN P10ACTIVEN C4 GPIO_16 HP0PEP — AF25 GPIO_42 HP3PIN P11LINKUPN B4 GPIO_17 HP0RSTN — AG28 GPIO_43 HP3PEP P11ACTIVEN B3 GPIO_18 HP1APN — AG25 GPIO_44 HP3RSTN — A3 GPIO_19 HP1PDN — G8 GPIO_45 HP4APN — H8 GPIO_20 HP1PFN — G7 GPIO_46 HP4PDN — C3 GPIO_21 HP1PWRGDN — H10 GPIO_47 HP4PFN — K10 GPIO_22 HP1MRLN P1LINKUPN H7 GPIO_48 HP4PWRGDN — D4 GPIO_23 HP1AIN P1ACTIVEN J10 GPIO_49 HP4MRLN — E4 GPIO_24 HP1PIN P2LINKUPN J6 GPIO_50 HP4AIN — J9 GPIO_25 HP1PEP P2ACTIVEN J7 GPIO_51 HP4PIN — D2 GPIO_26 HP1RSTN P3LINKUPN K8 GPIO_52 HP4PEP — C2 GPIO_27 HP2APN P3ACTI VEN K7 GPIO_53 HP4RSTN — Table 24 PES48H12AG2 Alternate Signal Functions

42 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Power Pins VDDCore V DDCore V DDI/O V DDPEA V DDPEA V DDPEHA V DDPETA N13 V19 A4 J14 V11 H13 H15 N14 V21 A30 J21 V12 H22 H20 N15 V22 B2 L13 V23 J17 K15 N17 W13 B33 L14 V24 J18 K20 N19 W14 D3 L15 Y11 K13 R8 N20 W16 D31 L17 Y12 K17 R10 N21 W18 D34 L18 Y23 K18 R25 N22 W20 E1 L20 Y24 K22 R27 P13 Y13 H9 L21 AA9 N8 Y8 P15 Y15 H27 L22 AA11 N10 Y10 P17 Y17 J26 M13 AA24 N25 Y25 P19 Y19 K9 M15 AA26 N27 Y27 P21 Y21 AE8 M17 AB11 U9 AE15 P22 Y22 AE9 M18 AB12 U10 AE20 R13 AA13 AE26 M20 AB23 U25 AG15 R14 AA14 AF9 M22 AB24 U26 AG20 R16 AA16 AF10 N11 AC13 V9 R18 AA18 AG8 N12 AC15 V10 R20 AA20 AG9 N23 AC17 V25 R22 AA22 AG26 N24 AC18 V26 T15 AB13 AK34 P9 AC20 AB8 T17 AB14 AL1 P11 AC22 AB10 T19 AB15 AL4 P24 AD13 AB25 T21 AB16 AL32 P26 AD14 AB27 T22 AB18 AM3 R11 AD15 AE13 U13 AB20 AN2 R12 AD17 AE17 U14 AB21 AN3 R23 AD18 AE18 U16 AB22 AN33 R24 AD20 AE22 U18 AP5 U11 AD21 AF17 U20 AP31 U12 AD22 AF18 V15 U23 AF14 AG13 V17 U24 AF21 AG22 Table 25 PES48H12AG2 Power Pins

43 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Ground Pins VSS VSS VSS VSS VSS VSS VSS VSS A1 C16 E33 G32 J32 M1 P14 T23 A2 C17 E34 H3 K3 M2 P16 T24 A5 C18 F1 H6 K6 M3 P18 T25 A 8C 1 9F 2H 1 1 K 1 1M 4P 2 0 T 2 6 A11 C20 F3 H12 K12 M5 P23 T32 A14 C21 F4 H14 K14 M6 P25 U3 A17 C22 F5 H16 K16 M7 P29 U6 A20 C23 F6 H17 K19 M8 P30 U8 A23 C24 F7 H18 K21 M9 P31 U15 A26 C25 F8 H19 K23 M10 P32 U17 A29 C26 F9 H23 K24 M11 P33 U19 A33 C27 F12 H24 K29 M12 P34 U21 A34 C28 F13 H25 K32 M14 R1 U22 B1 C29 F15 H29 L3 M16 R2 U27 B5 D5 F16 H30 L6 M19 R3 U29 B8 D8 F18 H31 L7 M21 R4 U30 B11 D11 F21 H32 L8 M23 R5 U31 B14 D14 F22 H33 L9 M24 R6 U32 B17 D17 F24 H34 L10 M25 R9 U33 B20 D20 F25 J1 L11 M26 R15 U34 B23 D23 F26 J2 L12 M27 R17 V1 B26 D26 F27 J3 L16 M29 R19 V2 B29 D29 F28 J4 L19 M32 R21 V3 B34 E5 F29 J5 L23 N3 R26 V4 C5 E8 F32 J8 L24 N6 R28 V5 C6 E11 G3 J11 L25 N9 R32 V6 C7 E14 G6 J12 L26 N16 T3 V8 C8 E17 G9 J13 L27 N18 T10 V13 C9 E20 G10 J16 L28 N26 T11 V14 C10 E23 G13 J19 L29 N29 T12 V16 C11 E26 G16 J20 L30 N32 T13 V18 C12 E29 G21 J22 L31 P3 T14 V20 C13 E30 G24 J23 L32 P6 T16 V27 C14 E31 G25 J24 L33 P10 T18 V29 C15 E32 G29 J29 L34 P12 T20 V32 Table 26 PES48H12AG2 Ground Pins (Part 1 of 2)

44 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet W3 AA4 AC21 AE11 AG3 AJ6 AK18 AM26 W6 AA5 AC23 AE12 AG4 AJ7 AK21 AM27 W9 AA6 AC24 AE14 AG5 AJ8 AK24 AM28 W10 AA10 AC25 AE16 AG6 AJ9 AK27 AM29 W11 AA12 AC26 AE19 AG10 AJ10 AK30 AM30 W12 AA15 AC27 AE21 AG11 AJ11 AL6 AN1 W15 AA17 AC28 AE23 AG12 AJ13 AL9 AN6 W17 AA19 AC29 AE24 AG14 AJ17 AL12 AN9 W19 AA21 AC30 AE28 AG16 AJ18 AL15 AN12 W21 AA23 AC31 AE29 AG17 AJ19 AL18 AN15 W22 AA25 AC32 AE32 AG18 AJ20 AL21 AN18 W23 AA27 AC33 AF3 AG19 AJ21 AL24 AN21 W24 AA28 AC34 AF6 AG23 AJ22 AL27 AN24 W25 AA29 AD1 AF7 AG24 AJ23 AL30 AN27 W27 AA32 AD2 AF8 AG29 AJ24 AM6 AN30 W28 AB3 AD3 AF11 AG32 AJ25 AM7 AN34 W29 AB9 AD4 AF12 AH3 AJ26 AM8 AP1 W32 AB17 AD5 AF13 AH6 AJ27 AM9 AP2 Y3 AB19 AD6 AF15 AH9 AJ28 AM10 AP6 Y9 AB26 AD7 AF16 AH10 AJ29 AM11 AP9 Y14 AB28 AD8 AF19 AH11 AJ30 AM12 AP12 Y 1 6 A B 2 9A D 1 1A F 2 0A H 1 3A J 3 1A M 1 3A P 1 5 Y 1 8 A B 3 2A D 1 2A F 2 2A H 1 9A J 3 2A M 1 4A P 1 8 Y20 AC3 AD16 AF23 AH20 AJ33 AM15 AP21 Y26 AC6 AD19 AF24 AH21 AJ34 AM16 AP24 Y28 AC7 AD23 AF28 AH23 AK1 AM17 AP27 Y30 AC8 AD24 AF29 AH24 AK2 AM18 AP30 Y31 AC9 AD28 AF30 AH25 AK3 AM19 AP33 Y32 AC10 AD29 AF31 AH26 AK4 AM20 AP34 Y33 AC11 AD32 AF32 AH27 AK5 AM21 Y34 AC12 AE3 AF33 AH28 AK6 AM22 AA1 AC14 AE6 AF34 AH29 AK9 AM23 AA2 AC16 AE7 AG1 AH32 AK12 AM24 AA3 AC19 AE10 AG2 AJ3 AK15 AM25 V SS VSS VSS VSS VSS VSS VSS VSS Table 26 PES48H12AG2 Ground Pins (Part 2 of 2)

45 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet No Connection Pins Signals Listed Alphabetically NC NC NC NC NC NC G12 V34 AB33 AG33 AK28 AN26 G15 W26 AB34 AG34 AK29 AN28 G19 W30 AD9 AH16 AL19 AN29 G22 W31 AD10 AH22 AL20 AP19 N7 W33 AD30 AH30 AL22 AP20 N28 W34 AD31 AH31 AL23 AP22 T6 Y6 AD33 AH33 AL25 AP23 T29 Y29 AD34 AH34 AL26 AP25 U7 AA30 AE30 AJ14 AL28 AP26 U28 AA31 AE31 AK19 AL29 AP28 V7 AA33 AE33 AK20 AN19 AP29 V28 AA34 AE34 AK22 AN20 V30 AB7 AG21 AK23 AN22 V31 AB30 AG30 AK25 AN23 V33 AB31 AG31 AK26 AN25 Table 27 PES48H12AG2 No Connection Pins Signal Name I/O Type Location Signal Category CLKMODE0 I AG7 System CLKMODE1 I K25 CLKMODE2 I AH7 GCLKFSEL I AH8 GCLKN0 I G17 GCLKN1 I AH18 GCLKP0 I G18 GCLKP1 I AH17 GPIO_00 I/O AM31 General Purpose I/O GPIO_01 I/O AN31 GPIO_02 I/O AN32 GPIO_03 I/O AP32 GPIO_04 I/O AG27 GPIO_05 I/O AM32 Table 28 PES48H12AG2 Alphabetical Signal List (Part 1 of 10)

46 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO_06 I/O AE25 General Purpose I/O (cont.) GPIO_07 I/O AL31 GPIO_08 I/O AK31 GPIO_09 I/O AF26 GPIO_10 I/O AL33 GPIO_11 I/O AM33 GPIO_12 I/O AL34 GPIO_13 I/O AM34 GPIO_14 I/O AK33 GPIO_15 I/O AK32 GPIO_16 I/O C4 GPIO_17 I/O B4 GPIO_18 I/O B3 GPIO_19 I/O A3 GPIO_20 I/O H8 GPIO_21 I/O C3 GPIO_22 I/O K10 GPIO_23 I/O D4 GPIO_24 I/O E4 GPIO_25 I/O J9 GPIO_26 I/O D2 GPIO_27 I/O C2 GPIO_28 I/O D1 GPIO_29 I/O C1 GPIO_30 I/O E2 GPIO_31 I/O E3 GPIO_32 I/O G28 GPIO_33 I/O G26 GPIO_34 I/O J28 GPIO_35 I/O K28 GPIO_36 I/O K27 GPIO_37 I/O AD27 GPIO_38 I/O AD26 GPIO_39 I/O AD25 GPIO_40 I/O AE27 GPIO_41 I/O AF27 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 2 of 10)

47 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet GPIO_42 I/O AF25 General Purpose I/O (cont.) GPIO_43 I/O AG28 GPIO_44 I/O AG25 GPIO_45 I/O G8 GPIO_46 I/O G7 GPIO_47 I/O H10 GPIO_48 I/O H7 GPIO_49 I/O J10 GPIO_50 I/O J6 GPIO_51 I/O J7 GPIO_52 I/O K8 GPIO_53 I/O K7 JTAG_TCK I K26 Test JTAG_TDI I C31 JTAG_TDO O J25 JTAG_TMS I D30 JTAG_TRST_N I C32 MSMBADDR1 I A31 SMBus Interface MSMBADDR2 I B31 MSMBADDR3 I B30 MSMBADDR4 I C30 MSMBCLK I/O G27 MSMBDAT I/O H26 MSMBSMODE I A32 System NO CONNECT See Table 27 for a listing of No Connect pins. P00CLKN I T27 PCI Express P00CLKP I T28 P01CLKN I P27 P01CLKP I P28 P02CLKN I G23 P02CLKP I F23 P03CLKN I G20 P03CLKP I F20 P04CLKN I W8 P04CLKP I W7 P05CLKN I AA8 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 3 of 10)

48 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet P05CLKP I AA7 PCI Express (cont.) P06CLKN I AH12 P06CLKP I AJ12 P07CLKN I AH15 P07CLKP I AJ15 P08CLKN I G14 P08CLKP I F14 P09CLKN I G11 P09CLKP I F11 P10CLKN I P8 P10CLKP I P7 P11CLKN I T8 P11CLKP I T7 P01MERGEN I AL2 System P23MERGEN I AM1 P45MERGEN I AL3 P67MERGEN I AM2 P89MERGEN I AL5 P1011MERGEN I AM4 PE00RN0 I T31 PCI Express PE00RN1 I R31 PE00RN2 I N31 PE00RN3 I M31 PE00RP0 I T30 PE00RP1 I R30 PE00RP2 I N30 PE00RP3 I M30 PE00TN0 O T33 PE00TN1 O R33 PE00TN2 O N33 PE00TN3 O M33 PE00TP0 O T34 PE00TP1 O R34 PE00TP2 O N34 PE00TP3 O M34 PE01RN0 I K31 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 4 of 10)

49 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PE01RN1 I J31 PCI Express (cont.) PE01RN2 I G31 PE01RN3 I F31 PE01RP0 I K30 PE01RP1 I J30 PE01RP2 I G30 PE01RP3 I F30 PE01TN0 O K33 PE01TN1 O J33 PE01TN2 O G33 PE01TN3 O F33 PE01TP0 O K34 PE01TP1 O J34 PE01TP2 O G34 PE01TP3 O F34 PE02RN0 I D28 PE02RN1 I D27 PE02RN2 I D25 PE02RN3 I D24 PE02RP0 I E28 PE02RP1 I E27 PE02RP2 I E25 PE02RP3 I E24 PE02TN0 O B28 PE02TN1 O B27 PE02TN2 O B25 PE02TN3 O B24 PE02TP0 O A28 PE02TP1 O A27 PE02TP2 O A25 PE02TP3 O A24 PE03RN0 I D22 PE03RN1 I D21 PE03RN2 I D19 PE03RN3 I D18 PE03RP0 I E22 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 5 of 10)

50 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PE03RP1 I E21 PCI Express (cont.) PE03RP2 I E19 PE03RP3 I E18 PE03TN0 O B22 PE03TN1 O B21 PE03TN2 O B19 PE03TN3 O B18 PE03TP0 O A22 PE03TP1 O A21 PE03TP2 O A19 PE03TP3 O A18 PE04RN0 I W4 PE04RN1 I Y4 PE04RN2 I AB4 PE04RN3 I AC4 PE04RP0 I W5 PE04RP1 I Y5 PE04RP2 I AB5 PE04RP3 I AC5 PE04TN0 O W2 PE04TN1 O Y2 PE04TN2 O AB2 PE04TN3 O AC2 PE04TP0 O W1 PE04TP1 O Y1 PE04TP2 O AB1 PE04TP3 O AC1 PE05RN0 I AE4 PE05RN1 I AF4 PE05RN2 I AH4 PE05RN3 I AJ4 PE05RP0 I AE5 PE05RP1 I AF5 PE05RP2 I AH5 PE05RP3 I AJ5 PE05TN0 O AE2 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 6 of 10)

51 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PE05TN1 O AF2 PCI Express (cont.) PE05TN2 O AH2 PE05TN3 O AJ2 PE05TP0 O AE1 PE05TP1 O AF1 PE05TP2 O AH1 PE05TP3 O AJ1 PE06RN0 I AL7 PE06RN1 I AL8 PE06RN2 I AL10 PE06RN3 I AL11 PE06RP0 I AK7 PE06RP1 I AK8 PE06RP2 I AK10 PE06RP3 I AK11 PE06TN0 O AN7 PE06TN1 O AN8 PE06TN2 O AN10 PE06TN3 O AN11 PE06TP0 O AP7 PE06TP1 O AP8 PE06TP2 O AP10 PE06TP3 O AP11 PE07RN0 I AL13 PE07RN1 I AL14 PE07RN2 I AL16 PE07RN3 I AL17 PE07RP0 I AK13 PE07RP1 I AK14 PE07RP2 I AK16 PE07RP3 I AK17 PE07TN0 O AN13 PE07TN1 O AN14 PE07TN2 O AN16 PE07TN3 O AN17 PE07TP0 O AP13 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 7 of 10)

52 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PE07TP1 O AP14 PCI Express (cont.) PE07TP2 O AP16 PE07TP3 O AP17 PE08RN0 I D16 PE08RN1 I D15 PE08RN2 I D13 PE08RN3 I D12 PE08RP0 I E16 PE08RP1 I E15 PE08RP2 I E13 PE08RP3 I E12 PE08TN0 O B16 PE08TN1 O B15 PE08TN2 O B13 PE08TN3 O B12 PE08TP0 O A16 PE08TP1 O A15 PE08TP2 O A13 PE08TP3 O A12 PE09RN0 I D10 PE09RN1 I D9 PE09RN2 I D7 PE09RN3 I D6 PE09RP0 I E10 PE09RP1 I E9 PE09RP2 I E7 PE09RP3 I E6 PE09TN0 O B10 PE09TN1 O B9 PE09TN2 O B7 PE09TN3 O B6 PE09TP0 O A10 PE09TP1 O A9 PE09TP2 O A7 PE09TP3 O A6 PE10RN0 I G4 Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 8 of 10)

53 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PE10RN1 I H4 PCI Express (cont.) PE10RN2 I K4 PE10RN3 I L4 PE10RP0 I G5 PE10RP1 I H5 PE10RP2 I K5 PE10RP3 I L5 PE10TN0 O G2 PE10TN1 O H2 PE10TN2 O K2 PE10TN3 O L2 PE10TP0 O G1 PE10TP1 O H1 PE10TP2 O K1 PE10TP3 O L1 PE11RN0 I N4 PE11RN1 I P4 PE11RN2 I T4 PE11RN3 I U4 PE11RP0 I N5 PE11RP1 I P5 PE11RP2 I T5 PE11RP3 I U5 PE11TN0 O N2 PE11TN1 O P2 PE11TN2 O T2 PE11TN3 O U2 PE11TP0 O N1 PE11TP1 O P1 PE11TP2 O T1 PE11TP3 O U1 PERSTN I B32 System Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 9 of 10)

54 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet REFRES00 I/O R29 SerDes Reference Resistors REFRES01 I/O M28 REFRES02 I/O H21 REFRES03 I/O F19 REFRES04 I/O Y7 REFRES05 I/O AB6 REFRES06 I/O AH14 REFRES07 I/O AJ16 REFRES08 I/O J15 REFRES09 I/O F10 REFRES10 I/O R7 REFRES11 I/O T9 REFRESPLL I/O F17 RSTHALT I AP3 System SSMBADDR1 I C34 SMBus Interface SSMBADDR2 I C33 SSMBADDR3 I D33 SSMBADDR5 I D32 SSMBCLK I/0 H28 SSMBDAT I/O J27 SWMODE0 I AN4 System SWMODE1 I AP4 SWMODE2 I AN5 SWMODE3 I AM5 V DDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA See Table 25 for a listing of power pins. VSS See Table 26 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 28 PES48H12AG2 Alphabetical Signal List (Part 10 of 10)

55 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet PES48H12AG2 Pinout — Top View 123456 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 Vss (Ground) VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VDDPETA (Transmitter Power) VDDPEA (Analog Power) VDDPEHA (High Analog Power) Signals 27 28 29 30 31 32 33 34 AG AH AJ AK AL AM AN AP A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1 2 3 4 5 6 7 8 9 1 01 11 2 1 31 4 1 51 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X XX X X X X X X X X XX X X X No connect X X X X X X X X X X XX X X X X X X X XX X X XX X XX X X X X X X X X X XX X X X X X X X XX X X X X XX X X X X XX X X X X X X X X X XX X X X X XX X X X X X X X X X X

56 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet

57 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet Package Drawing — Page Two

58 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet

Revision History

January 21, 2010: Publication of Final datasheet. March 30, 2011: In Table 14, added VDDPETA to footnote #1. November 28, 2011: Added new Tables 21 and 22, SMBus Characterization and Timing. December 12, 2013: Removed the Alt information for AE25-GPIO_06.

59 of 59 December 12, 2013 IDT 89HPES48H12AG2 Datasheet CORPORATE HEADQUARTERS

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Ordering Information

89H48H12AG2ZBBL 1156-ball FCBGA package, Commercial Temperature 89H48H12AG2ZBBLG 1156-ball Green FCBG A package, Commercial Temperature 89H48H12AG2ZBBLI 1156-ball FCBGA package, Industrial Temperature 89H48H12AG2ZBBLGI 1156-ball Green FC BGA package, Industrial Temperature 89H48H12AG2ZCBL 1156-ball FCBGA package, Commercial Temperature 89H48H12AG2ZCBLG 1156-ball Green FCBG A package, Commercial Temperature 89H48H12AG2ZCBLI 1156-ball FCBGA package, Industrial Temperature 89H48H12AG2ZCBLGI 1156-ball Green FC BGA package, Industrial Temperature NN A NNANNA AA A Operating Voltage Product Package Temp Range H Product Family

89 Serial Switching Product

48H12A 48-lane, 12-port 1.0V +/- 0.1V Core Voltage Detail Legend A = Alpha Character N = Numeric Character AA Device Revision ZB ZB revision AN Generation Series G2 PCIe Gen 2 1156-ball FCBGA BL 1156-ball FCBGA, Green BLG Blank Commercial Temperature (0°C to +70°C Ambient) I Industrial Temperature (-40° C to +85° C Ambient) ZC ZC revision

Product Information

89HPES48H12AG2 specifications and overview.

Summary

Low latency cut-through architecture

Description

Low latency cut-through architecture

Source title 89HPES48H12AG2 Datasheet(PDF) - Integrated Device Technology

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