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Features

 High Performance Non-Blocking Switch Architecture – 32-lane, 8-port PCIe switch with flexible port configuration – Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation – Delivers up to 32 GBps (256 Gbps) of switching capacity – Supports 128 Bytes to 2 KB maximum payload size – Low latency cut-through architecture – Supports one virtual channel and eight traffic classes  Port Configurability – Eight x4 switch ports

  • Adjacent x4 ports can be merged to achieve x8 port widths – Automatic per port link width negotiation – Crosslink support – Automatic lane reversal – Per lane SerDes configuration
  • De-emphasis
  • Receive equalization
  • Drive strength  Innovative Switch Partitioning Feature – Supports up to 8 fully independent switch partitions – Logically independent switches in the same device – Configurable downstream port device numbering – Supports dynamic reconfiguration of switch partitions
  • Dynamic port reconfigurat ion — downstream, upstream, non-transparent bridge
  • Dynamic migration of ports between partitions
  • Movable upstream port within and between switch partitions  Non-Transparent Bridging (NTB) Support – Supports up to 8 NT endpoints per switch, each endpoint can communicate with other switch partitions or external PCIe domains or CPUs – 6 BARs per NT Endpoint
  • Bar address translation
  • All BARs support 32/64-bit base and limit address translation
  • Two BARs (BAR2 and BAR4) support look-up table based address translation – 32 inbound and outbound doorbell registers – 4 inbound and outbound message registers – Supports up to 64 masters – Unlimited number of outstanding transactions  Multicast – Compliant with the PCI-SIG multicast – Supports 64 multicast groups – Supports multicast across non-transparent port – Multicast overlay mechanism support – ECRC regeneration support  Integrated Direct Memory Access (DMA) Controllers – Supports up to 2 DMA upstream ports, each with 2 DMA chan- nels – Supports 32-bit and 64-bit memory-to-memory transfers
  • Fly-by translation provides reduced latency and increased performance over buffered approach
  • Supports arbitrary source and destination address alignment
  • Supports intra- as well as inter-partition data transfers using the non-transparent endpoint – Supports DMA transfers to multicast groups – Linked list descriptor-based operation – Flexible addressing modes
  • Linear addressing
  • Constant addressing  Quality of Service (QoS) – Port arbitration
  • Round robin – Request metering
  • IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput – High performance switch core architecture
  • Combined Input Output Queued (CIOQ) switch architecture with large buffers  Clocking – Supports 100 MHz and 125 MHz reference clock frequencies – Flexible port clocking modes
  • Common clock
  • Non-common clock
  • Local port clock with SSC (spread spectrum setting) and port reference clock input 89HPES32NT8BG2 Datasheet 32-Lane 8-Port PCIe® Gen2 System Interconnect Switch

IDT 89HPES32NT8BG2 Datasheet 2 of 35 December 17, 2013  Hot-Plug and Hot Swap – Hot-plug controller on all ports

  • Hot-plug supported on all downstream switch ports – All ports support hot-plug us ing low-cost external I 2C I/O expanders – Configurable presence-detect supports card and cable appli- cations – GPE output pin for hot-plug event notification
  • Enables SCI/SMI generation for legacy operating system support – Hot-swap capable I/O  Power Management – Supports D0, D3hot and D3 power management states – Active State Power Management (ASPM)
  • Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
  • Configurable L0s and L1 entry timers allow performance/ power-savings tuning – SerDes power savings
  • Supports low swing / half-swing SerDes operation
  • SerDes associated with unused ports are turned off
  • SerDes associated with unused lanes are placed in a low power state  Reliability, Availability, and Serviceability (RAS) – ECRC support – AER on all ports – SECDED ECC protection on all internal RAMs – End-to-end data path parity protection – Checksum Serial EEPROM content protected – Ability to generate an interrupt (INTx or MSI) on link up/down transitions  Initialization / Configuration – Supports Root (BIOS, OS, or driver), Serial EEPROM, or SMBus switch initialization – Common switch configurations are supported with pin strap- ping (no external components) – Supports in-system Serial EEP ROM initialization/program- ming  On-Die Temperature Sensor – Range of 0 to 127.5 degrees Celsius – Three programmable temperature thresholds with over and under temperature threshold alarms – Automatic recording of maximum high or minimum low temperature  9 General Purpose I/O  Test and Debug – Ability to inject AER errors simplifies in system error handling software validation – On-chip link activity and status outputs available for several ports – Per port link activity and status outputs available using external I2C I/O expander for all remaining ports – Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG  Standards and Compatibility – PCI Express Base Specification 2.1 compliant – Implements the following optional PCI Express features
  • Advanced Error Reporting (AER) on all ports
  • End-to-End CRC (ECRC)
  • Access Control Services (ACS)
  • Device Serial Number Enhanced Capability
  • Sub-System ID and Sub-System Vendor ID Capability
  • Internal Error Reporting
  • Multicast
  • VGA and ISA enable
  • L0s and L1 ASPM
  • ARI  Power Supplies – Requires three power supply voltages (1.0V, 2.5V, and 3.3V)  Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with 1mm ball spacing Product Description With Non-Transparent Bridging f unctionality and innovative Switch Partitioning feature, the PES32NT8BG 2 allows true multi-host or multi- processor communications in a single device. Integrated DMA control- lers enable high-performance system design by off-loading data transfer operations across memories from t he processors. Each lane is capable of 5 GT/s link speed in both directi ons and is fully compliant with PCI Express Base Specification 2.1. A non-transparent bridge (NTB) is required when two PCI Express domains need to communicate to each other. The main function of the NTB block is to initialize and translate addresses and device IDs to allow data exchange across PCI Express domains. The major function- alities of the NTB block are summarized in Table 1.

IDT 89HPES32NT8BG2 Datasheet 3 of 35 December 17, 2013 Block Diagram Figure 1 PES32NT8BG2 Block Diagram SMBus Interface The PES32NT8BG2 contains two SMBus interfaces . The slave interface provides full access to the configuration registers in the P ES32NT8BG2, allowing every configuration regi ster in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES32NT8BG2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Function Number Description NTB ports Up to 8 Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots. Mapping table entries Up to 64 for entire device Each device can have up to 64 masters ID for address and ID translations. Mapping windows Six 32-bits or three 64-bits Each NT port has six BARs, where each BAR opening an NT window to another domain. Address translation Direct-address and lookup table trans- lations Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment has independent translation programming and is associated with an entry in a look-up table. Doorbell registers 32 bits Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets a corresponding bit at the inbound doorbell in the other domain. Message registers 4 inbound and out- bound registers of 32-bits Message registers allow mailbox message passing between domains -- message placed in the inbound register will be seen at the outbound register at the other domain. Table 1 Non-Transparent Bridge Function Summary 8-Port Switch Core / 32 Gen2 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer (Port 0) (Port 2) (Port 20)(Ports 4, 6, 8, 12, 16)

IDT 89HPES32NT8BG2 Datasheet 4 of 35 December 17, 2013 Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has the SSMBADDR2 pin. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration. In the split configuration, the master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM and I/O expander slaves. Figure 2 Split SMBus Interface Configuration Hot-Plug Interface The PES32NT8BG2 supports PCI Express Hot- Plug on each downstream port. To reduce the num ber of pins required on the device, the PES32NT8BG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. F ollowing reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32NT8BG2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES32NT8BG2. In response to an I/O expander interrupt, the PES32NT8BG2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES32NT8BG2 provides 9 General Purpos e I/O (GPIO) pins that may be individua lly configured as general purpose inputs, gener al purpose outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Processor Switch SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM ... Hot-Plug I/O Expander

IDT 89HPES32NT8BG2 Datasheet 5 of 35 December 17, 2013 Pin Description The following tables list the functions of the pins provided on the PES32NT8BG2. Some of the functions listed may be multiplexe d onto the same pin. The active polarity of a signal is defined using a suff ix. Signals ending with an “N” are defined as being active, or asse rted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal ending in “N” is the negative portion of the differential pair. Note: Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc. Signal Type Name/Description PE00RN[3:0] PE00RP[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. PE00TN[3:0] PE00TP[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. PE02RN[3:0] PE02RP[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE02TN[3:0] PE02TP[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PE04RN[3:0] PE04RP[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE04TN[3:0] PE04TP[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PE06RN[3:0] PE06RP[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE06TN[3:0] PE06TP[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6. PE08RN[3:0] PE08RP[3:0] I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for port 8. PE08TN[3:0] PE08TP[3:0] O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for port 8. PE12RN[3:0] PE12RP[3:0] I PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pairs for port 12. PE12TN[3:0] PE12TP[3:0] O PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pairs for port 12. PE16RN[3:0] PE16RP[3:0] I PCI Express Port 16 Serial Data Receive. Differential PCI Express receive pairs for port 16. PE16TN[3:0] PE16TP[3:0] O PCI Express Port 16 Serial Data Transmit. Differential PCI Express transmit pairs for port 16. PE20RN[3:0] PE20RP[3:0] I PCI Express Port 20 Serial Data Receive. Differential PCI Express receive pairs for port 20. PE20TN[3:0] PE20TP[3:0] O PCI Express Port 20 Serial Data Transmit. Differential PCI Express transmit pairs for port 20. Table 2 PCI Express Interface Pins

IDT 89HPES32NT8BG2 Datasheet 6 of 35 December 17, 2013 Signal Type Name/Description GCLKN[1:0] GCLKP[1:0] I Global Reference Clock. Differential reference clock input pairs. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic. The frequency of the differential reference clock is determined by the GCLKFSEL signal. Note: Both pairs of the Global Reference Clocks must be connected to and derived from the same clock source. Refer to the Overview section of Chapter 2 in the PES32NT8xG2 User Manual for additional details. P00CLKN P00CLKP I Port Reference Clock. Differential reference clock pair associated with port 0. P02CLKN P02CLKP I Port Reference Clock. Differential reference clock pair associated with port 2. P04CLKN P04CLKP I Port Reference Clock. Differential reference clock pair associated with port 4. Table 3 Reference Clock Pins Signal Type Name/Description MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. SSMBADDR[2] I Slave SMBus Address. This pin determines the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 4 SMBus Interface Pins

IDT 89HPES32NT8BG2 Datasheet 7 of 35 December 17, 2013 Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: PART0PERSTN 1st Alternate function pin type: Input/Output 1st Alternate function: Assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd Alternate function pin name: P16LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 16 Link Up Status output. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: PART1PERSTN 1st Alternate function pin type: Input/Output 1st Alternate function: Assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd Alternate function pin name: P16ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 16 Link Active Status Output. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: PART2PERSTN 1st Alternate function pin type: Input/Output 1st Alternate function: Assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd Alternate function pin name: P4LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 4 Link Up Status output. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: PART3PERSTN 1st Alternate function pin type: Input/Output 1st Alternate function: Assertion of this signal initiated a partition funda- mental reset in the corresponding partition. 2nd Alternate function pin name: P4ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 4 Link Active Status Output. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER0 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. 2nd Alternate function pin name: P0LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 0 Link Up Status output. GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: GPEN 1st Alternate function pin type: Output 1st Alternate function: Hot-plug general purpose even output. 2nd Alternate function pin name: P0ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 0 Link Active Status Output. Table 5 General Purpose I/O Pins (Part 1 of 2)

IDT 89HPES32NT8BG2 Datasheet 8 of 35 December 17, 2013 GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER1 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. 2nd Alternate function pin name: FAILOVER3 2nd Alternate function pin type: Input 2nd Alternate function: When this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: FAILOVER2 1st Alternate function pin type: Input 1st Alternate function: When this signal changes state and the correspond- ing failover capability is enabled, a failover event is signaled. 2nd Alternate function pin name: P8LINKUPN 2nd Alternate function pin type: Output 2nd Alternate function: Port 8 Link Up Status output. GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. 1st Alternate function pin name: IOEXPINTN 1st Alternate function pin type: Input 1st Alternate function: IO expander interrupt. 2nd Alternate function pin name: P8ACTIVEN 2nd Alternate function pin type: Output 2nd Alternate function: Port 8 Link Active Status Output. Signal Type Name/Description STK0CFG0 I Stack 0 Configuration. This pin selects the configuration of stack 0. STK1CFG0 I Stack 1 Configuration. This pin selects the configuration of stack 1. STK2CFG0 I Stack 2 Configuration. This pin selects the configuration of stack 2. STK3CFG0 I Stack 3 Configuration. This pin selects the configuration of stack 3. Table 6 Stack Configuration Pins Signal Type Name/Description CLKMODE[1:0] I Clock Mode. These signals determine the port clocking mode used by ports of the device. GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of the GCLKP and GCLKN signals. 0x0 100 MHz 0x1 125 MHz Table 7 System Pins (Part 1 of 2) Signal Type Name/Description Table 5 General Purpose I/O Pins (Part 2 of 2)

IDT 89HPES32NT8BG2 Datasheet 9 of 35 December 17, 2013 PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the device. RSTHALT I Reset Halt. When this signal is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the quasi-reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the switch operating mode. These pins should be static and not change following the negation of PERSTN. 0x0 - Single partition 0x1 - Single partition with Serial EEPROM initialization 0x2 - Single partition with Serial EEPROM Jump 0 initialization 0x3 - Single partition with Serial EEPROM Jump 1 initialization 0x4 through 0x7 - Reserved 0x8 - Single partition with reduced latency 0x9 - Single partition with Serial EEPROM initialization and reduced latency 0xA - Multi-partition with Unattached ports 0xB - Multi-partition with Unattached ports and I 2C Reset 0xC - Multi-partition with Unattached ports and Serial EEPROM initialization 0xD - Multi-partition with Unattached ports with I2C Reset and Serial EEPROM initial- ization 0xE - Multi-partition with Disabled ports 0xF - Multi-partition with Disabled ports and Serial EEPROM initialization Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 8 Test Pins Signal Type Name/Description Table 7 System Pins (Part 2 of 2)

IDT 89HPES32NT8BG2 Datasheet 10 of 35 December 17, 2013 Signal Type Name/Description REFRES[7:0] — External Reference Resistor. Reference for the corresponding SerDes bias currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be connected from this pin to ground and isolated from any source of noise injection. Each bit of this signal corresponds to a SerDes quad, e.g., REFRES[5] is the reference resistor for SerDes quad 5. REFRESPLL — PLL External Reference Resistor. Provides a reference for the PLL bias currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be connected from this pin to ground and isolated from any source of noise injection. V DDCORE — Core VDD. Power supply for core logic (1.0V). VDDI/O — I/O VDD. LVTTL I/O buffer power supply (3.3V). VDDPEA — PCI Express Analog Power. Serdes analog power supply (1.0V). VDDPEHA — PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA — PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS — Ground. Table 9 Power, Ground, and SerDes Resistor Pins

IDT 89HPES32NT8BG2 Datasheet 11 of 35 December 17, 2013 Pin Characteristics Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, floating pins can cause a slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally, No Connection pins should not be connected. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Interface PE00RN[3:0] I PCIe differential2 Serial Link Note: Unused SerDes pins can be left floatingPE00RP[3:0] I PE00TN[3:0] O PE00TP[3:0] O PE02RN[3:0] I PE02RP[3:0] I PE02TN[3:0] O PE02TP[3:0] O PE04RN[3:0] I PE04RP[3:0] I PE04TN[3:0] O PE04TP[3:0] O PE06RN[3:0] I PE06RP[3:0] I PE06TN[3:0] O PE06TP[3:0] O PE08RN[3:0] I PE08RP[3:0] I PE08TN[3:0] O PE08TP[3:0] O PE12RN[3:0] I PE12RP[3:0] I PE12TN[3:0] O PE12TP[3:0] O PE16RN[3:0] I PE16RP[3:0] I PE16TN[3:0] O PE16TP[3:0] O PCI Express Interface (cont.) PE20RN[3:0] I PCIe differential Serial Link PE20RP[3:0] I PE20TN[3:0] O PE20TP[3:0] O Table 10 Pin Characteristics (Part 1 of 2)

IDT 89HPES32NT8BG2 Datasheet 12 of 35 December 17, 2013 Reference Clocks GCLKN[1:0] I HCSL Diff. Clock Input Refer to Table 11 Note: Unused port clock pins should be connected to Vss on the board. GCLKP[1:0] I P00CLKN I P00CLKP I P02CLKN I P02CLKP I P04CLKN I P04CLKP I SMBus MSMBCLK I/O LVTTL STI

3 Note: When unused, these signals must

be pulled up on the board using an external resistor or current source in accordance with the SMBus specifica- tion. MSMBDAT I/O STI SSMBADDR[2] I pull-up SSMBCLK I/O STI Note: When unused, these signals must be pulled up on the board using an external resistor or current source in accordance with the SMBus specifica- tion. SSMBDAT I/O STI General Purpose I/O GPIO[8:0] I/O LVTTL STI, High Drive pull-up Unused pins can be left floating. Stack Configuration STK0CFG0 I LVTTL Input pull-down Unused pins can be left floating.STK1CFG0 I STK2CFG0 I STK3CFG0 I System Pins CLKMODE[1:0] I LVTTL Input pull-up Unused pins can be left floating.GCLKFSEL I pull-down PERSTN I Schmitt trigger RSTHALT I pull-down Unused pins can be left floating.SWMODE[3:0] I pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up Unused pins can be left floating.JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up SerDes Reference Resis- tors REFRES[7:0] — Analog Unused pins should be connected to Vss on the board.REFRESPLL — 1. Internal resistor values under typical operating conditions are 92K  for pull-up and 91K for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. 3. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 10 Pin Characteristics (Part 2 of 2)

IDT 89HPES32NT8BG2 Datasheet 13 of 35 December 17, 2013 Logic Diagram — PES32NT8BG2 Figure 3 PES32NT8BG2 Logic Diagram JTAG_TCK GPIO[8:0]

9 General Purpose

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins P00CLKN P00CLKP PE00RP[3:0] PE00RN[3:0] PE00TP[3;0] PE00TN[3:0] PE02TP[3:0] PE02TN[3:0] PE06TP[3:0] PE06TN[3:0] PE20TP[3:0] PE20TN[3:0] PCIe Switch SerDes Output Port 20 PES32NT8BG2 PCIe Switch SerDes Input Port 0 PCIe Switch SerDes Output Port 2 PCIe Switch SerDes Output Port 0 PCIe Switch SerDes Output Port 6 Global Reference Clocks GCLKN[1:0] GCLKP[1:0] GCLKFSEL VDDCORE VDDI/O VDDPEA Power/Ground VSS VDDPEHA VDDPETA RSTHALT System Pins SWMODE[3:0] CLKMODE[1:0] PERSTN PE04TP[3:0] PE04TN[3:0] PCIe Switch SerDes Output Port 4 PE08TP[3:0] PE08TN[3:0] PCIe Switch SerDes Output Port 8 PE12TP[3:0] PE12TN[3:0] PCIe Switch SerDes Output Port 12 PE16TP[3:0] PE16TN[3:0] PCIe Switch SerDes Output Port 16 STK[3:0]CFG0 SSMBCLK SSMBDAT Slave SMBus Interface SSMBADDR[2] P02CLKN P02CLKP PE02RP[3:0] PE02RN[3:0] PCIe Switch SerDes Input Port 2 P04CLKN P04CLKP PE04RP[3:0] PE04RN[3:0] PCIe Switch SerDes Input Port 4 PE06RP[3:0] PE06RN[3:0] PCIe Switch SerDes Input Port 6 PE08RP[3:0] PE08RN[3:0] PCIe Switch SerDes Input Port 8 PE12RP[3:0] PE12RN[3:0] PCIe Switch SerDes Input Port 12 PE16RP[3:0] PE16RN[3:0] PCIe Switch SerDes Input Port 16 PE20RP[3:0] PE20RN[3:0] PCIe Switch SerDes Input Port 20 REFRES[7:0] SerDes Reference ResistorsREFRESPLL

IDT 89HPES32NT8BG2 Datasheet 14 of 35 December 17, 2013 System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 16 and 15. Note: Refclk jitter compliant to PCIe Gen2 Common Clock architecture is adequate for the GCLKN/P[x] and PE[x]CLKN/P pins of this IDT PCIe switch. This same jitter specification is applicable when interfacing the switch to another IDT switch in a Separate (Non-Common) Clock architecture. AC Timing Characteristics Parameter Description Condition Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal GCLKFSEL. MHz TC-RISE Rising edge rate Differential 0.6 4 V/ns TC-FALL Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 mV VIL Differential input low voltage Differential -150 mV voltage Single-ended +250 +550 mV VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended +140 mV VRB Ring back voltage margin Differential -100 +100 mV TSTABLE Time before VRB is allowed Differential 500 ps TPERIOD-AVG Average clock period accuracy -300 2800 ppm trum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps Duty Cycle Duty cycle 40 60 % Rise/Fall Matching Single ended rising Refclk edge rate ver- sus falling Refclk edge rate 20 % ZC-DC Clock source output DC impedance 40 60  Table 11 Input Clock Requirements Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 PCIe Transmit UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps TTX-EYE Minimum Tx Eye Width 0.75 0.75 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maxi- mum deviation from the median 0.125 UI Table 12 PCIe AC Timing Characteristics (Part 1 of 2)

IDT 89HPES32NT8BG2 Datasheet 15 of 35 December 17, 2013 Figure 4 GPIO AC Timing Waveform TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI TTX- IDLE-MIN Minimum time in idle 20 20 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 88 n s TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 8 8 ns TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI PCIe Receive UI Unit Interval 399.88 400 400.12 199.94 200.06 ps TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-SKEW Lane to lane input skew 20 8 ns TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI 1. Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[8:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns See Figure 4. Table 13 GPIO AC Timing Characteristics Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 Table 12 PCIe AC Timing Characteristics (Part 2 of 2) Tpw_13b EXTCLK GPIO (asynchronous input)

IDT 89HPES32NT8BG2 Datasheet 16 of 35 December 17, 2013 Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_T MS should be held at 1 while t he signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 14 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

IDT 89HPES32NT8BG2 Datasheet 17 of 35 December 17, 2013 Recommended Operating Temperature Recommended Operating Supply Voltages — Commercial Temperature Recommended Operating Supply Voltages — Industrial Temperature Power-Up/Power-Down Sequence During power supply ramp-up, V DDCORE must remain at least 1.0V below V DDI/O at all times. There are no other power-up sequence require- ments for the various operating supply voltages. The power-down sequence can occur in any order. Grade Temperature Commercial 0 C to +70C Ambient Industrial -40 C to +85C Ambient Table 15 PES32NT8BG2 Operating Temperatures Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes 3.125 3.3 3.465 V VDDPEA1 1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. PCI Express Analog Power 0.95 1.0 1.1 V VDDPEHA2 2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA1 PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 16 PES32NT8BG2 Operating Voltages — Commercial Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes 3.125 3.3 3.465 V VDDPEA1 1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. PCI Express Analog Power 0.95 1.0 1.05 V VDDPEHA2 2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA1 PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 17 PES32NT8BG2 Operating Voltages — Industrial Temperature

IDT 89HPES32NT8BG2 Datasheet 18 of 35 December 17, 2013 Power Consumption Typical power is measured under the follow ing conditions: 25°C Ambient, 35% total li nk usage on all ports, typical voltages def ined in Table 16 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 16 (and also listed below). Note 1: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in VDDPEA, VDDPEHA, and VDDPETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned- off port is close to zero. For example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be calculated quite simply as 3/16 multiplied by the power consumption indicated in the above table. Note 2: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: VDDPEA, VDDPEHA, and VDDPETA. Number of Active Lanes per Port Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.1V Typ 3.3V Max 3.465 Typ Power Max Power x8/x8/x8/x4/x4 (Full Swing) mA 2486 3400 1623 1806 230 234 679 729 3 5 x8/x8/x8/x4/x4 (Half Swing) mA 2486 3400 1396 1553 230 234 353 379 3 5 Table 18 PES32NT8BG2 Power Consumption

IDT 89HPES32NT8BG2 Datasheet 19 of 35 December 17, 2013 Thermal Considerations This section describes thermal considerations for the PES32NT8BG2 (23mm2 FCBGA484 package). The data in Table 19 below contains informa- tion that is relevant to the thermal performance of the PES32NT8BG2 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 19. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be maintained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 19), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products 85 oC Maximum for industrial-rated products JA(effective) Effective Thermal Resistance, Junction-to-Ambient 15.2 oC/W Zero air flow 8.5 oC/W 1 m/S air flow 7.1 oC/W 2 m/S air flow JB Thermal Resistance, Junction-to-Board 3.1 oC/W JC Thermal Resistance, Junction-to-Case 0.15 oC/W P Power Dissipation of the Device 7.19 Watts Maximum Table 19 Thermal Specifications for PES32NT8BG2, 23x23 mm FCBGA484 Package

IDT 89HPES32NT8BG2 Datasheet 20 of 35 December 17, 2013 Values based on systems running at recommended supply voltages, as shown in Table 16. Note: See Table 10, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- 3.5dB De-emphasized differential out- put voltage VTX-DE-RATIO- 6.0dB De-emphasized differential out- put voltage VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 66 d B ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120  VTX-CM-ACpp Peak-Peak AC Common NA 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 0 3.6 0 3.6 V VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detec- tion 600 600 mV I TX-SHORT Transmitter Short Circuit Current Limit 09 0 9 0 m A Table 20 DC Electrical Characteristics (Part 1 of 4)

IDT 89HPES32NT8BG2 Datasheet 21 of 35 December 17, 2013 Serial Link (cont.) PCIe Receive VRX-DIFFp-p Differential input voltage (peak- to-peak) 175 1200 120 1200 mV RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz 8 1.25 - 2.5GHz RLRX-CM Receiver Common Mode Return Loss 66 d B ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec  ZRX--DC DC common mode impedance 40 50 60 40 60  ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 50k  ZRX-HIGH-IMP- DC-POS DC input CM input impedance for V>0 during reset or power down 50k 50k  Z RX-HIGH-IMP- DC-NEG DC input CM input impedance for V<0 during reset or power down 1.0k 1.0k  V RX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 65 175 mV VRX-CM-ACp Receiver AC common-mode peak voltage 150 150 mV V RX-CM-ACp PCIe REFCLK CIN Input Capacitance 1.5 — 1.5 — pF Other I/Os LOW Drive Output IOL —2 . 5— —2 . 5 — m A V OL = 0.4v IOH —- 5 . 5— —- 5 . 5 — m A V OH = 1.5V High Drive Output IOL —1 2 . 0— —1 2 . 0 — m A V OL = 0.4v Schmitt Trigger Input (STI) VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Input V IL -0.3 — 0.8 -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 3.3V Output Low Voltage VOL —— 0 . 4 —0 . 4 V I OL = 8mA for JTAG_TDO and GPIO pins 3.3V Output High Volt- age VOH 2.4 — — 2.4 — — V I OH = 8mA for JTAG_TDO and GPIO pins I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 20 DC Electrical Characteristics (Part 2 of 4)

IDT 89HPES32NT8BG2 Datasheet 22 of 35 December 17, 2013 Capacitance C IN — — 8.5 — — 8.5 pF — I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 20 DC Electrical Characteristics (Part 3 of 4)

IDT 89HPES32NT8BG2 Datasheet 23 of 35 December 17, 2013 Absolute Maximum Voltage Rating Warning: For proper and reliable operation in adherence with this data s heet, the device should not exceed the recommended operating vol tages in Table 16. The absolute maximum operating voltages in Table 21 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability. SMBus Characterization Leakage Inputs — — + 10 — — + 10 AV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 — — + 10 AV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 — — + 80 AV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1. Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Table 21 PES32NT8BG2 Absolute Maximum Voltage Rating Symbol Parameter SMBus 2.0 Char. Data1 Unit 3V 3.3V 3.6V DC Parameter for SDA Pin VIL Input Low 1.16 1.26 1.35 V VIH Input High 1.56 1.67 1.78 V VOL@350uA Output Low 15 15 15 mV IOL@0.4V 23 24 25 mA IPullup Current Source — — — A IIL_Leak Input Low Leakage 0 0 0 A IIH_Leak Input High Leakage 0 0 0 A Table 22 SMBus DC Characterization Data (Part 1 of 2) I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 20 DC Electrical Characteristics (Part 4 of 4)

IDT 89HPES32NT8BG2 Datasheet 24 of 35 December 17, 2013 DC Parameter for SCL Pin VIL (V) Input Low 1.11 1.2 1.31 V VIH (V) Input High 1.54 1.65 1.76 V IIL_Leak Input Low Leakage 0 0 0 A IIH_Leak Input High Leakage 0 0 0 A 1. Data at room and hot temperature. Symbol Parameter SMBus @3.3V ±10%1 1. Data at room and hot temperature. Unit Min Max FSCL Clock frequency 5 600 KHz TBUF Bus free time between Stop and Start 3.5 — s THD:STA Start condition hold time 1 — s TSU:STA Start condition setup time 1 — s TSU:STO Stop condition setup time 1 — s THD:DAT Data hold time 1 — ns TSU:DAT Data setup time 1 — ns TTIMEOUT Detect clock low time out — 74.7 ms TLOW 2. TLOW and THIGH are measured at FSCL = 135 kHz. Clock low period 3.7 — s THIGH 2 Clock high period 3.7 — s TF Clock/Data fall time — 72.2 ns TR Clock/Data rise time — 68.3 ns TPOR@10kHz Time which a device must be operational after power-on reset 20 — ms Table 23 SMBus AC Timing Data Symbol Parameter SMBus 2.0 Char. Data1 Unit 3V 3.3V 3.6V Table 22 SMBus DC Characterization Data (Part 2 of 2)

IDT 89HPES32NT8BG2 Datasheet 25 of 35 December 17, 2013 The following table lists the pin numbers and signal names for the PES32NT8BG2 device. Note: Pins labeled NC are No Connection. Pin Function Alt. Pin Function Alt. Pin Function Alt. A1 V SS B5 V SS C9 V SS A2 V DDI/O B6 PE06TN1 C10 PE06RN0 A3 PE06TP3 B7 PE06TN0 C11 V SS A4 PE06TP2 B8 V SS C12 V SS A5 V SS B9 GCLKN0 C13 PE04RN3 A6 PE06TP1 B10 V SS C14 V SS A7 PE06TP0 B11 PE04TN3 C15 PE04RN2 A8 V SS B12 PE04TN2 C16 REFRES02 A9 GCLKP0 B13 V SS C17 V SS A10 V SS B14 P04CLKN C18 PE04RN0 A11 PE04TP3 B15 V SS C19 PERSTN A12 PE04TP2 B16 PE04TN1 C20 JTAG_TRST_N A13 V SS B17 PE04TN0 C21 SSMBDAT A14 P04CLKP B18 V DDI/O C22 V DDI/O A15 V SS B19 MSMBCLK D1 V SS A16 PE04TP1 B20 JTAG_TMS D2 V SS A17 PE04TP0 B21 SSMBCLK D3 V SS A18 V DDI/O B22 JTAG_TCK D4 V SS A19 MSMBDAT C1 V SS D5 PE06RP3 A20 JTAG_TDO C2 V DDI/O D6 PE06RN2 A21 CLKMODE1 C3 V SS D7 V SS A22 SSMBADDR2 C4 V SS D8 PE06RP1 B1 V SS C5 PE06RN3 D9 V SS B2 V DDI/O C6 V SS D10 PE06RP0 B3 PE06TN3 C7 V SS D11 REFRESPLL B4 PE06TN2 C8 PE06RN1 D12 V SS Table 24 PES32NT8BG2 Signal Pin-Out (Part 1 of 7)

IDT 89HPES32NT8BG2 Datasheet 26 of 35 December 17, 2013 D13 PE04RP3 E17 PE04RP1 F21 PE02TN2 D14 V SS E18 V DDPEHA F22 PE02TP2 D15 PE04RP2 E19 V SS G1 PE08TP0 D16 V SS E20 V SS G2 PE08TN0 D17 PE04RN1 E21 PE02TN3 G3 V SS D18 PE04RP0 E22 PE02TP3 G4 PE08RN1 D19 V SS F1 V SS G5 PE08RP1 D20 JTAG_TDI F2 V SS G6 V DDPEA D21 V DDI/O F3 PE08RN0 G7 V SS D22 V DDI/O F4 PE08RP0 G8 V DDCORE E1 V SS F5 V DDPEHA G9 V DDCORE E2 V SS F6 V DDPEHA G10 V SS E3 V SS F7 V DDPEHA G11 V DDCORE E4 V SS F8 V DDPEA G12 V DDCORE E5 V DDPEHA F9 V DDPETA G13 V SS E6 PE06RP2 F10 V DDPEA G14 V DDCORE E7 V DDPEA F11 V DDPEA G15 V DDCORE E8 V DDPEA F12 V DDPETA G16 V SS E9 V DDPETA F13 V DDPETA G17 V DDPEA E10 V DDPEA F14 V DDPEA G18 V DDPEA E11 REFRES03 F15 V DDPEA G19 PE02RP3 E12 V DDPETA F16 V DDPEA G20 PE02RN3 E13 NC F17 V DDPEHA G21 V SS E14 V SS F18 V DDPEHA G22 V SS E15 V DDPEA F19 V DDPEHA H1 PE08TP1 E16 V SS F20 V SS H2 PE08TN1 Pin Function Alt. Pin Function Alt. Pin Function Alt. Table 24 PES32NT8BG2 Signal Pin-Out (Part 2 of 7)

IDT 89HPES32NT8BG2 Datasheet 27 of 35 December 17, 2013 H3 REFRES05 J7 V SS K11 V DDCORE H4 V SS J8 V DDCORE K12 V DDCORE H5 V DDPEA J9 V DDCORE K13 V SS H6 V DDPEA J10 V SS K14 V DDCORE H7 V SS J11 V DDCORE K15 V DDCORE H8 V DDCORE J12 V DDCORE K16 V SS H9 V DDCORE J13 V SS K17 V DDPETA H10 V SS J14 V DDCORE K18 REFRES01 H11 V DDCORE J15 V DDCORE K19 PE02RP1 H12 V DDCORE J16 V SS K20 PE02RN1 H13 V SS J17 V DDPETA K21 V SS H14 V DDCORE J18 V DDPETA K22 V SS H15 V DDCORE J19 REFRES00 L1 PE08TP3 H16 V SS J20 NC L2 PE08TN3 H17 V DDPEA J21 P02CLKN L3 V SS H18 PE02RP2 J22 P02CLKP L4 V SS H19 PE02RN2 K1 PE08TP2 L5 V DDPEA H20 V SS K2 PE08TN2 L6 V DDPEA H21 P00CLKN K3 V SS L7 V SS H22 P00CLKP K4 PE08RN3 L8 V DDCORE J1 V SS K5 PE08RP3 L9 V DDCORE J2 V SS K6 V DDPETA L10 V SS J3 PE08RN2 K7 V SS L11 V DDCORE J4 PE08RP2 K8 V DDCORE L12 V DDCORE J5 V DDPETA K9 V DDCORE L13 V SS J6 V DDPETA K10 V SS L14 V DDCORE Pin Function Alt. Pin Function Alt. Pin Function Alt. Table 24 PES32NT8BG2 Signal Pin-Out (Part 3 of 7)

IDT 89HPES32NT8BG2 Datasheet 28 of 35 December 17, 2013 L15 V DDCORE M19 V SS P1 PE12TP1 L16 V SS M20 V SS P2 PE12TN1 L17 V DDPEA M21 PE02TN0 P3 V SS L18 PE02RP0 M22 PE02TP0 P4 V SS L19 PE02RN0 N1 PE12TP0 P5 V DDPETA L20 V SS N2 PE12TN0 P6 V DDPETA L21 PE02TN1 N3 REFRES04 P7 V SS L22 PE02TP1 N4 PE12RN1 P8 V DDCORE M1 V SS N5 PE12RP1 P9 V DDCORE M2 V SS N6 V DDPEA P10 V SS M3 PE12RN0 N7 V SS P11 V DDCORE M4 PE12RP0 N8 V DDCORE P12 V DDCORE M5 V DDPEA N9 V DDCORE P13 V SS M6 V DDPEA N10 V SS P14 V DDCORE M7 V SS N11 V DDCORE P15 V DDCORE M8 V DDCORE N12 V DDCORE P16 V SS M9 V DDCORE N13 V SS P17 V DDPEA M10 V SS N14 V DDCORE P18 PE00RP2 M11 V DDCORE N15 V DDCORE P19 PE00RN2 M12 V DDCORE N16 V SS P20 V SS M13 V SS N17 V DDPEA P21 PE00TN3 M14 V DDCORE N18 V DDPEA P22 PE00TP3 M15 V DDCORE N19 PE00RP3 R1 V SS M16 V SS N20 PE00RN3 R2 V SS M17 V DDPEA N21 V SS R3 PE12RN2 M18 V DDPEA N22 V SS R4 PE12RP2 Pin Function Alt. Pin Function Alt. Pin Function Alt. Table 24 PES32NT8BG2 Signal Pin-Out (Part 4 of 7)

IDT 89HPES32NT8BG2 Datasheet 29 of 35 December 17, 2013 R5 V DDPETA T9 V DDCORE U13 V DDPEA R6 V DDPETA T10 V SS U14 V DDPEA R7 V SS T11 V DDCORE U15 V DDPETA R8 V DDCORE T12 V DDCORE U16 V DDPEA R9 V DDCORE T13 V SS U17 V DDPEHA R10 V SS T14 V DDCORE U18 PE00RP0 R11 V DDCORE T15 V DDCORE U19 PE00RN0 R12 V DDCORE T16 V SS U20 V SS R13 V SS T17 V DDPETA U21 PE00TN1 R14 V DDCORE T18 V DDPETA U22 PE00TP1 R15 V DDCORE T19 PE00RP1 V1 V DDI/O R16 V SS T20 PE00RN1 V2 V DDI/O R17 V DDPETA T21 V SS V3 PE12RN3 R18 V DDPETA T22 V SS V4 PE12RP3 R19 V SS U1 PE12TP3 V5 V SS R20 V SS U2 PE12TN3 V6 PE16RP1 R21 PE00TN2 U3 V SS V7 V SS R22 PE00TP2 U4 V SS V8 V DDPEA T1 PE12TP2 U5 V DDPEHA V9 V DDPEA T2 PE12TN2 U6 V DDPEHA V10 V SS T3 V SS U7 V DDPEA V11 V DDPETA T4 V SS U8 V DDPEA V12 V SS T5 V DDPEHA U9 V DDPEA V13 V DDPEA T6 V DDPEHA U10 V DDPETA V14 PE20RP1 T7 V SS U11 V DDPETA V15 V DDPETA T8 V DDCORE U12 V DDPEA V16 V DDPEA Pin Function Alt. Pin Function Alt. Pin Function Alt. Table 24 PES32NT8BG2 Signal Pin-Out (Part 5 of 7)

IDT 89HPES32NT8BG2 Datasheet 30 of 35 December 17, 2013 V17 V DDPEHA W21 V DDI/O AA3 SWMODE0 V18 V DDPEHA W22 V DDI/O AA4 V SS V19 V SS Y1 STK0CFG0 AA5 V DDI/O V20 V SS Y2 STK3CFG0 AA6 PE16TN0 V21 PE00TN0 Y3 V SS AA7 PE16TN1 V22 PE00TP0 Y4 V DDI/O AA8 V SS W1 V SS Y5 PE16RN0 AA9 PE16TN2 W2 STK1CFG0 Y6 V SS AA10 PE16TN3 W3 STK2CFG0 Y7 V SS AA11 V SS W4 V DDI/O Y8 PE16RN2 AA12 GCLKN1 W5 PE16RP0 Y9 V SS AA13 V SS W6 PE16RN1 Y10 V SS AA14 PE20TN0 W7 REFRES06 Y11 PE16RN3 AA15 PE20TN1 W8 PE16RP2 Y12 V SS AA16 V SS W9 V SS Y13 PE20RN0 AA17 PE20TN2 W10 V SS Y14 V SS AA18 PE20TN3 W11 PE16RP3 Y15 REFRES07 AA19 V SS W12 V SS Y16 PE20RN2 AA20 GPIO_03 2 W13 PE20RP0 Y17 V SS AA21 GPIO_04 2 W14 PE20RN1 Y18 V SS AA22 GPIO_05 2 W15 V SS Y19 PE20RN3 AB1 SWMODE1 W16 PE20RP2 Y20 GPIO_06 2 AB2 RSTHALT W17 V SS Y21 GPIO_07 2 AB3 SWMODE2 W18 V DDPEHA Y22 GPIO_08 2 AB4 SWMODE3 W19 PE20RP3 AA1 CLKMODE0 AB5 V DDI/O W20 V DDI/O AA2 GCLKFSEL AB6 PE16TP0 Pin Function Alt. Pin Function Alt. Pin Function Alt. Table 24 PES32NT8BG2 Signal Pin-Out (Part 6 of 7)

IDT 89HPES32NT8BG2 Datasheet 31 of 35 December 17, 2013 AB7 PE16TP1 AB13 V SS AB19 V SS AB8 V SS AB14 PE20TP0 AB20 GPIO_00 2 AB9 PE16TP2 AB15 PE20TP1 AB21 GPIO_01 2 AB10 PE16TP3 AB16 V SS AB22 GPIO_02 2 AB11 V SS AB17 PE20TP2 AB12 GCLKP1 AB18 PE20TP3 Pin Function Alt. Pin Function Alt. Pin Function Alt. Table 24 PES32NT8BG2 Signal Pin-Out (Part 7 of 7)

IDT 89HPES32NT8BG2 Datasheet 32 of 35 December 17, 2013

IDT 89HPES32NT8BG2 Datasheet 33 of 35 December 17, 2013 Note: Nominal package height: 2.63mm Minimum package height: 2.53mm.

IDT 89HPES32NT8BG2 Datasheet 34 of 35 December 17, 2013

Revision History

October 27, 2010: Initial publication of final data sheet. November 11, 2010: Added ZB silicon on Ordering page. January 26, 2011: In Table 18, Power Consumption, revised IO ( and Total) power numbers in Full Sw ing section and added Half Swing section. Adjusted P value in Table 19. March 9, 2011: In Table 10, deleted “External pull-down” from the Notes column for JTAG_TRST_N. March 28, 2011: In Tables 16 and 17, added VDDPETA to footnote #1. May 20, 2011: Removed ZA silicon and added ZC to Order page and codes. November 7, 2011: Revised values in Table 18, Power Consumption, and updated power dissipation value in Table 19. November 29, 2011: Added new Tables 22 and 23, SMBus Characterization and Timing. March 14, 2012: In Table 3, revised description for GCLKN/P signals. April 16, 2013: In Table 20, added 3.3V output voltage parameters under Other I/Os category. May 16, 2013: Added Note after Table 11. In Table 20, added information in the Conditions column for the 3.3V parameters. December 17, 2013: Added footnote 2 to Table 23.

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Ordering Information

89H32NT8BG2ZBHL 484-ball FCBGA package, Commercial Temp. 89H32NT8BG2ZCHL 484-ball FCBGA package, Commercial Temp. 89H32NT8BG2ZBHLG 484-ball Green FC BGA package, Commercial Temp. 89H32NT8BG2ZCHLG 4 84-ball Green FCBGA package, Commercial Temp. 89H32NT8BG2ZBHLI 484-ball FCBGA package, Industrial Temp. 89H32NT8BG2ZCHLI 484-ball FCBGA package, Industrial Temp. 89H32NT8BG2ZBHLGI 484-ball Green FCBGA package, Industrial Temp. 89H32NT8BG2ZCHLGI 484-ball Green FCBGA package, Industrial Temp. NN A NNAANA AAA A Operating Voltage Product Package Temp Range H Product Family

89 Serial Switching Product

32NT8B 32-lane, 8-port 1.0V Core Voltage Detail Legend A = Alpha Character N = Numeric Character AA Device Revision AN Generation Series G2 PCIe Gen 2 484-ball FCBGA HL 484-ball FCBGA, Green HLG Blank Commercial Temperature (0°C to +70°C Ambient) I Industrial Temperature (-40° C to +85° C Ambient) ZB ZB revision ZC ZC revision