89HPES32H8

89HPES32H8 IDT | Alldatasheet

Document overview

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Technical content

Features

◆ High Performance PCI Express Switch – Eight maximum switch ports

Four main ports each of which consists of eight SerDes
Each x8 main port can further bifurcate to 2 x4-ports – Thirty-two 2.5 Gbps embedded SerDes
Supports pre-emphasis and receive equalization on per-port basis – Delivers 128 Gbps (16 GBps) aggregate switching capacity – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – Supports two virtual channels and eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ◆ Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin algorithms – Virtual channels arbitration based on priority – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all ports – Supports locked transactions, allowing use with legacy soft- ware – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates thirty-two 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Redundant upstream port failover capability – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) Block Diagram Figure 1 Internal Block Diagram 8-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 DL/Transaction Layer SerDes x8/x4/x2/x1 89HPES32H8 Data Sheet 32-Lane 8-Port PCI Express® System Interconnect Switch

2 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet – Supports optional PCI Express end-to-end CRC checking – Supports optional PCI Express Advanced Error Reporting – Supports PCI Express Hot-Plug

Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM)
Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3hot) – Unused SerDes disabled ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Thirty-two General Purpose Input/Output pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in a 31mm x 31mm 900-ball Flip Chip BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES32H8 provides the most efficient system interconnect switching solution for applications requiring maximum throughput, low latency, and simple board layout with a minimum number of board layers. It provides 128 Gbps of aggre- gated, full-duplex switching capacity through 32 integrated serial lanes, using proven and robust IDT technology . Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES32H8 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification or cut-through switch and is designed to switch memory and I/O transac- tions. It supports eight Traffic Cla sses (TCs) and two Virtual Channels (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded appli- cations. SMBus Interface The PES32H8 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32H8, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configura- tion register values of the PES32H8 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pi ns are sampled, the resulting address is assigned as shown in Table 1. Figure 2 Port Configuration Examples Note: The configurations in the above diagram show the maximum port widths. The PES32H8 can negotiate to narrower port widths — x4, x2, or x1. 1 0 Non-bifurcated Fully Bifurcated 4 5 x87 4 5 x4x4

3 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES32H8 acts both as a SMBus master as well as a SMBus slave on th is bus. This requires that the SMBus master or processor that has access to PES32H8 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a pr ocessor or micro controller, and may not support SMBus arbit ration. To support these systems, the PES32H8 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operat e as two independent buses and thus multi-master arbitration is never required. The PES32H8 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES32H8 supports PCI Express Hot-Plug on each downstream port (ports 1 through 7). To reduce the number of pins required on the device, the PES32H8 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. F ollowing reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32H8 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is r eceived on the IOEX- PINTN input pin (alternate function of GPIO) of the PES32H8. In response to an I/O expander interrupt, the PES32H8 generates an SMBus transac- tion to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES32H8 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose outputs, or alternate functions. Some GPIO pins are shared wi th other on-chip functions. These alternate functions may be enabl ed via software, SMBus slave interface, or serial configuration EEPROM. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment Processor PES32H8 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM Processor PES32H8 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses

4 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES32H8. Some of the functions listed may be multiplexed o nto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ- ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal ending in “N” is the negative portion of the differential pair. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PE1RP[3:0] PE1RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PE1TP[3:0] PE1TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PE2RP[3:0] PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[3:0] PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PE3RP[3:0] PE3RN[3:0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. PE3TP[3:0] PE3TN[3:0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. PE4RP[3:0] PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[3:0] PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PE5RP[3:0] PE5RN[3:0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. PE5TP[3:0] PE5TN[3:0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. PE6RP[3:0] PE6RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE6TP[3:0] PE6TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6. PE7RP[3:0] PE7RN[3:0] I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. Table 2 PCI Express Interface Pins (Part 1 of 2)

5 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PE7TP[3:0] PE7TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz PEREFCLKP[3:0] PEREFCLKN[3:0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output Table 4 General Purpose I/O Pins (Part 1 of 3) Signal Type Name/Description Table 2 PCI Express Interface Pins (Part 2 of 2)

6 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 GPIO[12] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P7RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 7 GPIO[13] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[14] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[15] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[16] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[17] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[18] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[19] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Signal Type Name/Description Table 4 General Purpose I/O Pins (Part 2 of 3)

7 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet GPIO[20] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[21] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 0 GPIO[22] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 1 GPIO[23] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 2 GPIO[24] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 3 GPIO[25] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[26] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[27] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[28] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[29] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[30] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[31] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN10 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 10 Signal Type Name/Description Table 4 General Purpose I/O Pins (Part 3 of 3)

8 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. P01MERGEN I Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a single x8 port. The SerDes lanes associated with port B become lanes 4 through 7 of port 0. P23MERGEN I Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a single x8 port. The SerDes lanes associated with port D become lanes 4 through 7 of port 2. P45MERGEN I Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a single x8 port. The SerDes lanes associated with port F become lanes 4 through 7 of port 4. P67MERGEN I Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 6. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES32H8 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES32H8 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES32H8 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - Normal switch mode with upstream port failover (port 0 selected as the upstream port) 0x9 - Normal switch mode with upstream port failover (port 2 selected as the upstream port) 0xA - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 0 selected as the upstream port) 0xB - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 2 selected as the upstream port) 0xC through 0xF - Reserved Table 5 System Pins

9 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VSS I Ground. VTTPE PCI Express Serial Data Transmit Termination Voltage. This pin allows the driver termination voltage to be set, enabling the system designer to control the Common Mode Voltage and output voltage swing of the corre- sponding PCI Serial Data Transmit differential pair. Table 7 Power and Ground Pins

10 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Pin Characteristics Note: Some input pads of the PES32H8 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor Notes PCI Express Interface PE0RN[3:0] I CML Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE1RN[3:0] I PE1RP[3:0] I PE1TN[3:0] O PE1TP[3:0] O PE2RN[3:0] I PE2RP[3:0] I PE2TN[3:0] O PE2TP[3:0] O PE3RN[3:0] I PE3RP[3:0] I PE3TN[3:0] O PE3TP[3:0] O PE4RN[3:0] I PE4RP[3:0] I PE4TN[3:0] O PE4TP[3:0] O PE5RN[3:0] I PE5RP[3:0] I PE5TN[3:0] O PE5TP[3:0] O PE6RN[3:0] I PE6RP[3:0] I PE6TN[3:0] O PE6TP[3:0] O PE7RN[3:0] I PE7RP[3:0] I PE7TN[3:0] O PE7TP[3:0] O Table 8 Pin Characteristics (Part 1 of 2)

11 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PCI Express Interface (cont.) PEREFCLKN[3:0] I LVPECL/ CML Diff. Clock Input Refer to Table 9 PEREFCLKP[3:0] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL STI 1 pull-up MSMBCLK I/O STI MSMBDAT I/O STI SSMBADDR[5,3:1] I pull-up SSMBCLK I/O STI SSMBDAT I/O STI General Purpose I/O GPIO[31:0] I/O LVTTL pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down P01MERGEN I pull-down P23MERGEN I pull-down P45MERGEN I pull-down P67MERGEN I pull-down PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-down 1. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor Notes Table 8 Pin Characteristics (Part 2 of 2)

12 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Logic Diagram — PES32H8 Figure 4 PES32H8 Logic Diagram ... Reference Clocks PEREFCLKP[3:0] PEREFCLKN[3:0] JTAG_TCK GPIO[31:0]

32 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT Master SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[3:0] CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE1RP[0] PE1RN[0] PE1RP[3] PE1RN[3] PCI Express Switch SerDes Input PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PCI Express Switch SerDes Output ... Port 1 Port 1 ... PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PE2TP[3] PE2TN[3] PCI Express Switch SerDes Output ... Port 2 Port 2 ... PE3RP[0] PE3RN[0] PE3RP[3] PE3RN[3] PCI Express Switch SerDes Input PE3TP[0] PE3TN[0] PE3TP[3] PE3TN[3] PCI Express Switch SerDes Output ... Port 3 Port 3 ... PE7RP[0] PE7RN[0] PE7RP[3] PE7RN[3] PCI Express Switch SerDes Input PE7TP[0] PE7TN[0] PE7TP[3] PE7TN[3] PCI Express Switch SerDes Output ... Port 7 Port 7 ... PES32H8 ... P01MERGEN P23MERGEN P45MERGEN P67MERGEN SSMBADDR[5,3:1] SSMBCLK SSMBDAT Slave SMBus Interface

13 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. AC Timing Characteristics Parameter Description Min Typical Max Unit PEREFCLK RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps Table 9 Input Clock Requirements Parameter Description Min 1 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns Table 10 PCIe AC Timing Characteristics

14 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Figure 5 GPIO AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[31:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns See Figure 5. Table 11 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Referenc e JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 6. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset sta te. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Tpw_13b EXTCLK GPIO (asynchronous input)

15 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Figure 6 JTAG AC Timing Waveform Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. For the PES32H8, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the rev erse order of the power-up sequence. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES32H8 Operating Voltages Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

16 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Grade Temperature Commercial 0 °C to +70°C Ambient Industrial -40 °C to +85°C Ambient Table 14 PES32H8 Operating Temperatures Number of active Lanes per Port Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V Typ Power Max Power 8/8/8/8 mA 1800 2100 1677 1990 792 909 804 826 1 2 5.5W 6.81W Table 15 PES32H8 Power Consumption

17 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Thermal Considerations This section describes thermal considerations for the PES32H8 (31mm 2 FCBGA900 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES32H8 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 10 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 1 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oC Maximum TA(max) Ambient Temperature 70 oC Maximum θJC Thermal Resistance, Junction-to-Case 0.2 oC/W P Power Dissipation of the Device 6.81 Watts Maximum Table 16 Thermal Specifications for PES32H8, 31x31 mm FCBGA900 Package

18 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 17 DC Electrical Characteristics (Part 1 of 2)

19 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL — 12.0 — mA V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 17 DC Electrical Characteristics (Part 2 of 2)

20 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet The following table lists the pin numbers and signal names for the PES32H8 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B5 V SS C9 V SS D13 V SS A2 V SS B6 V SS C10 V SS D14 PE3RP01 A3 GPIO_19 B7 V SS C11 V SS D15 PE3RP00 A4 V DDIO B8 V SS C12 V SS D16 V SS A5 V SS B9 V SS C13 V SS D17 PE2RP03 A6 V SS B10 V SS C14 V SS D18 PE2RP02 A7 V SS B11 PE3TN03 C15 V SS D19 V SS A8 V SS B12 PE3TN02 C16 V SS D20 PE2RP01 A9 V SS B13 V SS C17 V SS D21 PE2RP00 A10 V SS B14 PE3TN01 C18 V SS D22 V SS A11 PE3TP03 B15 PE3TN00 C19 V SS D23 V SS A12 PE3TP02 B16 V SS C20 V SS D24 V SS A13 V SS B17 PE2TN03 C21 V SS D25 V SS A14 PE3TP01 B18 PE2TN02 C22 V SS D26 JTAG_TMS A15 PE3TP00 B19 V SS C23 V SS D27 V DDIO A16 V SS B20 PE2TN01 C24 V SS D28 SSMBADDR_5 A17 PE2TP03 B21 PE2TN00 C25 V SS D29 SSMBADDR_3 A18 PE2TP02 B22 V SS C26 MSMBADDR_4 D30 V DDIO A19 V SS B23 V SS C27 JTAG_TDI E1 V DDIO A20 PE2TP01 B24 V SS C28 JTAG_TRST_N E2 GPIO_30 A21 PE2TP00 B25 V SS C29 SSMBADDR_2 E3 GPIO_31 1 A22 V SS B26 MSMBADDR_3 C30 SSMBADDR_1 E4 GPIO_24 1 A23 V SS B27 MSMBADDR_2 D1 GPIO_28 1 E5 V SS A24 V SS B28 PERSTN D2 GPIO_26 1 E6 V SS A25 V SS B29 V DDIO D3 V DDIO E7 V SS A26 V DDIO B30 V SS D4 GPIO_23 1 E8 V SS A27 MSMBADDR_1 C1 GPIO_29 D5 V SS E9 PEREFCLKP1 A28 MSMBSMODE C2 GPIO_27 1 D6 V SS E10 V SS A29 V SS C3 GPIO_21 1 D7 V SS E11 PE3RN03 A30 V SS C4 GPIO_16 D8 V SS E12 PE3RN02 B1 V SS C5 V SS D9 PEREFCLKN1 E13 V SS B2 V DDIO C6 V SS D10 V SS E14 PE3RN01 B3 GPIO_18 C7 V SS D11 PE3RP03 E15 PE3RN00 B4 GPIO_17 C8 V SS D12 PE3RP02 E16 V SS Table 18 PES32H8 900-pin Signal Pin-Out (Part 1 of 7)

21 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet E17 PE2RN03 F23 V SS G29 V SS J5 PEREFCLKN2 E18 PE2RN02 F24 MSMBDAT G30 V SS J6 V SS E19 V SS F25 V DDIO H1 V SS J7 V SS E20 PE2RN01 F26 SSMBCLK H2 V SS J8 V SS E21 PE2RN00 F27 V SS H3 V SS J9 V SS E22 V SS F28 V SS H4 V SS J10 V SS E23 V SS F29 V SS H5 V SS J11 V DDPE E24 V SS F30 V SS H6 V SS J12 V DDPE E25 MSMBCLK G1 V SS H7 V DDIO J13 V DDPE E26 V SS G2 V SS H8 GPIO_22 1 J14 V SS E27 V SS G3 V SS H9 V SS J15 V DDPE E28 V SS G4 V SS H10 V SS J16 V DDPE E29 V SS G5 V SS H11 V TTPE J17 V SS E30 V SS G6 V SS H12 V SS J18 V DDPE F1 V SS G7 GPIO_25 1 H13 V DDAPE J19 V DDPE F2 V SS G8 V SS H14 V SS J20 V DDPE F3 V SS G9 V SS H15 V TTPE J21 V SS F4 V SS G10 V SS H16 V TTPE J22 V SS F5 V SS G11 V SS H17 V SS J23 V SS F6 GPIO_20 G12 V DDPE H18 V DDAPE J24 V SS F7 V DDIO G13 V SS H19 V SS J25 V SS F8 V SS G14 V SS H20 V TTPE J26 V SS F9 V SS G15 V TTPE H21 V SS J27 V SS F10 V SS G16 V TTPE H22 V SS J28 V SS F11 V SS G17 V SS H23 CCLKDS J29 V SS F12 V SS G18 V SS H24 JTAG_TCK J30 V SS F13 V SS G19 V DDPE H25 V SS K1 V SS F14 V SS G20 V SS H26 V SS K2 V SS F15 V SS G21 V SS H27 V SS K3 V SS F16 V SS G22 V SS H28 V SS K4 V SS F17 V SS G23 JTAG_TDO H29 V SS K5 V SS F18 V SS G24 V DDIO H30 V SS K6 V SS F19 V SS G25 SSMBDAT J1 V SS K7 V SS F20 V SS G26 V SS J2 V SS K8 V SS F21 V SS G27 V SS J3 V SS K9 V SS F22 V SS G28 V SS J4 PEREFCLKP2 K10 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES32H8 900-pin Signal Pin-Out (Part 2 of 7)

22 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet K11 V DDPE L17 V DDCORE M23 V SS N29 PE1TN01 K12 V SS L18 V DDCORE M24 V DDPE N30 PE1TP01 K13 V DDPE L19 V DDCORE M25 V SS P1 PE4TP02 K14 V SS L20 V DDCORE M26 V SS P2 PE4TN02 K15 V DDPE L21 V DDPE M27 V SS P3 V SS K16 V DDPE L22 V DDPE M28 V SS P4 PE4RP02 K17 V SS L23 V TTPE M29 V SS P5 PE4RN02 K18 V DDPE L24 V SS M30 V SS P6 V SS K19 V SS L25 V SS N1 V SS P7 V SS K20 V DDPE L26 PE1RN02 N2 V SS P8 V SS K21 V SS L27 PE1RP02 N3 V SS P9 V SS K22 V SS L28 V SS N4 V SS P10 V SS K23 V SS L29 PE1TN02 N5 V SS P11 V SS K24 V SS L30 PE1TP02 N6 V SS P12 V SS K25 V SS M1 PE4TP01 N7 V SS P13 V DDCORE K26 PE1RN03 M2 PE4TN01 N8 V DDAPE P14 V SS K27 PE1RP03 M3 V SS N9 V DDPE P15 V DDCORE K28 V SS M4 PE4RP01 N10 V DDPE P16 V SS K29 PE1TN03 M5 PE4RN01 N11 V DDCORE P17 V DDCORE K30 PE1TP03 M6 V SS N12 V DDCORE P18 V SS L1 PE4TP00 M7 V DDPE N13 V SS P19 V DDCORE L2 PE4TN00 M8 V SS N14 V DDCORE P20 V DDCORE L3 V SS M9 V DDPE N15 V SS P21 V SS L4 PE4RP00 M10 V SS N16 V DDCORE P22 V SS L5 PE4RN00 M11 V DDCORE N17 V SS P23 V SS L6 V SS M12 V SS N18 V DDCORE P24 V SS L7 V SS M13 V DDCORE N19 V SS P25 V SS L8 V TTPE M14 V SS N20 V DDCORE P26 PE1RN00 L9 V DDPE M15 V DDCORE N21 V DDPE P27 PE1RP00 L10 V DDPE M16 V SS N22 V DDPE P28 V SS L11 V DDCORE M17 V DDCORE N23 V DDAPE P29 PE1TN00 L12 V DDCORE M18 V SS N24 V SS P30 PE1TP00 L13 V DDCORE M19 V DDCORE N25 V SS R1 PE4TP03 L14 V SS M20 V DDCORE N26 PE1RN01 R2 PE4TN03 L15 V DDCORE M21 V SS N27 PE1RP01 R3 V SS L16 V SS M22 V DDPE N28 V SS R4 PE4RP03 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES32H8 900-pin Signal Pin-Out (Part 3 of 7)

23 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet R5 PE4RN03 T11 V SS U17 V SS V23 V DDAPE R6 V SS T12 V SS U18 V DDCORE V24 V SS R7 V TTPE T13 V DDCORE U19 V SS V25 V SS R8 V TTPE T14 V SS U20 V SS V26 V SS R9 V DDPE T15 V DDCORE U21 V SS V27 V SS R10 V DDPE T16 V SS U22 V SS V28 V SS R11 V DDCORE T17 V DDCORE U23 V SS V29 V SS R12 V DDCORE T18 V SS U24 V SS V30 V SS R13 V SS T19 V DDCORE U25 V SS W1 V SS R14 V DDCORE T20 V DDCORE U26 PE0RN02 W2 V SS R15 V SS T21 V DDPE U27 PE0RP02 W3 V SS R16 V DDCORE T22 V DDPE U28 V SS W4 V SS R17 V SS T23 V TTPE U29 PE0TN02 W5 V SS R18 V DDCORE T24 V TTPE U30 PE0TP02 W6 V SS R19 V SS T25 V SS V1 PE5TP01 W7 V DDPE R20 V SS T26 PE0RN03 V2 PE5TN01 W8 V SS R21 V DDPE T27 PE0RP03 V3 V SS W9 V DDPE R22 V DDPE T28 V SS V4 PE5RP01 W10 V SS R23 V TTPE T29 PE0TN03 V5 PE5RN01 W11 V DDCORE R24 V TTPE T30 PE0TP03 V6 V SS W12 V DDCORE R25 V SS U1 PE5TP00 V7 V SS W13 V SS R26 V SS U2 PE5TN00 V8 V DDAPE W14 V DDCORE R27 V SS U3 V SS V9 V DDPE W15 V SS R28 V SS U4 PE5RP00 V10 V DDPE W16 V DDCORE R29 V SS U5 PE5RN00 V11 V DDCORE W17 V SS R30 V SS U6 V SS V12 V SS W18 V DDCORE T1 V SS U7 V SS V13 V DDCORE W19 V SS T2 V SS U8 V SS V14 V SS W20 V DDCORE T3 V SS U9 V SS V15 V DDCORE W21 V SS T4 V SS U10 V SS V16 V SS W22 V DDPE T5 V SS U11 V DDCORE V17 V DDCORE W23 V SS T6 V SS U12 V DDCORE V18 V SS W24 V DDPE T7 V TTPE U13 V SS V19 V DDCORE W25 V SS T8 V TTPE U14 V DDCORE V20 V DDCORE W26 PE0RN01 T9 V DDPE U15 V SS V21 V DDPE W27 PE0RP01 T10 V DDPE U16 V DDCORE V22 V DDPE W28 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES32H8 900-pin Signal Pin-Out (Part 4 of 7)

24 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet W29 PE0TN01 AA5 PE5RN03 AB11 V DDPE AC17 V SS W30 PE0TP01 AA6 V SS AB12 V DDPE AC18 V DDAPE Y1 PE5TP02 AA7 V SS AB13 V DDPE AC19 V SS Y2 PE5TN02 AA8 V SS AB14 V SS AC20 V TTPE Y3 V SS AA9 V SS AB15 V DDPE AC21 V SS Y4 PE5RP02 AA10 V SS AB16 V DDPE AC22 V SS Y5 PE5RN02 AA11 V DDPE AB17 V SS AC23 GPIO_06 1 Y6 V SS AA12 V SS AB18 V DDPE AC24 V DDIO Y7 V SS AA13 V DDPE AB19 V DDPE AC25 V SS Y8 V TTPE AA14 V SS AB20 V DDPE AC26 V SS Y9 V DDPE AA15 V DDPE AB21 V SS AC27 V SS Y10 V DDPE AA16 V DDPE AB22 V SS AC28 V SS Y11 V DDCORE AA17 V SS AB23 V SS AC29 V SS Y12 V DDCORE AA18 V DDPE AB24 V SS AC30 V SS Y13 V DDCORE AA19 V SS AB25 V SS AD1 V SS Y14 V DDCORE AA20 V DDPE AB26 PEREFCLKN0 AD2 V SS Y15 V SS AA21 V SS AB27 PEREFCLKP0 AD3 V SS Y16 V DDCORE AA22 V SS AB28 V SS AD4 V SS Y17 V SS AA23 V SS AB29 V SS AD5 V SS Y18 V DDCORE AA24 V SS AB30 V SS AD6 V SS Y19 V DDCORE AA25 V SS AC1 V SS AD7 V DDIO Y20 V DDCORE AA26 V SS AC2 V SS AD8 V DDIO Y21 V DDPE AA27 V SS AC3 V SS AD9 V SS Y22 V DDPE AA28 V SS AC4 V SS AD10 V SS Y23 V TTPE AA29 V SS AC5 V SS AD11 V SS Y24 V SS AA30 V SS AC6 V SS AD12 V DDPE Y25 V SS AB1 V SS AC7 V DDIO AD13 V SS Y26 PE0RN00 AB2 V SS AC8 V DDIO AD14 V SS Y27 PE0RP00 AB3 V SS AC9 V SS AD15 V TTPE Y28 V SS AB4 V SS AC10 V SS AD16 V TTPE Y29 PE0TN00 AB5 V SS AC11 V TTPE AD17 V SS Y30 PE0TP00 AB6 V SS AC12 V SS AD18 V SS AA1 PE5TP03 AB7 V SS AC13 V DDAPE AD19 V DDPE AA2 PE5TN03 AB8 V SS AC14 V SS AD20 V SS AA3 V SS AB9 V SS AC15 V TTPE AD21 V SS AA4 PE5RP03 AB10 V SS AC16 V TTPE AD22 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES32H8 900-pin Signal Pin-Out (Part 5 of 7)

25 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet AD23 V SS AE29 V SS AG5 V SS AH11 V SS AD24 GPIO_09 1 AE30 V SS AG6 V SS AH12 V SS AD25 V SS AF1 V SS AG7 V SS AH13 V SS AD26 V SS AF2 V SS AG8 V SS AH14 V SS AD27 V SS AF3 V SS AG9 V SS AH15 V SS AD28 V SS AF4 V SS AG10 PE6RP00 AH16 V SS AD29 V SS AF5 V SS AG11 PE6RP01 AH17 V SS AD30 V SS AF6 REFCLKM AG12 V SS AH18 V SS AE1 V SS AF7 V SS AG13 PE6RP02 AH19 V SS AE2 V SS AF8 V SS AG14 PE6RP03 AH20 V SS AE3 V SS AF9 V SS AG15 V SS AH21 V SS AE4 V SS AF10 PE6RN00 AG16 PE7RP00 AH22 V SS AE5 CCLKUS AF11 PE6RN01 AG17 PE7RP01 AH23 V SS AE6 V DDIO AF12 V SS AG18 V SS AH24 V SS AE7 V SS AF13 PE6RN02 AG19 PE7RP02 AH25 V SS AE8 V SS AF14 PE6RN03 AG20 PE7RP03 AH26 V SS AE9 V SS AF15 V SS AG21 V SS AH27 GPIO_00 AE10 V SS AF16 PE7RN00 AG22 PEREFCLKN3 AH28 GPIO_05 1 AE11 V SS AF17 PE7RN01 AG23 V SS AH29 GPIO_11 1 AE12 V SS AF18 V SS AG24 V SS AH30 GPIO_13 AE13 V SS AF19 PE7RN02 AG25 V SS AJ1 V SS AE14 V SS AF20 PE7RN03 AG26 V SS AJ2 V DDIO AE15 V SS AF21 V SS AG27 GPIO_07 1 AJ3 V SS AE16 V SS AF22 PEREFCLKP3 AG28 V DDIO AJ4 SWMODE_0 AE17 V SS AF23 V SS AG29 GPIO_10 1 AJ5 SWMODE_2 AE18 V SS AF24 V SS AG30 GPIO_12 1 AJ6 V SS AE19 V SS AF25 V SS AH1 P23MERGEN AJ7 V SS AE20 V SS AF26 V SS AH2 P67MERGEN AJ8 V SS AE21 V SS AF27 GPIO_08 1 AH3 V SS AJ9 V SS AE22 V SS AF28 GPIO_15 AH4 V SS AJ10 PE6TN00 AE23 V SS AF29 GPIO_14 AH5 SWMODE_3 AJ11 PE6TN01 AE24 V DDIO AF30 V DDIO AH6 V SS AJ12 V SS AE25 GPIO_04 AG1 V DDIO AH7 V SS AJ13 PE6TN02 AE26 V SS AG2 P01MERGEN AH8 V SS AJ14 PE6TN03 AE27 V SS AG3 P45MERGEN AH9 V SS AJ15 V SS AE28 V SS AG4 V DDIO AH10 V SS AJ16 PE7TN00 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES32H8 900-pin Signal Pin-Out (Part 6 of 7)

26 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Alternate Signal Functions AJ17 PE7TN01 AJ28 GPIO_02 AK9 V SS AK20 PE7TP03 AJ18 V SS AJ29 V DDIO AK10 PE6TP00 AK21 V SS AJ19 PE7TN02 AJ30 V SS AK11 PE6TP01 AK22 V SS AJ20 PE7TN03 AK1 V SS AK12 V SS AK23 V SS AJ21 V SS AK2 V SS AK13 PE6TP02 AK24 V SS AJ22 V SS AK3 RSTHALT AK14 PE6TP03 AK25 V SS AJ23 V SS AK4 SWMODE_1 AK15 V SS AK26 V SS AJ24 V SS AK5 V DDIO AK16 PE7TP00 AK27 V DDIO AJ25 V SS AK6 V SS AK17 PE7TP01 AK28 GPIO_03 AJ26 V SS AK7 V SS AK18 V SS AK29 V SS AJ27 GPIO_01 AK8 V SS AK19 PE7TP02 AK30 V SS Pin GPIO Alternate Pin GPIO Alternate AH28 GPIO_05 GPEN H8 GPIO_22 IOEXPINTN1 AC23 GPIO_06 P1RSTN D4 GPIO_23 IOEXPINTN2 AG27 GPIO_07 P2RSTN E4 GPIO_24 IOEXPINTN3 AF27 GPIO_08 P3RSTN G7 GPIO_25 IOEXPINTN4 AD24 GPIO_09 P4RSTN D2 GPIO_26 IOEXPINTN5 AG29 GPIO_10 P5RSTN C2 GPIO_27 IOEXPINTN6 AH29 GPIO_11 P6RSTN D1 GPIO_28 IOEXPINTN7 AG30 GPIO_12 P7RSTN E3 GPIO_31 IOEXPINTN10 C3 GPIO_21 IOEXPINTN0 Table 19 PES32H8 Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 18 PES32H8 900-pin Signal Pin-Out (Part 7 of 7)

27 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Power Pins VDDCore V DDCore V DDIO V DDPE V DDPE V DDAPE V TTPE L11 T17 A4 G12 T9 H13 G15 L12 T19 A26 G19 T10 H18 G16 L13 T20 B2 J11 T21 N8 H11 L15 U11 B29 J12 T22 N23 H15 L17 U12 D3 J13 V9 V8 H16 L18 U14 D27 J15 V10 V23 H20 L19 U16 D30 J16 V21 AC13 L8 L20 U18 E1 J18 V22 AC18 L23 M11 V11 F7 J19 W7 R7 M13 V13 F25 J20 W9 R8 M 1 5V 1 5G 2 4K 1 1W 2 2 R 2 3 M17 V17 H7 K13 W24 R24 M19 V19 AC7 K15 Y9 T7 M20 V20 AC8 K16 Y10 T8 N11 W11 AC24 K18 Y21 T23 N12 W12 AD7 K20 Y22 T24 N14 W14 AD8 L9 AA11 Y8 N16 W16 AE6 L10 AA13 Y23 N18 W18 AE24 L21 AA15 AC11 N20 W20 AF30 L22 AA16 AC15 P13 Y11 AG1 M7 AA18 AC16 P15 Y12 AG4 M9 AA20 AC20 P17 Y13 AG28 M22 AB11 AD15 P19 Y14 AJ2 M24 AB12 AD16 P20 Y16 AJ29 N9 AB13 R11 Y18 AK5 N10 AB15 R12 Y19 AK27 N21 AB16 R14 Y20 N22 AB18 R16 R9 AB19 R18 R10 AB20 T13 R21 AD12 T15 R22 AD19 Table 20 PES32H8 Power Pins

28 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Ground Pins VSS VSS VSS VSS VSS VSS VSS VSS A1 C8 E13 F30 H21 K8 M29 R13 A2 C9 E16 G1 H22 K9 M30 R15 A5 C10 E19 G2 H25 K10 N1 R17 A6 C11 E22 G3 H26 K12 N2 R19 A7 C12 E23 G4 H27 K14 N3 R20 A8 C13 E24 G5 H28 K17 N4 R25 A9 C14 E26 G6 H29 K19 N5 R26 A10 C15 E27 G8 H30 K21 N6 R27 A13 C16 E28 G9 J1 K22 N7 R28 A16 C17 E29 G10 J2 K23 N13 R29 A19 C18 E30 G11 J3 K24 N15 R30 A22 C19 F1 G13 J6 K25 N17 T1 A23 C20 F2 G14 J7 K28 N19 T2 A 2 4 C 2 1F 3G 1 7J 8 L 3N 2 4T 3 A 2 5 C 2 2F 4G 1 8J 9 L 6N 2 5T 4 A29 C23 F5 G20 J10 L7 N28 T5 A30 C24 F8 G21 J14 L14 P3 T6 B1 C25 F9 G22 J17 L16 P6 T11 B5 D5 F10 G26 J21 L24 P7 T12 B6 D6 F11 G27 J22 L25 P8 T14 B7 D7 F12 G28 J23 L28 P9 T16 B8 D8 F13 G29 J24 M3 P10 T18 B9 D10 F14 G30 J25 M6 P11 T25 B10 D13 F15 H1 J26 M8 P12 T28 B13 D16 F16 H2 J27 M10 P14 U3 B16 D19 F17 H3 J28 M12 P16 U6 B19 D22 F18 H4 J29 M14 P18 U7 B22 D23 F19 H5 J30 M16 P21 U8 B23 D24 F20 H6 K1 M18 P22 U9 B24 D25 F21 H9 K2 M21 P23 U10 B25 E5 F22 H10 K3 M23 P24 U13 B30 E6 F23 H12 K4 M25 P25 U15 C5 E7 F27 H14 K5 M26 P28 U17 C6 E8 F28 H17 K6 M27 R3 U19 C7 E10 F29 H19 K7 M28 R6 U20 Table 21 PES32H8 Ground Pins (Part 1 of 2)

29 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet U21 W17 AA27 AC9 AD23 AE28 AG25 AJ9 U22 W19 AA28 AC10 AD25 AE29 AG26 AJ12 U23 W21 AA29 AC12 AD26 AE30 AH3 AJ15 U24 W23 AA30 AC14 AD27 AF1 AH4 AJ18 U25 W25 AB1 AC17 AD28 AF2 AH6 AJ21 U28 W28 AB2 AC19 AD29 AF3 AH7 AJ22 V3 Y3 AB3 AC21 AD30 AF4 AH8 AJ23 V6 Y6 AB4 AC22 AE1 AF5 AH9 AJ24 V7 Y7 AB5 AC25 AE2 AF7 AH10 AJ25 V12 Y15 AB6 AC26 AE3 AF8 AH11 AJ26 V14 Y17 AB7 AC27 AE4 AF9 AH12 AJ30 V16 Y24 AB8 AC28 AE7 AF12 AH13 AK1 V18 Y25 AB9 AC29 AE8 AF15 AH14 AK2 V24 Y28 AB10 AC30 AE9 AF18 AH15 AK6 V25 AA3 AB14 AD1 AE10 AF21 AH16 AK7 V26 AA6 AB17 AD2 AE11 AF23 AH17 AK8 V27 AA7 AB21 AD3 AE12 AF24 AH18 AK9 V28 AA8 AB22 AD4 AE13 AF25 AH19 AK12 V29 AA9 AB23 AD5 AE14 AF26 AH20 AK15 V30 AA10 AB24 AD6 AE15 AG5 AH21 AK18 W1 AA12 AB25 AD9 AE16 AG6 AH22 AK21 W2 AA14 AB28 AD10 AE17 AG7 AH23 AK22 W3 AA17 AB29 AD11 AE18 AG8 AH24 AK23 W4 AA19 AB30 AD13 AE19 AG9 AH25 AK24 W5 AA21 AC1 AD14 AE20 AG12 AH26 AK25 W6 AA22 AC2 AD17 AE21 AG15 AJ1 AK26 W8 AA23 AC3 AD18 AE22 AG18 AJ3 AK29 W10 AA24 AC4 AD20 AE23 AG21 AJ6 AK30 W13 AA25 AC5 AD21 AE26 AG23 AJ7 W15 AA26 AC6 AD22 AE27 AG24 AJ8 V SS VSS VSS VSS VSS VSS VSS VSS Table 21 PES32H8 Ground Pins (Part 2 of 2)

30 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I H23 System CCLKUS I AE5 GPIO_00 I/O AH27 General Purpose I/O GPIO_01 I/O AJ27 GPIO_02 I/O AJ28 GPIO_03 I/O AK28 GPIO_04 I/O AE25 GPIO_05 I/O AH28 GPIO_06 I/O AC23 GPIO_07 I/O AG27 GPIO_08 I/O AF27 GPIO_09 I/O AD24 GPIO_10 I/O AG29 GPIO_11 I/O AH29 GPIO_12 I/O AG30 GPIO_13 I/O AH30 GPIO_14 I/O AF29 GPIO_15 I/O AF28 GPIO_16 I/O C4 GPIO_17 I/O B4 GPIO_18 I/O B3 GPIO_19 I/O A3 GPIO_20 I/O F6 GPIO_21 I/O C3 General Purpose I/O (cont.) GPIO_22 I/O H8 GPIO_23 I/O D4 GPIO_24 I/O E4 GPIO_25 I/O G7 GPIO_26 I/O D2 GPIO_27 I/O C2 GPIO_28 I/O D1 GPIO_29 I/O C1 GPIO_30 I/O E2 GPIO_31 I/O E3 Table 22 89PES32H8 Alphabetical Signal List (Part 1 of 6)

31 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet JTAG_TCK I H24 Test JTAG_TDI I C27 JTAG_TDO O G23 JTAG_TMS I D26 JTAG_TRST_N I C28 MSMBADDR_1 I A27 SMBus Interface MSMBADDR_2 I B27 MSMBADDR_3 I B26 MSMBADDR_4 I C26 MSMBCLK I/O E25 MSMBDAT I/O F24 MSMBSMODE I A28 System P01MERGEN I AG2 P23MERGEN I AH1 P45MERGEN I AG3 P67MERGEN I AH2 PE0RN00 I Y26 PCI Express PE0RN01 I W26 PE0RN02 I U26 PE0RN03 I T26 PE0RP00 I Y27 PE0RP01 I W27 PE0RP02 I U27 PE0RP03 I T27 PE0TN00 O Y29 PE0TN01 O W29 PE0TN02 O U29 PE0TN03 O T29 PE0TP00 O Y30 PE0TP01 O W30 PE0TP02 O U30 PE0TP03 O T30 PE1RN00 I P26 PE1RN01 I N26 PE1RN02 I L26 Signal Name I/O Type Location Signal Category Table 22 89PES32H8 Alphabetical Signal List (Part 2 of 6)

32 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PE1RN03 I K26 PCI Express (cont.) PE1RP00 I P27 PE1RP01 I N27 PE1RP02 I L27 PE1RP03 I K27 PE1TN00 O P29 PE1TN01 O N29 PE1TN02 O L29 PE1TN03 O K29 PE1TP00 O P30 PE1TP01 O N30 PE1TP02 O L30 PE1TP03 O K30 PE2RN00 I E21 PE2RN01 I E20 PE2RN02 I E18 PE2RN03 I E17 PE2RP00 I D21 PE2RP01 I D20 PE2RP02 I D18 PE2RP03 I D17 PE2TN00 O B21 PE2TN01 O B20 PE2TN02 O B18 PE2TN03 O B17 PE2TP00 O A21 PE2TP01 O A20 PE2TP02 O A18 PE2TP03 O A17 PE3RN00 I E15 PE3RN01 I E14 PE3RN02 I E12 PE3RN03 I E11 PE3RP00 I D15 PE3RP01 I D14 PE3RP02 I D12 Signal Name I/O Type Location Signal Category Table 22 89PES32H8 Alphabetical Signal List (Part 3 of 6)

33 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PE3RP03 I D11 PCI Express (cont.) PE3TN00 O B15 PE3TN01 O B14 PE3TN02 O B12 PE3TN03 O B11 PE3TP00 O A15 PE3TP01 O A14 PE3TP02 O A12 PE3TP03 O A11 PE4RN00 I L5 PE4RN01 I M5 PE4RN02 I P5 PE4RN03 I R5 PE4RP00 I L4 PE4RP01 I M4 PE4RP02 I P4 PE4RP03 I R4 PE4TN00 O L2 PE4TN01 O M2 PE4TN02 O P2 PE4TN03 O R2 PE4TP00 O L1 PE4TP01 O M1 PE4TP02 O P1 PE4TP03 O R1 PE5RN00 I U5 PE5RN01 I V5 PE5RN02 I Y5 PE5RN03 I AA5 PE5RP00 I U4 PE5RP01 I V4 PE5RP02 I Y4 PE5RP03 I AA4 PE5TN00 O U2 PE5TN01 O V2 PE5TN02 O Y2 Signal Name I/O Type Location Signal Category Table 22 89PES32H8 Alphabetical Signal List (Part 4 of 6)

34 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PE5TN03 O AA2 PCI Express (cont.) PE5TP00 O U1 PE5TP01 O V1 PE5TP02 O Y1 PE5TP03 O AA1 PE6RN00 I AF10 PE6RN01 I AF11 PE6RN02 I AF13 PE6RN03 I AF14 PE6RP00 I AG10 PE6RP01 I AG11 PE6RP02 I AG13 PE6RP03 I AG14 PE6TN00 O AJ10 PE6TN01 O AJ11 PE6TN02 O AJ13 PE6TN03 O AJ14 PE6TP00 O AK10 PE6TP01 O AK11 PE6TP02 O AK13 PE6TP03 O AK14 PE7RN00 I AF16 PE7RN01 I AF17 PE7RN02 I AF19 PE7RN03 I AF20 PE7RP00 I AG16 PE7RP01 I AG17 PE7RP02 I AG19 PE7RP03 I AG20 PE7TN00 O AJ16 PE7TN01 O AJ17 PE7TN02 O AJ19 PE7TN03 O AJ20 PE7TP00 O AK16 PE7TP01 O AK17 PE7TP02 O AK19 Signal Name I/O Type Location Signal Category Table 22 89PES32H8 Alphabetical Signal List (Part 5 of 6)

35 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PE7TP03 O AK20 PCI Express (cont.) PEREFCLKN0 I AB26 PEREFCLKN1 I D9 PEREFCLKN2 I J5 PEREFCLKN3 I AG22 PEREFCLKP0 I AB27 PEREFCLKP1 I E9 PEREFCLKP2 I J4 PEREFCLKP3 I AF22 PERSTN I B28 System REFCLKM I AF6 PCI Express RSTHALT I AK3 System SSMBADDR_1 I C30 SMBus Interface SSMBADDR_2 I C29 SSMBADDR_3 I D29 SSMBADDR_5 I D28 SSMBCLK I/O F26 SSMBDAT I/O G25 SWMODE_0 I AJ4 System SWMODE_1 I AK4 SWMODE_2 I AJ5 SWMODE_3 I AH5 V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 20 for a listing of power pins. VSS See Table 21 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 22 89PES32H8 Alphabetical Signal List (Part 6 of 6)

36 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet PES32H8 Pinout — Top View 1 2 3 4 5 6 7 8 91 01 1 1 21 3 1 4 1 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VTTPE (Power)VDDPE (Power) VDDAPE (Power) Signals 27 28 29 30 AG AH AJ AK 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 4 1 5 1 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK X X X X X XX XX XX X XX X X X X XX X XX X

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Revision History

July 19, 2007: Initial publication of data sheet.

40 of 40 July 19, 2007 IDT 89HPES32H8 Data Sheet CORPORATE HEADQUARTERS

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Ordering Information

89HPES32H8ZAAL 900-ball FCBGA package, Commercial Temperature 89HPES32H8ZAAR 900-ball RoHS FCBGA package, Commercial Temperature 89HPES32H8ZAALI 900-ball FCBGA package, Industrial Temperature 89HPES32H8ZAARI 900-ball RoHS FCBGA package, Industrial Temperature NN AA A A NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

32H8 32-lane, 8-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character 900-ball FCBGA, RoHS AR AA Device Revision ZA ZA revision I Industrial Temperature (-40° C to +85° C Ambient)

Summary

32-Lane 8-Port PCI Express System Interconnect Switch

Description