89HPES24T3G2ZCBL

89HPES24T3G2 RENESAS | Alldatasheet

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Features

u High Performance PCI Express Switch – Twenty-four 5 Gbps Gen2 PCI Express lanes supporti ng 5 Gbps and 2.5 Gbps operation Up to three switch ports – Support for Max Payload Size up to 2048 bytes – Supports one virtual channel and eight traffic classes – Fully compliant with PCI Expr ess base specification Revision 2.0 u Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2, or x1 – Automatic lane reversal on all ports – Automatic polarity inversion – Supports in-band hot-plug presence de tect capability Supports external signal for hot plug event notification allowing SCI/SMI generation for legacy operating systems – Dynamic link width reconfiguration for power/performance optimization – Configurable downstream por t PCI-to-PCI bridge device numbering – Crosslink support – Supports ARI forwarding defined in the Alternative Routing-ID Interpretation (ARI) ECN for virtualized and non-virtualized environments – Ability to load device conf iguration from serial EEPROM u Legacy Support – PCI compatible INTx emulation – Supports bus locked transactions, allowing use of PCI Express with legacy software u Highly Integrated Solution Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes, 8B/10B encoder/decoder (no separate transceivers needed) u Reliability, Availability, and Serviceability (RAS) Features – Ability to disable peer-to-peer communications – Supports ECRC and Advanced Error Reporting – All internal data and control RAMs are SECDED ECC protected – Supports PCI Express hot-p lug on all downstream ports – Supports upstream port hot-plug Block Diagram Figure 1 Internal Block Diagram SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer 3-Port Switch Core / 24 Gen2 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer 89HPES24T3G2 Datasheet 24-Lane 3-Port Gen2 PCI Express® Switch

2 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet – Hot-swap capable I/O – External Serial EEPROM contents are checksum protected – Supports PCI Express Device Serial Number Capability – Capability to monitor link re liability and autonomously change link speed to prevent link instability u Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Power Management Interface specification (PCI- PM 1.1)

• Supports device power management states: D0, D3 hot and D3cold – Support for PCI Express Active State Power Management (ASPM) link state
• Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3 – Supports PCI Express Power Budgeting Capability – Configurable SerDes power consumption
• Supports optional PCI-Express SerDes Transmit Low-Swing Voltage Mode
• Supports numerous SerDes Transmit Voltage Margin settings – Unused SerDes are disabled u Testability and Debug Features – Per port link up and activity st atus outputs available on I/O expander outputs – Built in SerDes 8-bit and 10-bit pseudo-random bit stream (PRBS) generators – Numerous SerDes test modes, including a PRBS Master Loopback mode for in-system link testing – Ability to read and write any in ternal register via SMBus and JTAG interfaces, including SerDes internal controls – Per port statistics and performance counters, as well as propri- etary link status registers u General Purpose Input/Output Pins – Each pin may be individually co nfigured as an input or output – Each pin may be individually co nfigured as an interrupt input – Some pins have selectable alternate functions u Option A Package: 19mm x 19mm 324-ball Flip Chip BGA with 1mm ball spacing u Option B Package: 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spac ing Product Description Utilizing standard PCI Express interconnect, the PES24T3G2 provides the most efficient I/O c onnectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It pr ovides connectivity for up to 3 ports across 24 integrated serial l anes. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5 Gbps, and mixed 5 Gbps / 2.5Gbps modes. The PES24T3G2 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traf fic Classes (TCs) and one Virtual Channel (VC) with sophisticated re source management to enable effi- cient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. Figure 2 I/O Expansion Application SMBus Interface The PES24T3G2 contains two SMBus interfaces. The slave inter- face provides full access to the configuration registers in the PES24T3G2, allowing every configurat ion register in the device to be read or written by an external agen t. The master interface allows the default configuration register val ues of the PES24T3G2 to be over- ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interfac e, these address pins allow the SMBus address to which the device re sponds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be config- ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pi ns. When the pins are sampled, the resulting address is assigned as shown in Table 1. Note: MSMBADDR and SSMBADDR address pins are not available in the 19mm package. The MSMBADDR address is hardwired to 0x50, and the SSMBADDR address is hardwired to 0x77. MemoryMemoryMemory Processor MemoryNorth Bridge PES24T3G2 I/O Dual 10GbE I/O SATA I/O SATAPCI Express Slot Processor x8 x8

3 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES24T3G2 acts both as a SMBus master as well as a SMBus slave on t his bus. This requires that the SMBus master or processor that has access to PES24T3G2 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBu s arbitration. To support these systems, the PES24T3G2 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses oper ate as two independent buses and thus multi-master arbitration is never required. The PES24T3G2 supports reading and writing of the serial EEPROM on the master SMBu s via the slave SMBus, allowing in system pro gramming of the serial EEPROM. Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES24T3G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24T3G2 utilizes an external I/O expander, such as that used on PC mother boards, connected to the SMBus mast er interface. Following res et and configura- tion, whenever the state of a Hot-Plug out put needs to be modified, the PES24T3G2 generat es an SMBus transaction to the I/O exp ander with the new value of all of the outputs. Whenever a Hot-Plug input c hanges, the I/O expander generates an interrupt which is received o n the IOEXPINTN input pin (alternate function of GPIO) of the PES24T3G2. In response to an I/O expander interrupt, the PES24T3G2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES24T3G2 provides General Purpose Input/Output (GPIO) pins (7 pins in the 19mm package and 11 pins in the 27mm package) that may be used by the system designer as bit I/O por ts. Each GPIO pin may be configured independent ly as an input or output through softw are control. Many GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configura- tion EEPROM. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment for 27x27mm PackageProcessor PES24T3G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM Processor PES24T3G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses

4 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Pin Description The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES24T3G2, the two downstream ports are labeled port 2 and port 4. Signal Type Name/Description PE0RP[7:0] PE0RN[7:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[7:0] PE0TN[7:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. Port 0 is the upstream port. PE2RP[7:0] PE2RN[7:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[7:0] PE2TN[7:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE4RP[7:0] PE4RN[7:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[7:0] PE4TN[7:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 4. PEREFCLKP PEREFCLKN I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM 1. REFCLKM is not available in the 19mm package and frequency is set at 100MHz. I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN. Table 2 PCI Express Interface Pins Signal Type Name/Description MSMBADDR[4:1] 1 I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1]2 I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. Table 3 SMBus Interface Pins (Part 1 of 2)

5 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. 1. MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50. 2. SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77. Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[3] 1. GPIO pins 3, 4, 5, 6 are not available in the 19mm package. I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: I/O Expander interrupt 1 input GPIO[4] 1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] 1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[6]1 I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 4 General Purpose I/O Pins Signal Type Name/Description Table 3 SMBus Interface Pins (Part 2 of 2)

6 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Signal Type Name/Description CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each down- stream port’s PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. MSMBSMODE 1. MSMBSMODE is not available in the 19mm package, resulting in the master SMBus operating only at 400 KHz. I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES24T3G2 and initiates a PCI Express fundamental reset. RSTHALT 2. RSTHALT is not available in the 19mm package. I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES24T3G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES24T3G2 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. Table 5 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. Table 6 Test Pins (Part 1 of 2)

7 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Signal Type Name/Description REFRES0, REFRES1 I/O Port 0 External Reference Resistors. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from these pins to ground. REFRES2, REFRES3 I/O Port 2 External Reference Resistors. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from these pins to ground. REFRES4, REFRES5 I/O Port 4 External Reference Resistors. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from these pins to ground. V DDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V). VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS I Ground. Table 7 Power, Ground, and SerDes Resistor Pins Signal Type Name/Description Table 6 Test Pins (Part 2 of 2)

8 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Pin Characteristics Note: Some input pads of the PES24T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[7:0] I PCIe differential2 Serial Link PE0RP[7:0] I PE0TN[7:0] O PE0TP[7:0] O PE2RN[7:0] I PE2RP[7:0] I PE2TN[7:0] O PE2TP[7:0] O PE4RN[7:0] I PE4RP[7:0] I PE4TN[7:0] O PE4TP[7:0] O PEREFCLKN I HCSL Diff. Clock Input Refer to Table 9 PEREFCLKP I REFCLKM

3 I LVTTL Input pull-down

SMBus MSMBADDR[4:1] 4 I LVTTL Input pull-down MSMBCLK I/O STI 5 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1]

4 I Input pull-up

SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[10:0]

6 I/O LVTTL STI,

System Pins CCLKDS I LVTTL Input pull-up CCLKUS I Input pull-up MSMBSMODE

7 I Input pull-down

SWMODE[2:0] I Input pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up Table 8 Pin Characteristics (Part 1 of 2)

9 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet SerDes Reference Resistors REFRES0 I/O Analog REFRES1 I/O REFRES2 I/O REFRES3 I/O REFRES4 I/O REFRES5 I/O 1. Internal resistor values under typical operating conditions are 92K  for pull-up and 90K for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. 3. REFCLKM pin is not available in the 19mm package. 4. SMBus address pins are not available in the 19mm package. 5. Schmitt Trigger Input (STI). 6. GPIO pins 3, 4, 5, 6 are not available in the 19mm package. 7. MSMBSMODE and RSTHALT are not available in the 19mm package. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2)

10 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Logic Diagram — PES24T3G2 Figure 4 PES24T3G2 Logic Diagram Note: The following pins are not available in the 19mm package: REFCLKM, MSMBADDR, SSMBADDR, MSMBSMODE, RSTHALT, GPIO[6:3]. Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[10:0]

11 General Purpose

I/O* VDDCORE VDDI/O VDDPEA Power/Ground MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALTSystem Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[2:0] CCLKDS PERSTN REFCLKM MSMBSMODE PE0RP[0] PE0RN[0] PE0RP[7] PE0RN[7] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PE0TP[7] PE0TN[7] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE2RP[0] PE2RN[0] PE2RP[7] PE2RN[7] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PE2TP[7] PE2TN[7] PCI Express Switch SerDes Output ... Port 2 Port 2 ... PE4RP[0] PE4RN[0] PE4RP[7] PE4RN[7] PCI Express Switch SerDes Input PE4TP[0] PE4TN[0] PE4TP[7] PE4TN[7] PCI Express Switch SerDes Output ... Port 4 Port 4 ...PES24T3G2 REFRES0 SerDes Reference Resistors REFRES2 REFRES4 REFRES5 VDDPEHA Reference Clock Frequency Selection REFRES1 REFRES3 VDDPETA

11 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15. AC Timing Characteristics Parameter Description Condition Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. Frequency is set at 100 MHz in the 19mm package. MHz TC-RISE Rising edge rate Differential 0.6 4 V/ns TC-FALL Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 mV VIL Differential input low voltage Differential -150 mV voltage Single-ended +250 +550 mV VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended +140 mV VRB Ring back voltage margin Differential -100 +100 mV TSTABLE Time before VRB is allowed Differential 500 ps TPERIOD-AVG Average clock period accuracy -300 2800 ppm trum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps Duty Cycle Duty cycle 40 60 % Rise/Fall Matching Single ended rising Refclk edge rate ver- sus falling Refclk edge rate 20 % ZC-DC Clock source output DC impedance 40 60  Table 9 Input Clock Requirements Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 PCIe Transmit UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps T TX-EYE Minimum Tx Eye Width 0.75 0.75 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.125 UI TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI TTX- IDLE-MIN Minimum time in idle 20 20 UI Table 10 PCIe AC Timing Characteristics (Part 1 of 2)

12 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 88 n s TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 8 8 ns TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI PCIe Receive UI Unit Interval 399.88 400 400.12 199.94 200.06 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-SKEW Lane to lane input skew 20 8 ns TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[10:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Note that GPIO{6:3} pins are not available in the 19mm package. Tpw2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 11 GPIO AC Timing Characteristics Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 Table 10 PCIe AC Timing Characteristics (Part 2 of 2)

13 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

14 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Recommended Operating Supply Voltages Absolute Maximum Voltage Rating Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages in Table 13. The absolute maximum operating voltages in Table 14 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability. Power-Up/Power-Down Sequence During power supply ramp-up, V DDCORE must remain at least 1.0V below V DDI/O at all times. There are no other power-up sequence require- ments for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerD es LVPECL/CML 3.135 3.3 3.465 V VDDPEA1 1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. PCI Express Analog Power 0.95 1.0 1.1 V VDDPEHA2 2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA1 PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 13 PES24T3G2 Operating Voltages Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Table 14 PES24T3G2 Absolute Maximum Voltage Rating Grade Temperature Commercial 0 C to +70C Ambient Industrial -40 C to +85C Ambient Table 15 PES24T3G2 Operating Temperatures

15 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Power Consumption Typical power is measured under the followi ng conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Number of Active Lanes per Port Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.15V Typ 3.3V Max 3.465V Typ Power Max Power 8/8/8 (Full Swing) mA 1010 1260 1384 1600 161 176 541 600 3 5 (Half Swing) mA 1010 1260 1190 1376 161 176 281 312 3 5 Table 16 PES24T3G2 Power Consumption

16 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Thermal Considerations — Option A Package This section describes thermal considerations for the PES24T3G2 (19mm2 FCBGA324 package). The data in Table 17 below contains information that is relevant to the thermal performance of the PES24T3G2 switch. Thermal Considerations — Option B Package This section describes thermal considerations for the PES24T3G2 (27mm2 FCBGA676 package). The data in Table 18 below contains information that is relevant to the thermal performance of the PES24T3G2 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 17. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be maintained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 17), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oCM a x i m u m JA(effective) Effective Thermal Resistance, Junction-to-Ambient 16.8 oC/W Zero air flow 10.1 oC/W 1 m/S air flow 9.2 oC/W 2 m/S air flow JB Thermal Resistance, Junction-to-Board 4.1 oC/W JC Thermal Resistance, Junction-to-Case 0.3 oC/W P Power Dissipation of the Device 4.31 Watts Maximum Table 17 Thermal Specifications for PES24T3G2, 19x19 mm FCBGA324 Package Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oCM a x i m u m JA(effective) Effective Thermal Resistance, Junction-to-Ambient 14.6 oC/W Zero air flow 8.2 oC/W 1 m/S air flow 7.2 oC/W 2 m/S air flow JB Thermal Resistance, Junction-to-Board 3.1 oC/W JC Thermal Resistance, Junction-to-Case 0.3 oC/W P Power Dissipation of the Device 4.31 Watts Maximum Table 18 Thermal Specifications for PES24T3G2, 27x27 mm FCBGA676 Package

17 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- 3.5dB De-emphasized differential output voltage VTX-DE-RATIO- 6.0dB De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC-active- idle-delta Abs delta of DC common mode voltage between L0 and idle 100 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 66 d B ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120  VTX-CM-ACpp Peak-Peak AC Common NA 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 0 3.6 0 3.6 V VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detec- tion 600 600 mV ITX-SHORT Transmitter Short Circuit Current Limit 09 0 9 0 m A Table 19 DC Electrical Characteristics (Part 1 of 2)

18 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Serial Link (cont.) PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to- peak) 175 1200 120 1200 mV RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz 8 1.25 - 2.5GHz RLRX-CM Receiver Common Mode Return Loss 66 d B ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec  ZRX--DC DC common mode impedance 40 50 60 40 60  ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 50k  ZRX-HIGH-IMP-DC- POS DC input CM input impedance for V>0 during reset or power down 50k 50k  ZRX-HIGH-IMP-DC- NEG DC input CM input impedance for V<0 during reset or power down 1.0k 1.0k  VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 65 175 mV VRX-CM-ACp Receiver AC common-mode peak voltage 150 150 mV V RX-CM-ACp PCIe REFCLK CIN Input Capacitance 1.5 — 1.5 — pF Other I/Os LOW Drive Output I OL —2 . 5— —2 . 5 — m A V OL = 0.4v IOH —- 5 . 5— —- 5 . 5 — m A V OH = 1.5V High Drive Output IOL — 12.0 — — 12.0 — mA V OL = 0.4v Schmitt Trig- ger Input (STI) VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Input V IL -0.3 — 0.8 -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Capacitance C IN —— 8 . 5 ——8 . 5p F — Leakage Inputs — — + 10 — — + 10 AV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 — — + 10 AV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 — — + 80 AV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 19 DC Electrical Characteristics (Part 2 of 2)

19 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option A Package Pinout, 19x19mm 324-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES24T3G2 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B17 PE4TN00 D15 V DDCORE F13 V SS A2 V DDI/O B18 PE4TP00 D16 V SS F14 PE4RN03 A3 V SS C1 PE2TP06 D17 V SS F15 PE4RP03 A4 V SS C2 PE2TN06 D18 V SS F16 V SS A5 V SS C3 V SS E1 PE2TP05 F17 PE4TN03 A6 V DDI/O C4 PE2RP06 E2 PE2TN05 F18 PE4TP03 A7 V SS C5 PE2RN06 E3 V SS G1 V SS A8 JTAG_TDI C6 V SS E4 PE2RP05 G2 V SS A9 MSMBDAT C7 JTAG_TCK E5 PE2RN05 G3 V SS A10 V DDI/O C8 JTAG_TRST_N E6 V DDCORE G4 V DDCORE A11 V SS C9 SSMBDAT E7 V DDCORE G5 V DDCORE A12 GPIO_00 1 C10 CCLKDS E8 V DDCORE G6 V DDPEA A13 V DDI/O C11 SWMODE_2 E9 V SS G7 V DDPEA A14 V DDI/O C12 GPIO_02 E10 V DDCORE G8 V DDCORE A15 V SS C13 GPIO_09 E11 V DDCORE G9 V DDCORE A16 V SS C14 PE4RN01 E12 V DDCORE G10 V DDCORE A17 V DDI/O C15 PE4RP01 E13 V DDCORE G11 V SS A18 V DDI/O C16 V SS E14 PE4RN02 G12 V DDPEA B1 PE2TP07 C17 PE4TN01 E15 PE4RP02 G13 V DDPEA B2 PE2TN07 C18 PE4TP01 E16 V SS G14 V DDCORE B3 V SS D1 V SS E17 PE4TN02 G15 V DDCORE B4 PE2RP07 D2 V SS E18 PE4TP02 G16 V SS B5 PE2RN07 D3 V SS F1 PE2TP04 G17 V SS B6 V DDI/O D4 V DDCORE F2 PE2TN04 G18 V SS B7 V SS D5 V DDCORE F3 V SS H1 PE2TP03 B8 JTAG_TMS D6 V DDI/O F4 PE2RP04 H2 PE2TN03 B9 SSMBCLK D7 JTAG_TDO F5 PE2RN04 H3 V SS B10 V DDI/O D8 MSMBCLK F6 V SS H4 PE2RP03 B11 SWMODE_1 D9 CCLKUS F7 V SS H5 PE2RN03 B12 GPIO_01 1 D10 SWMODE_0 F8 V DDCORE H6 V DDPEA B13 GPIO_10 D11 PERSTN F9 V SS H7 V DDPEA B14 PE4RN00 D12 GPIO_07 1 F10 V DDCORE H8 V DDCORE B15 PE4RP00 D13 GPIO_08 F11 V SS H9 V DDCORE B16 V SS D14 V DDCORE F12 V SS H10 V DDCORE Table 20 PES24T3G2 (19x19mm 324-pin) Signal Pin-Out (Part 1 of 3)

20 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet H11 V SS K13 V DDPETA M15 PE4RP07 P17 V DDCORE H12 V DDPEA K14 V DDCORE M16 V SS P18 V SS H13 V DDPEA K15 NC M17 PE4TN07 R1 V SS H14 PE4RN04 K16 V SS M18 PE4TP07 R2 V DDCORE H15 PE4RP04 K17 REFRES5 N1 V SS R3 V DDCORE H16 V SS K18 REFRES4 N2 V SS R4 PE0RP07 H17 PE4TN04 L1 PE2TP01 N3 V SS R5 PE0RP06 H18 PE4TP04 L2 PE2TN01 N4 V DDCORE R6 NC J1 PE2TP02 L3 V SS N5 V DDCORE R7 PE0RP05 J2 PE2TN02 L4 PE2RP01 N6 V SS R8 PE0RP04 J3 V SS L5 PE2RN01 N7 V SS R9 V DDCORE J4 PE2RP02 L6 V DDPETA N8 V DDPEA R10 PE0RP03 J5 PE2RN02 L7 V DDPETA N9 V DDPEHA R11 PE0RP02 J6 V DDPEHA L8 V DDPEA N10 V DDPETA R12 V DDCORE J7 V DDPEHA L9 V DDPEHA N11 V DDPEA R13 PE0RP01 J8 V DDCORE L10 V DDPETA N12 V DDPEHA R14 PE0RP00 J9 V SS L11 V DDPEA N13 V SS R15 V DDCORE J10 V DDCORE L12 V DDPEHA N14 V SS R16 V DDCORE J11 V SS L13 V DDPETA N15 V DDCORE R17 V DDCORE J12 V DDPEHA L14 PE4RN06 N16 V SS R18 V SS J13 V DDPEHA L15 PE4RP06 N17 V SS T1 V SS J14 PE4RN05 L16 V SS N18 V SS T2 V SS J15 PE4RP05 L17 PE4TN06 P1 V SS T3 V SS J16 V SS L18 PE4TP06 P2 V DDCORE T4 V SS J17 PE4TN05 M1 PE2TP00 P3 V DDCORE T5 V SS J18 PE4TP05 M2 PE2TN00 P4 PE0RN07 T6 V SS K1 REFRES2 M3 V SS P5 PE0RN06 T7 V SS K2 REFRES3 M4 PE2RP00 P6 V DDCORE T8 V SS K3 V SS M5 PE2RN00 P7 PE0RN05 T9 V SS K4 V DDCORE M6 V DDPETA P8 PE0RN04 T10 V SS K5 V DDCORE M7 V DDPETA P9 V DDCORE T11 V SS K6 V DDPETA M8 V DDPEA P10 PE0RN03 T12 V SS K7 V DDPETA M9 V DDPEHA P11 PE0RN02 T13 V SS K8 V DDCORE M10 V DDPETA P12 V DDCORE T14 V SS K9 V SS M11 V DDPEA P13 PE0RN01 T15 V SS K10 V DDCORE M12 V DDPEHA P14 PE0RN00 T16 V SS K11 V SS M13 V SS P15 V DDCORE T17 V SS K12 V DDPETA M14 PE4RN07 P16 V DDCORE T18 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 20 PES24T3G2 (19x19mm 324-pin) Signal Pin-Out (Part 2 of 3)

21 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option A Package Power Pins (19x19mm 324-Pin) U1 V SS U10 PE0TN03 V1 V SS V10 PE0TP03 U2 PEREFCLKN U11 PE0TN02 V2 PEREFCLKP V11 PE0TP02 U3 V SS U12 V SS V3 V SS V12 V SS U4 PE0TN07 U13 PE0TN01 V4 PE0TP07 V13 PE0TP01 U5 PE0TN06 U14 PE0TN00 V5 PE0TP06 V14 PE0TP00 U6 REFRES1 U15 V SS V6 REFRES0 V15 V SS U7 PE0TN05 U16 V SS V7 PE0TP05 V16 V SS U8 PE0TN04 U17 V SS V8 PE0TP04 V17 V SS U9 V SS U18 V SS V9 V SS V18 V SS VDDCore V DDCore V DDCore V DDI/O V DDPEA V DDPEHA V DDPETA D4 G9 N15 A2 G6 J6 K6 D5 G10 P2 A6 G7 J7 K7 D14 G14 P3 A10 G12 J12 K12 D15 G15 P6 A13 G13 J13 K13 E6 H8 P9 A14 H6 L9 L6 E7 H9 P12 A17 H7 L12 L7 E8 H10 P15 A18 H12 M9 L10 E10 J8 P16 B6 H13 M12 L13 E11 J10 P17 B10 L8 N9 M6 E12 K4 R2 D6 L11 N12 M7 E13 K5 R3 M8 M10 F8 K8 R9 M11 N10 F10 K10 R12 N8 G4 K14 R15 N11 G5 N4 R16 G8 N5 R17 Table 21 PES24T3G2 (19x19mm 324-Pin) Power Pins Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 20 PES24T3G2 (19x19mm 324-pin) Signal Pin-Out (Part 3 of 3)

22 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option A Package Ground Pins (19x19mm 324-Pin) Option A Package Alternate Signal Functions (19x19mm 324-Pin) VSS VSS VSS VSS VSS VSS A1 D16 G11 M3 T1 T18 A3 D17 G16 M13 T2 U1 A4 D18 G17 M16 T3 U3 A5 E3 G18 N1 T4 U9 A7 E9 H3 N2 T5 U12 A11 E16 H11 N3 T6 U15 A15 F3 H16 N6 T7 U16 A16 F6 J3 N7 T8 U17 B 3 F 7 J 9N 1 3T 9U 1 8 B7 F9 J11 N14 T10 V1 B16 F11 J16 N16 T11 V3 C3 F12 K3 N17 T12 V9 C6 F13 K9 N18 T13 V12 C16 F16 K11 P1 T14 V15 D1 G1 K16 P18 T15 V16 D2 G2 L3 R1 T16 V17 D3 G3 L16 R18 T17 V18 Table 22 PES24T3G2 (19x19mm 324-Pin) Ground Pins Pin GPIO Alternate A12 GPIO_00 P2RSTN B12 GPIO_01 P4RSTN C12 GPIO_02 IOEXPINTN0 D12 GPIO_07 GPEN Table 23 PES24T3G2 (19x19mm 324-Pin) Alternate Signal Functions

23 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option A Package Signals Listed Alphabetically (19x19mm 324-Pin) Signal Name I/O Type Location Signal Category CCLKDS I C10 System CCLKUS I D9 GPIO_00 I/O A12 General Purpose Input/Output GPIO_01 I/O B12 GPIO_02 I/O C12 GPIO_07 I/O D12 GPIO_08 I/O D13 GPIO_09 I/O C13 GPIO_10 I/O B13 JTAG_TCK I C7 JTAG JTAG_TDI I A8 JTAG_TDO O D7 JTAG_TMS I B8 JTAG_TRST_N I C8 MSMBCLK I/O D8 SMBus MSMBDAT I/O A9 NO CONNECT K15, R6 PE0RN00 I P14 PCI Express PE0RN01 I P13 PE0RN02 I P11 PE0RN03 I P10 PE0RN04 I P8 PE0RN05 I P7 PE0RN06 I P5 PE0RN07 I P4 PE0RP00 I R14 PE0RP01 I R13 PE0RP02 I R11 PE0RP03 I R10 PE0RP04 I R8 PE0RP05 I R7 PE0RP06 I R5 PE0RP07 I R4 PE0TN00 O U14 Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 1 of 4)

24 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE0TN01 O U13 PCI Express (cont.) PE0TN02 O U11 PE0TN03 O U10 PE0TN04 O U8 PE0TN05 O U7 PE0TN06 O U5 PE0TN07 O U4 PE0TP00 O V14 PE0TP01 O V13 PE0TP02 O V11 PE0TP03 O V10 PE0TP04 O V8 PE0TP05 O V7 PE0TP06 O V5 PE0TP07 O V4 PE2RN00 I M5 PE2RN01 I L5 PE2RN02 I J5 PE2RN03 I H5 PE2RN04 I F5 PE2RN05 I E5 PE2RN06 I C5 PE2RN07 I B5 PE2RP00 I M4 PE2RP01 I L4 PE2RP02 I J4 PE2RP03 I H4 PE2RP04 I F4 PE2RP05 I E4 PE2RP06 I C4 PE2RP07 I B4 PE2TN00 O M2 PE2TN01 O L2 PE2TN02 O J2 PE2TN03 O H2 PE2TN04 O F2 Signal Name I/O Type Location Signal Category Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 2 of 4)

25 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE2TN05 O E2 PCI Express (cont.) PE2TN06 O C2 PE2TN07 O B2 PE2TP00 O M1 PE2TP01 O L1 PE2TP02 O J1 PE2TP03 O H1 PE2TP04 O F1 PE2TP05 O E1 PE2TP06 O C1 PE2TP07 O B1 PE4RN00 I B14 PE4RN01 I C14 PE4RN02 I E14 PE4RN03 I F14 PE4RN04 I H14 PE4RN05 I J14 PE4RN06 I L14 PE4RN07 I M14 PE4RP00 I B15 PE4RP01 I C15 PE4RP02 I E15 PE4RP03 I F15 PE4RP04 I H15 PE4RP05 I J15 PE4RP06 I L15 PE4RP07 I M15 PE4TN00 O B17 PE4TN01 O C17 PE4TN02 O E17 PE4TN03 O F17 PE4TN04 O H17 PE4TN05 O J17 PE4TN06 O L17 PE4TN07 O M17 PE4TP00 O B18 Signal Name I/O Type Location Signal Category Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 3 of 4)

26 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE4TP01 O C18 PCI Express (cont.) PE4TP02 O E18 PE4TP03 O F18 PE4TP04 O H18 PE4TP05 O J18 PE4TP06 O L18 PE4TP07 O M18 PEREFCLKN I U2 PEREFCLKP I V2 PERSTN I D11 System REFRES0 I/O V6 SerDes Reference Resistors REFRES1 I/O U6 REFRES2 I/O K1 REFRES3 I/O K2 REFRES4 I/O K18 REFRES5 I/O K17 SSMBCLK I/O B9 SMBus SSMBDAT I/O C9 SWMODE_0 I D10 System SWMODE_1 I B11 SWMODE_2 I C11 V DDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA See Table 21 for a listing of power pins. VSS See Table 22 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 24 PES24T3G2 (19x19mm 324-Pin) Alphabetical Signal List (Part 4 of 4)

27 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option A Package — Package Trace Length Signal Name Conductor Length (microns) PE0RN00 6476.76 PE0RP00 6852.44 PE0RN01 5193.18 PE0RP01 5556.44 PE0RN02 4122.07 PE0RP02 4488.70 PE0RN03 4026.18 PE0RP03 4426.98 PE0TN00 9779.14 PE0TP00 9830.77 PE0TN01 8725.88 PE0TP01 8836.41 PE0TN02 7608.89 PE0TP02 7657.42 PE0TN03 7295.70 PE0TP03 7361.98 PE2RN00 2227.99 PE2RP00 2600.58 PE2RN01 1881.27 PE2RP01 2256.96 PE2RN02 2105.60 PE2RP02 2470.94 PE2RN03 2835.27 PE2RP03 3207.86 PE2TN00 5462.64 PE2TP00 5576.55 PE2TN01 5163.54 PE2TP01 5273.30 PE2TN02 5389.58 PE2TP02 5512.25 PE2TN03 5310.88 PE2TP03 5451.71 PE4RN00 9450.47 PE4RP00 9700.88 PE4RN01 8438.57 Table 25 Signal Trace Length (Part 1 of 2)

28 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE4RP01 8818.65 PE4RN02 8521.33 PE4RP02 8890.07 PE4RN03 9130.21 PE4RP03 9403.58 PE4TN00 12116.40 PE4TP00 12168.24 PE4TN01 12011.65 PE4TP01 12035.01 PE4TN02 12731.79 PE4TP02 12864.34 PE4TN03 11571.96 PE4TP03 11712.79 PE0REFCLKN 12558.62 PE0REFCLKP 12641.05 Signal Name Conductor Length (microns) Table 25 Signal Trace Length (Part 2 of 2)

29 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option A Package Pinout — Top View 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 C D E F G H J K L M N P R T U V VDDPETA (Power) VDDPEA (Power) VDDPEHA (Power) Signals 12 3 4 5 6 7 89 1 0 1 1 1 2 1 3 1 4 1 5 1 6 17 18 A B C D E F G H J K L M N P R T U V x No Connect XX X X X X XX XX X X

30 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet 19x19mm Package Drawing — 324-Pin AL324/AR324

31 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet 19x19mm Package Drawing — Page Two

32 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package Pinout, 27x27mm 676-BGA Signal Pinout The following table lists the pin numbers and signal names for the PES24T3G2 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B9 MSMBDAT C17 V DDI/O D25 V SS A2 V SS B10 SSMBADDR_2 C18 V SS D26 NC A3 V SS B11 SSMBADDR_5 C19 V DDI/O E1 V SS A4 JTAG_TDI B12 SSMBDAT C20 V SS E2 V SS A5 JTAG_TMS B13 V SS C21 V DDI/O E3 V SS A6 MSMBADDR_1 B14 SWMODE_0 C22 GPIO_10 E4 V SS A7 MSMBADDR_3 B15 SWMODE_2 C23 V DDI/O E5 V SS A8 MSMBCLK B16 V SS C24 V SS E6 V DDCORE A9 SSMBADDR_1 B17 V DDI/O C25 V SS E7 V DDCORE A10 SSMBADDR_3 B18 GPIO_00 1 C26 NC E8 V SS A11 SSMBCLK B19 GPIO_02 1 D1 PEREFCLKP E9 V DDCORE A12 CCLKUS B20 GPIO_04 1 D2 V SS E10 V SS A13 CCLKDS B21 GPIO_06 D3 V SS E11 V DDCORE A14 V SS B22 MSMBSMODE D4 V SS E12 V SS A15 SWMODE_1 B23 REFCLKM D5 V DDCORE E13 V DDCORE A16 NC B24 V DDI/O D6 V DDCORE E14 V SS A17 PERSTN B25 V SS D7 V SS E15 V DDCORE A18 RSTHALT B26 V SS D8 V DDCORE E16 V SS A19 GPIO_01 1 C1 PEREFCLKN D9 V SS E17 V DDCORE A20 GPIO_03 1 C2 V SS D10 V DDCORE E18 V SS A21 GPIO_05 C3 V SS D11 V SS E19 V DDCORE A22 GPIO_07 1 C4 V DDCORE D12 V DDCORE E20 V DDCORE A23 V SS C5 V DDI/O D13 V DDCORE E21 V DDCORE A24 GPIO_09 C6 V SS D14 V SS E22 V SS A25 V SS C7 V DDI/O D15 V DDCORE E23 V SS A26 V SS C8 V SS D16 V SS E24 V SS B1 V SS C9 V DDI/O D17 V DDCORE E25 V SS B2 V SS C10 V SS D18 V DDCORE E26 V SS B3 V DDI/O C11 V DDI/O D19 V DDCORE F1 V DDCORE B4 JTAG_TCK C12 V SS D20 V SS F2 V DDCORE B5 JTAG-TDO C13 V DDI/O D21 V DDCORE F3 V DDPEA B6 JTAG-TRST_N C14 V DDCORE D22 V DDCORE F4 V SS B7 MSMBADDR_2 C15 V DDI/O D23 GPIO_08 F5 V SS B8 MSMBADDR_4 C16 V DDCORE D24 V SS F6 V DDI/O Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 1 of 5)

33 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet F7 V SS G18 V SS J3 V DDPETA K14 V SS F8 V SS G19 V SS J4 PE2RN06 K15 V DDCORE F9 V SS G20 V SS J5 PE2RP06 K16 V DDCORE F10 V SS G21 V SS J6 V SS K17 V SS F11 V SS G22 PE4RP00 J7 V DDCORE K18 V SS F12 NC G23 PE4RN00 J8 V DDCORE K19 V DDCORE F13 V SS G24 V DDPETA J9 V SS K20 V DDCORE F14 V SS G25 PE4TP00 J10 V SS K21 V SS F15 V SS G26 PE4TN00 J11 V DDCORE K22 V DDPEA F16 NC H1 V SS J12 V DDCORE K23 V DDPEA F17 V SS H2 V SS J13 V SS K24 V DDPEA F18 V SS H3 V DDPEHA J14 V SS K25 V SS F19 V SS H4 V DDPEHA J15 V DDCORE K26 REFRES4 F20 V SS H5 V SS J16 V DDCORE L1 PE2TN05 F21 V SS H6 V SS J17 V SS L2 PE2TP05 F22 V SS H7 V DDCORE J18 V SS L3 V DDPETA F23 V SS H8 V DDCORE J19 V DDCORE L4 PE2RN05 F24 V DDPEA H9 V SS J20 V DDCORE L5 PE2RP05 F25 V DDCORE H10 V SS J21 V SS L6 V SS F26 V DDCORE H11 V DDCORE J22 PE4RP01 L7 V DDCORE G1 PE2TN07 H12 V DDCORE J23 PE4RN01 L8 V DDCORE G2 PE2TP07 H13 V SS J24 V DDPETA L9 V SS G3 V DDPETA H14 V SS J25 PE4TP01 L10 V SS G4 PE2RN07 H15 V DDCORE J26 PE4TN01 L11 V DDCORE G5 PE2RP07 H16 V DDCORE K1 REFRES3 L12 V DDCORE G6 V SS H17 V SS K2 V SS L13 V SS G7 V SS H18 V SS K3 V DDPEA L14 V SS G8 V SS H19 V DDCORE K4 V DDPEA L15 V DDCORE G9 V SS H20 V DDCORE K5 V DDPEA L16 V DDCORE G10 V SS H21 V SS K6 V SS L17 V SS G11 V SS H22 V SS K7 V DDCORE L18 V SS G12 V SS H23 V DDPEHA K8 V DDCORE L19 V DDCORE G13 V SS H24 V DDPEHA K9 V SS L20 V DDCORE G14 V SS H25 V SS K10 V SS L21 V SS G15 V SS H26 V SS K11 V DDCORE L22 PE4RP02 G16 V SS J1 PE2TN06 K12 V DDCORE L23 PE4RN02 G17 V SS J2 PE2TP06 K13 V SS L24 V DDPETA Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 2 of 5)

34 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet L25 PE4TP02 N10 V SS P21 V SS T6 NC L26 PE4TN02 N11 V DDCORE P22 V SS T7 V DDCORE M1 V DDCORE N12 V DDCORE P23 V DDPEHA T8 V DDCORE M2 V SS N13 V SS P24 V DDPEHA T9 V SS M3 V DDPEHA N14 V SS P25 V SS T10 V SS M4 V DDPEHA N15 V DDCORE P26 V DDCORE T11 V DDCORE M5 V SS N16 V DDCORE R1 PE2TN03 T12 V DDCORE M6 NC N17 V SS R2 PE2TP03 T13 V SS M7 V DDCORE N18 V SS R3 V DDPETA T14 V SS M8 V DDCORE N19 V DDCORE R4 PE2RN03 T15 V DDCORE M9 V SS N20 V DDCORE R5 PE2RP03 T16 V DDCORE M10 V SS N21 V SS R6 V SS T17 V SS M11 V DDCORE N22 PE4RP03 R7 V DDCORE T18 V SS M12 V DDCORE N23 PE4RN03 R8 V DDCORE T19 V DDCORE M13 V SS N24 V DDPETA R9 V SS T20 V DDCORE M14 V SS N25 PE4TP03 R10 V SS T21 NC M15 V DDCORE N26 PE4TN03 R11 V DDCORE T22 V SS M16 V DDCORE P1 V DDCORE R12 V DDCORE T23 V DDPEA M17 V SS P2 V SS R13 V SS T24 V DDPEA M18 V SS P3 V DDPEHA R14 V SS T25 V SS M19 V DDCORE P4 V DDPEHA R15 V DDCORE T26 V DDCORE M20 V DDCORE P5 V SS R16 V DDCORE U1 PE2TN02 M21 NC P6 V SS R17 V SS U2 PE2TP02 M22 V SS P7 V DDCORE R18 V SS U3 V DDPETA M23 V DDPEHA P8 V DDCORE R19 V DDCORE U4 PE2RN02 M24 V DDPEHA P9 V SS R20 V DDCORE U5 PE2RP02 M25 V SS P10 V SS R21 V SS U6 V SS M26 V DDCORE P11 V DDCORE R22 PE4RP04 U7 V DDCORE N1 PE2TN04 P12 V DDCORE R23 PE4RN04 U8 V DDCORE N2 PE2TP04 P13 V SS R24 V DDPETA U9 V SS N3 V DDPETA P14 V SS R25 PE4TP04 U10 V SS N4 PE2RN04 P15 V DDCORE R26 PE4TN04 U11 V DDCORE N5 PE2RP04 P16 V DDCORE T1 V DDCORE U12 V DDCORE N6 V SS P17 V SS T2 V SS U13 V SS N7 V DDCORE P18 V SS T3 V DDPEA U14 V SS N8 V DDCORE P19 V DDCORE T4 V DDPEA U15 V DDCORE N9 V SS P20 V DDCORE T5 V SS U16 V DDCORE Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 3 of 5)

35 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet U17 V SS W2 PE2TP01 Y13 V SS AA24 V DDPETA U18 V SS W3 V DDPETA Y14 V SS AA25 PE4TP07 U19 V DDCORE W4 PE2RN01 Y15 V DDCORE AA26 PE4TN07 U20 V DDCORE W5 PE2RP01 Y16 V DDCORE AB1 V SS U21 V SS W6 V SS Y17 V SS AB2 V SS U22 PE4RP05 W7 V DDCORE Y18 V SS AB3 V DDCORE U23 PE4RN05 W8 V DDCORE Y19 V DDCORE AB4 V DDCORE U24 V DDPETA W9 V SS Y20 V DDCORE AB5 V DDCORE U25 PE4TP05 W10 V SS Y21 V SS AB6 V SS U26 PE4TN05 W11 V DDCORE Y22 V SS AB7 PE0RP07 V1 V DDCORE W12 V DDCORE Y23 V DDPEHA AB8 V SS V2 V SS W13 V SS Y24 V DDPEHA AB9 PE0RP06 V3 V DDPEA W14 V SS Y25 V SS AB10 V DDPEA V4 V DDPEA W15 V DDCORE Y26 REFRES5 AB11 PE0RP05 V5 V DDPEA W16 V DDCORE AA1 PE2TN00 AB12 V SS V6 V SS W17 V SS AA2 PE2TP00 AB13 PE0RP04 V7 V DDCORE W18 V SS AA3 V DDPETA AB14 V DDPEA V8 V DDCORE W19 V DDCORE AA4 PE2RN00 AB15 PE0RP03 V9 V SS W20 V DDCORE AA5 PE2RP00 AB16 V SS V10 V SS W21 V SS AA6 V SS AB17 PE0RP02 V11 V DDCORE W22 PE4RP06 AA7 V SS AB18 V DDPEA V12 V DDCORE W23 PE4RN06 AA8 V SS AB19 PE0RP01 V13 V SS W24 V DDPETA AA9 V SS AB20 V SS V14 V SS W25 PE4TP06 AA10 V SS AB21 PE0RP00 V15 V DDCORE W26 PE4TN06 AA11 V SS AB22 V SS V16 V DDCORE Y1 REFRES2 AA12 NC AB23 V DDCORE V17 V SS Y2 V SS AA13 V SS AB24 V DDCORE V18 V SS Y3 V DDPEHA AA14 V SS AB25 V SS V19 V DDCORE Y4 V DDPEHA AA15 V SS AB26 V SS V20 V DDCORE Y5 V SS AA16 NC AC1 V SS V21 V SS Y6 V SS AA17 V SS AC2 V SS V22 V DDPEA Y7 V DDCORE AA18 V SS AC3 V DDCORE V23 V DDPEA Y8 V DDCORE AA19 V SS AC4 V DDCORE V24 V DDPEA Y9 V SS AA20 V SS AC5 V DDCORE V25 V SS Y10 V SS AA21 V SS AC6 V DDPEHA V26 V DDCORE Y11 V DDCORE AA22 PE4RP07 AC7 PE0RN07 W1 PE2TN01 Y12 V DDCORE AA23 PE4RN07 AC8 V DDPEA Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 4 of 5)

36 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet AC9 PE0RN06 AD7 V SS AE5 V SS AF3 V DDCORE AC10 V DDPEA AD8 V DDPETA AE6 V SS AF4 V DDCORE AC11 PE0RN05 AD9 V SS AE7 PE0TP07 AF5 V DDCORE AC12 V DDPEHA AD10 V DDPETA AE8 V SS AF6 V SS AC13 PE0RN04 AD11 V DDPETA AE9 PE0TP06 AF7 PE0TN07 AC14 V DDPEHA AD12 V DDPEHA AE10 V SS AF8 REFRES1 AC15 PE0RN03 AD13 V DDPETA AE11 PE0TP05 AF9 PE0TN06 AC16 V DDPEA AD14 V DDPEHA AE12 V SS AF10 V DDCORE AC17 PE0RN02 AD15 V DDPETA AE13 PE0TP04 AF11 PE0TN05 AC18 V DDPEA AD16 V DDPEA AE14 V SS AF12 V DDCORE AC19 PE0RN01 AD17 V SS AE15 PE0TP03 AF13 PE0TN04 AC20 V DDPEHA AD18 V DDPETA AE16 V SS AF14 V DDCORE AC21 PE0RN00 AD19 V DDPETA AE17 PE0TP02 AF15 PE0TN03 AC22 V SS AD20 V DDPEHA AE18 V SS AF16 V DDCORE AC23 V DDCORE AD21 V DDPETA AE19 PE0TP01 AF17 PE0TN02 AC24 V DDCORE AD22 V SS AE20 V SS AF18 REFRES0 AC25 V SS AD23 V DDCORE AE21 PE0TP00 AF19 PE0TN01 AC26 V SS AD24 V DDCORE AE22 V SS AF20 V SS AD1 V SS AD25 V SS AE23 V DDCORE AF21 PE0TN00 AD2 V SS AD26 V SS AE24 V DDCORE AF22 V SS AD3 V DDCORE AE1 V SS AE25 V SS AF23 V DDCORE AD4 V DDCORE AE2 V SS AE26 V SS AF24 V DDCORE AD5 V DDCORE AE3 V DDCORE AF1 V SS AF25 V SS AD6 V DDPEHA AE4 V DDCORE AF2 V SS AF26 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 26 PES24T3G2 (27x27mm 676-Pin) Signal Pin-Out (Part 5 of 5)

37 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package Core Power Pins (27x27mm 676-Pin Package) VDDCore V DDCore V DDCore V DDCore V DDCore V DDCore C4 H7 L16 P20 V7 AB24 C14 H8 L19 P26 V8 AC3 C16 H11 L20 R7 V11 AC4 D5 H12 M1 R8 V12 AC5 D6 H15 M7 R11 V15 AC23 D8 H16 M8 R12 V16 AC24 D10 H19 M11 R15 V19 AD3 D12 H20 M12 R16 V20 AD4 D13 J7 M15 R19 V26 AD5 D15 J8 M16 R20 W7 AD23 D17 J11 M19 T1 W8 AD24 D18 J12 M20 T7 W11 AE3 D19 J15 M26 T8 W12 AE4 D21 J16 N7 T11 W15 AE23 D22 J19 N8 T12 W16 AE24 E6 J20 N11 T15 W19 AF3 E7 K7 N12 T16 W20 AF4 E9 K8 N15 T19 Y7 AF5 E11 K11 N16 T20 Y8 AF10 E 1 3K 1 2N 1 9T 2 6Y 1 1 A F 1 2 E15 K15 N20 U7 Y12 AF14 E17 K16 P1 U8 Y15 AF16 E19 K19 P7 U11 Y16 AF23 E20 K20 P8 U12 Y19 AF24 E 2 1L 7P 1 1 U 1 5 Y 2 0 F1 L8 P12 U16 AB3 F2 L11 P15 U19 AB4 F25 L12 P16 U20 AB5 F26 L15 P19 V1 AB23 Table 27 PES24T3G2 (27x27mm 676-Pin) Core Power Pins

38 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package I/O, PCIe, and Transmitter Power Pins (27x27mm 676-Pin) VDDI/O V DDPEA V DDPEHA V DDPETA B3 F3 H3 G3 B17 F24 H4 G24 B24 K3 H23 J3 C5 K4 H24 J24 C7 K5 M3 L3 C9 K22 M4 L24 C11 K23 M23 N3 C13 K24 M24 N24 C15 T3 P3 R3 C17 T4 P4 R24 C19 T23 P23 U3 C21 T24 P24 U24 C23 V3 Y3 W3 F6 V4 Y4 W24 V5 Y23 AA3 V22 Y24 AA24 V23 AC6 AD8 V24 AC12 AD10 AB10 AC14 AD11 AB14 AC20 AD13 AB18 AD6 AD15 AC8 AD12 AD18 AC10 AD14 AD19 AC16 AD20 AD21 AC18 AD16 Table 28 PES24T3G2 (27x27mm 676-Pin) I/O, PCIe, Transmitter Power Pins

39 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package Ground Pins (27x27mm 676-Pin) Vss Vss V ss V ss V ss V ss V ss V ss A1 E1 G7 J17 N13 T25 Y17 AD1 A2 E2 G8 J18 N14 U6 Y18 AD2 A3 E3 G9 J21 N17 U9 Y21 AD7 A14 E4 G10 K2 N18 U10 Y22 AD9 A23 E5 G11 K6 N21 U13 Y25 AD17 A25 E8 G12 K9 P2 U14 AA6 AD22 A26 E10 G13 K10 P5 U17 AA7 AD25 B1 E12 G14 K13 P6 U18 AA8 AD26 B2 E14 G15 K14 P9 U21 AA9 AE1 B13 E16 G16 K17 P10 V2 AA10 AE2 B16 E18 G17 K18 P13 V6 AA11 AE5 B25 E22 G18 K21 P14 V9 AA13 AE6 B26 E23 G19 K25 P17 V10 AA14 AE8 C2 E24 G20 L6 P18 V13 AA15 AE10 C3 E25 G21 L9 P21 V14 AA17 AE12 C6 E26 H1 L10 P22 V17 AA18 AE14 C8 F4 H2 L13 P25 V18 AA19 AE16 C10 F5 H5 L14 R6 V21 AA20 AE18 C12 F7 H6 L17 R9 V25 AA21 AE20 C18 F8 H9 L18 R10 W6 AB1 AE22 C20 F9 H10 L21 R13 W9 AB2 AE25 C24 F10 H13 M2 R14 W10 AB6 AE26 C25 F11 H14 M5 R17 W13 AB8 AF1 D2 F13 H17 M9 R18 W14 AB12 AF2 D3 F14 H18 M10 R21 W17 AB16 AF6 D4 F15 H21 M13 T2 W18 AB20 AF20 D7 F17 H22 M14 T5 W21 AB22 AF22 D9 F18 H25 M17 T9 Y2 AB25 AF25 D11 F19 H26 M18 T10 Y5 AB26 AF26 D14 F20 J6 M22 T13 Y6 AC1 D16 F21 J9 M25 T14 Y9 AC2 D20 F22 J10 N6 T17 Y10 AC22 D24 F23 J13 N9 T18 Y13 AC25 D25 G6 J14 N10 T22 Y14 AC26 Table 29 PES24T3G2 (27x27mm 676-Pin) Ground Pins

40 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package Alternate Signal Functions (27x27mm 676-Pin) Option B Package No Connect Pins (27x27mm 676-Pin) Pin GPIO Alternate B18 GPIO[0] P2RSTN A19 GPIO[1] P4RSTN B19 GPIO[2] IOEXPINTN0 A20 GPIO[3] IOEXPINTN1 B20 GPIO[4] IOEXPINTN2 A22 GPIO[7] GPEN Table 30 PES24T3G2 (27x27mm 676-Pin) Alternate Signal Functions NC Pins A16 C26 D26 F12 F16 M21 T21 AA12 AA16 Table 31 PES24T3G2 (27x27mm 676-Pin) No Connect Pins

41 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package Signals Listed Alphabetically (27x27mm 676-Pin) Signal Name I/O Type Location Signal Category CCLKDS I A13 System CCLKUS I A12 GPIO_00 I/O B18 General Purpose Input/Output GPIO_01 I/O A19 GPIO_02 I/O B19 GPIO_03 I/O A20 GPIO_04 I/O B20 GPIO_05 I/O A21 GPIO_06 I/O B21 GPIO_07 I/O A22 GPIO_08 I/O D23 GPIO_09 I/O A24 GPIO_10 I/O C22 JTAG_TCK I B4 JTAG JTAG_TDI I A4 JTAG_TDO O B5 JTAG_TMS I A5 JTAG_TRST_N I B6 MSMBADDR_1 I A6 SMBus MSMBADDR_2 I B7 MSMBADDR_3 I A7 MSMBADDR_4 I B8 MSMBCLK I/O A8 MSMBDAT I/O B9 MSMBSMODE I B22 System NO CONNECT See Table 31 for a list of No Connect pins. Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 1 of 5)

42 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE0RN00 I AC21 PCI Express PE0RN01 I AC19 PE0RN02 I AC17 PE0RN03 I AC15 PE0RN04 I AC13 PE0RN05 I AC11 PE0RN06 I AC9 PE0RN07 I AC7 PE0RP00 I AB21 PE0RP01 I AB19 PE0RP02 I AB17 PE0RP03 I AB15 PE0RP04 I AB13 PE0RP05 I AB11 PE0RP06 I AB9 PE0RP07 I AB7 PE0TN00 O AF21 PE0TN01 O AF19 PE0TN02 O AF17 PE0TN03 O AF15 PE0TN04 O AF13 PE0TN05 O AF11 PE0TN06 O AF9 PE0TN07 O AF7 PE0TP00 O AE21 PE0TP01 O AE19 PE0TP02 O AE17 PE0TP03 O AE15 PE0TP04 O AE13 PE0TP05 O AE11 PE0TP06 O AE9 PE0TP07 O AE7 PE2RN00 I AA4 PE2RN01 I W4 PE2RN02 I U4 PE2RN03 I R4 Signal Name I/O Type Location Signal Category Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 2 of 5)

43 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE2RN04 I N4 PCI Express (cont.) PE2RN05 I L4 PE2RN06 I J4 PE2RN07 I G4 PE2RP00 I AA5 PE2RP01 I W5 PE2RP02 I U5 PE2RP03 I R5 PE2RP04 I N5 PE2RP05 I L5 PE2RP06 I J5 PE2RP07 I G5 PE2TN00 O AA1 PE2TN01 O W1 PE2TN02 O U1 PE2TN03 O R1 PE2TN04 O N1 PE2TN05 O L1 PE2TN06 O J1 PE2TN07 O G1 PE2TP00 O AA2 PE2TP01 O W2 PE2TP02 O U2 PE2TP03 O R2 PE2TP04 O N2 PE2TP05 O L2 PE2TP06 O J2 PE2TP07 O G2 PE4RN00 I G23 PE4RN01 I J23 PE4RN02 I L23 PE4RN03 I N23 PE4RN04 I R23 PE4RN05 I U23 PE4RN06 I W23 PE4RN07 I AA23 Signal Name I/O Type Location Signal Category Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 3 of 5)

44 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet PE4RP00 I G22 PCI Express (cont.) PE4RP01 I J22 PE4RP02 I L22 PE4RP03 I N22 PE4RP04 I R22 PE4RP05 I U22 PE4RP06 I W22 PE4RP07 I AA22 PE4TN00 O G26 PE4TN01 O J26 PE4TN02 O L26 PE4TN03 O N26 PE4TN04 O R26 PE4TN05 O U26 PE4TN06 O W26 PE4TN07 O AA26 PE4TP00 O G25 PE4TP01 O J25 PE4TP02 O L25 PE4TP03 O N25 PE4TP04 O R25 PE4TP05 O U25 PE4TP06 O W25 PE4TP07 O AA25 PEREFCLKN I C1 PEREFCLKP I D1 PERSTN I A17 System REFCLKM I B23 PCI Express REFRES0 I/O AF18 SerDes Reference Resistors REFRES1 I/O AF8 REFRES2 I/O Y1 REFRES3 I/O K1 REFRES4 I/O K26 REFRES5 I/O Y26 RSTHALT I A18 System Signal Name I/O Type Location Signal Category Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 4 of 5)

45 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet SSMBADDR_1 I A9 SMBus SSMBADDR_2 I B10 SSMBADDR_3 I A10 SSMBADDR_5 I B11 SSMBCLK I/O A11 SSMBDAT I/O B12 SWMODE_0 I B14 System SWMODE_1 I A15 SWMODE_2 I B15 V DDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA See Tables 27 and 28 for a listing of power pins. VSS See Table 29 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 32 PES24T3G2 (27x27mm 676-Pin) Alphabetical Signal List (Part 5 of 5)

46 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet Option B Package Pinout (27x27mm) — Top View 12 3 4 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 Vss (Ground) VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VDDPETA (Transmitter Power) VDDPEA (Analog Power) VDDPEHA (High Analog Power) Signals 12 3 4 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF X No Connect X X X X X X X X X X XX X X XX X X XX X X XX

47 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet 27x27mm Package Drawing — 676-Pin BL676/BR676

48 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet 27x27mm Package Drawing — Page Two

49 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet

Revision History

January 15, 2009: Publication of final data sheet. February 11, 2009: Revised AC Timing Characteristics table and DC Electrical Characteristics table to correct typos. March 6, 2009: Added industrial temperature. April 7, 2009: In Valid Combinations, changed ZB to ZC silicon for commercial temperature. February 2, 2010: Added new section Absolute Maximum Voltage Rating with table. September 13, 2010: In Table 8, changed Buffer type for PCI Express from CML to PCIe differential and changed reference clocks to HCSL. September 29, 2010: Corrected typo in Ordering Code for 324-ball Green FCBGA package, Industrial Temperature. January 20, 2011: Added new Table 25, Package Trace Length for 19x19mm FCBGA package. March 30, 2011: In Table 13, added VddPETA to footnote #1. September 4, 2012: Removed references to extra ports in Table 25. December 16, 2013: Changed the revision identifier to ZC from ZF in Ordering Information.

50 of 50 December 16, 2013 IDT 89HPES24T3G2 Datasheet CORPORATE HEADQUARTERS

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Ordering Information

Option A (19x19mm) Option B (27x27mm) 89HPES24T3G2ZCAL 324-ball FCBGA package, Commercial Temperature 89HPES24T3G2ZCALG 324-ball Green FCBGA package, Commercial Temperature 89HPES24T3G2ZCALI 324-ball FCBGA package, Industrial Temperature 89HPES24T3G2ZCALGI 324-ball Green FCBGA package, Industrial Temperature 89HPES24T3G2ZCBL 676-ball FCBGA package, Commercial Temperature 89HPES24T3G2ZCBLG 676-ball Green FCBG A package, Commercial Temperature 89HPES24T3G2ZCBLI 676-ball FCBGA package, Industrial Temperature 89HPES24T3G2ZCBLGI 676-ball Green FCBGA package, Industrial Temperature NN A AAA NNAN AA A Operating Voltage Product Detail Generation Package Temp Range H Product Family

89 Serial Switching Product

24T3 24-lane, 3-port 1.0V +/- 0.1V Core Voltage Series Legend A = Alpha Character N = Numeric Character AA Device Revision AN Device Family G2 PCIe Gen 2 PCI Express SwitchPES 676-ball FCBGA, GreenBLG 324-ball FCBGAAL 324-ball FCBGA, GreenALG ZC ZC revision Blank Commercial Temperature (0°C to +70°C Ambient) I Industrial Temperature (-40° C to +85° C Ambient)

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