89HPES24N3A

89HPES24N3A RENESAS | Alldatasheet

Document overview

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Technical content

Features

◆ High Performance PCI Express Switch – Twenty-four 2.5 Gbps PCI Express lanes – Three switch ports – Upstream port configurable up to x8 – Downstream ports configurable up to x8 – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ◆ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device conf iguration from serial EEPROM ◆ Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/ 10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protecti on on all TLPs ensures data integrity even in systems t hat do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram Figure 1 Internal Block Diagram x8 Upstream Port and Two x8 Downstream Ports SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer 3-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer

24 PCI Express Lanes

PCI Express® Switch

2 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specificat ion (PC I-PM 1.1)

• Supports device power management states: D0, D3 hot and D3cold – Unused SerDes are disabled ◆ Testability and Debug Features – Ability to read and write any in ternal register via the SMBus ◆ Eight General Purpose Input/Output Pins – Each pin may be individually co nfigured as an input or output – Each pin may be individually co nfigured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in 27x27mm 420 ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES24N3A provides the most efficient I/O c onnectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It pr ovides connectivity for up to 3 ports across 24 integrated serial l anes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1. SMBus Interface The PES24N3A contains two SMBus interfaces. The slave interface provides full access to the confi guration registers in the PES24N3A, allowing every configuration register in the device to be read or written by an external agent. The master inte rface allows the default configura- tion register values of the PES24N3A to be overridden following a reset with values programmed in an exte rnal serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the tw o SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interfac e, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pi ns allow the SMBus address of the serial configuration EEPROM from which data is loaded to be config- ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

Table 1 Master and Slave SMBus Address Assignment As shown in Figure 2, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 2(a), the master and slave SMBuses are tied together and the PES24N3A acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES24N3A registers suppor ts SMBus arbitration. In some systems, this SMBus master in terface may be implemented using general purpose I/O pins on a proces sor or micro controller, and may not support SMBus arbitration. To support these systems, the PES24N3A may be configured to operate in a split configuration as shown in Figure 2(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi- master arbitration is never required. The PES24N3A supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. 4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment

4 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Pin Description The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed o nto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES24N3A, the two downstream ports are labeled port 2 and port 4. Signal Type Name/Description PE0RP[7:0] PE0RN[7:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[7:0] PE0TN[7:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. Port 0 is the upstream port. PE2RP[7:0] PE2RN[7:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[7:0] PE2TN[7:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE4RP[7:0] PE4RN[7:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[7:0] PE4TN[7:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 4. PEREFCLKP[2:1] PEREFCLKN[2:1] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 2 PCI Express Interface Pins Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins

5 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output Table 4 General Purpose I/O Pins Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Table 5 System Pins (Part 1 of 2)

6 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES24N3A and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES24N3A executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES24N3A switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. Table 7 Power and Ground Pins Signal Type Name/Description Table 5 System Pins (Part 2 of 2)

7 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Pin Characteristics Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[7:0] I CML Serial link PE0RP[7:0] I PE0TN[7:0] O PE0TP[7:0] O PE2RN[7:0] I PE2RP[7:0] I PE2TN[7:0] O PE2TP[7:0] O PE4RN[7:0] I PE4RP[7:0] I PE4TN[7:0] O PE4TP[7:0] O PEREFCLKN[2:1] I LVPECL/ CML Diff. Clock Input Refer to Table 9 PEREFCLKP[2:1] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI 2 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[7:0] I/O LVTTL High Drive pull-up Table 8 Pin Characteristics (Part 1 of 2) Signal Type Name/Description Table 7 Power and Ground Pins

8 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-down 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2)

9 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Logic Diagram — PES24N3A Figure 4 PES24N3A Logic Diagram Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[7:0]

8 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[3:0] CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE PE0RP[0] PE0RN[0] PE0RP[7] PE0RN[7] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PE0TP[7] PE0TN[7] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE2RP[0] PE2RN[0] PE2RP[7] PE2RN[7] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PE2TP[7] PE2TN[7] PCI Express Switch SerDes Output ... Port 2 Port 2 ... PE4RP[0] PE4RN[0] PE4RP[7] PE4RN[7] PCI Express Switch SerDes Input PE4TP[0] PE4TN[0] PE4TP[7] PE4TN[7] PCI Express Switch SerDes Output ... Port 4 Port 4 ...PES24N3A SSMBADDR[5,3:1] SSMBCLK SSMBDAT Slave SMBus Interface

10 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. AC Timing Characteristics Parameter Description Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 9 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI Table 10 PCIe AC Timing Characteristics (Part 1 of 2)

11 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[7:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 11 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Parameter Description Min 1 Typical1 Max1 Units Table 10 PCIe AC Timing Characteristics (Part 2 of 2)

12 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Figure 5 JTAG AC Timing Waveform Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES24N3A, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Seri al Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES24N3A Operating Voltages Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

13 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Am bient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Thermal Considerations This section describes thermal considerations for the PES24N3A (27mm2 BXG420 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES24N3A switch. Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card. Grade Temperature Commercial 0 °C to +70°C Ambient Table 14 PES24N3A Operating Temperatures Number of active Lanes per Port Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V Typ Power Max Power 8/8/8 mA 705 928 1037 1247 415 455 520 617 1 1 2.9W 3.9W 8/4/4 mA 676 845 873 1004 409 434 360 408 1 1 2.5W 3.2W Table 15 PES24N3A Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 10.6 oC/W Zero air flow 8.5 oC/W 1 m/S air flow 7.6 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 6.8 oC/W θJC Thermal Resistance, Junction-to-Case 0.7 oC/W P Power Dissipation of the Device 3.9 Watts Maximum Table 16 Thermal Specifications for PES24N3A, 27x27 mm BXG420 Package

14 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES24N3A under three common usage scenarios. As shown in this table, a heat sink is not required in most cases. Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surrounding s in the absence of a heat sink. The general formula to determine θJA is: θJA = (TJ - TA)/P Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is: TJ(actual) = TA + P * θJA(eff) = 70oC + 3.9W * 8.5W/oC = 103oC The actual TJ of 103oC is well below the maximum T J of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should b e added to the device based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is: TA(allowed) = TJ(desired) - (P * θJA(effective)) TA(allowed) = 100oC - (3.9W * 8.5W/oC) = 100oC - 33oC = 67oC An appropriate level of increased air flow and/or a heat sink c an be added to achieve this lower ambient temperature. Please co ntact ssdhelp@idt.com for further assistance. Air Flow Board Size Board Layers Heat Sink Requirement Zero 3.9”x6.2” (ExpressModule form factor) or larger 10 or more No heat sink required Zero Any 14 or more No heat sink required 1 m/S or more Any Any No heat sink required Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics

15 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV Serial Link (cont.) VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 18 DC Electrical Characteristics (Part 1 of 2)

16 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 18 DC Electrical Characteristics (Part 2 of 2)

17 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet The following table lists the pin numbers and signal names for the PES24N3A device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B9 MSMBDAT C17 V DDIO D25 V SS A2 V SS B10 SSMBADDR_2 C18 V SS D26 PEREFCLKN2 A3 V SS B11 SSMBADDR_5 C19 V DDIO E1 V SS A4 JTAG_TDI B12 SSMBDAT C20 V SS E2 V SS A5 JTAG_TMS B13 NC C21 V DDIO E3 V SS A6 MSMBADDR_1 B14 SWMODE_0 C22 V SS E4 V SS A7 MSMBADDR_3 B15 SWMODE_2 C23 V DDIO E5 V SS A8 MSMBCLK B16 NC C24 V SS E6 V DDCORE A9 SSMBADDR_1 B17 V DDIO C25 V SS E7 V DDCORE A10 SSMBADDR_3 B18 GPIO_00 1 C26 PEREFCLKP2 E8 V SS A11 SSMBCLK B19 GPIO_02 1 D1 PEREFCLKP1 E9 V DDCORE A12 CCLKUS B20 GPIO_04 1 D2 V SS E10 V SS A13 CCLKDS B21 GPIO_06 D3 V SS E11 V DDCORE A14 NC B22 MSMBSMODE D4 V SS E12 V SS A15 SWMODE_1 B23 REFCLKM D5 V DDCORE E13 V DDCORE A16 SWMODE_3 B24 V DDIO D6 V DDCORE E14 V SS A17 PERSTN B25 V SS D7 V SS E15 V DDCORE A18 RSTHALT B26 V SS D8 V DDCORE E16 V SS A19 GPIO_01 1 C1 PEREFCLKN1 D9 V SS E17 V DDCORE A20 GPIO_03 C2 V SS D10 V DDCORE E18 V SS A21 GPIO_05 C3 V SS D11 V SS E19 V DDCORE A22 GPIO_07 1 C4 V DDCORE D12 V DDCORE E20 V DDCORE A23 V SS C5 V DDIO D13 V DDCORE E21 V DDCORE A24 V SS C6 V SS D14 V SS E22 V SS A25 V SS C7 V DDIO D15 V DDCORE E23 V SS A26 V SS C8 V SS D16 V SS E24 V SS B1 V SS C9 V DDIO D17 V DDCORE E25 V SS B2 V SS C10 V SS D18 V DDCORE E26 V SS B3 V DDIO C11 V DDIO D19 V DDCORE F1 V DDCORE B4 JTAG_TCK C12 V SS D20 V SS F2 V DDCORE B5 JTAG-TDO C13 V DDIO D21 V DDCORE F3 V DDAPE B6 JTAG-TRST_N C14 V DDCORE D22 V DDCORE F4 V SS B7 MSMBADDR_2 C15 V DDIO D23 V SS F5 V SS B8 MSMBADDR_4 C16 V DDCORE D24 V SS F22 V SS Table 19 PES24N3A 420-pin Signal Pin-Out (Part 1 of 3)

18 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet F23 V SS K4 V DDAPE P1 V DDCORE U24 V DDPE F24 V DDAPE K5 V DDAPE P2 V SS U25 PE4TP05 F25 V DDCORE K22 V DDAPE P3 V TTPE U26 PE4TN05 F26 V DDCORE K23 V DDAPE P4 V TTPE V1 V DDCORE G1 PE2TN07 K24 V DDAPE P5 V SS V2 V SS G2 PE2TP07 K25 V SS P22 V SS V3 V DDAPE G3 V DDPE K26 V SS P23 V TTPE V4 V DDAPE G4 PE2RN07 L1 PE2TN05 P24 V TTPE V5 V DDAPE G5 PE2RP07 L2 PE2TP05 P25 V SS V22 V DDAPE G22 PE4RP00 L3 V DDPE P26 V DDCORE V23 V DDAPE G23 PE4RN00 L4 PE2RN05 R1 PE2TN03 V24 V DDAPE G24 V DDPE L5 PE2RP05 R2 PE2TP03 V25 V SS G25 PE4TP00 L22 PE4RP02 R3 V DDPE V26 V DDCORE G26 PE4TN00 L23 PE4RN02 R4 PE2RN03 W1 PE2TN01 H1 V SS L24 V DDPE R5 PE2RP03 W2 PE2TP01 H2 V SS L25 PE4TP02 R22 PE4RP04 W3 V DDPE H3 V TTPE L26 PE4TN02 R23 PE4RN04 W4 PE2RN01 H4 V TTPE M1 V DDCORE R24 V DDPE W5 PE2RP01 H5 V SS M2 V SS R25 PE4TP04 W22 PE4RP06 H22 V SS M3 V TTPE R26 PE4TN04 W23 PE4RN06 H23 V TTPE M4 V TTPE T1 V DDCORE W24 V DDPE H24 V TTPE M5 V SS T2 V SS W25 PE4TP06 H25 V SS M22 V SS T3 V DDAPE W26 PE4TN06 H26 V SS M23 V TTPE T4 V DDAPE Y1 V SS J1 PE2TN06 M24 V TTPE T5 V SS Y2 V SS J2 PE2TP06 M25 V SS T22 V SS Y3 V TTPE J3 V DDPE M26 V DDCORE T23 V DDAPE Y4 V TTPE J4 PE2RN06 N1 PE2TN04 T24 V DDAPE Y5 V SS J5 PE2RP06 N2 PE2TP04 T25 V SS Y22 V SS J22 PE4RP01 N3 V DDPE T26 V DDCORE Y23 V TTPE J23 PE4RN01 N4 PE2R N04 U1 PE2TN02 Y24 V TTPE J24 V DDPE N5 PE2RP04 U2 PE2TP02 Y25 V SS J25 PE4TP01 N22 PE4RP03 U3 V DDPE Y26 V SS J26 PE4TN01 N23 PE4RN03 U4 PE2RN02 AA1 PE2TN00 K1 V SS N24 V DDPE U5 PE2RP02 AA2 PE2TP00 K2 V SS N25 PE4TP03 U22 PE4RP05 AA3 V DDPE K3 V DDAPE N26 PE4TN03 U23 PE4RN05 AA4 PE2RN00 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES24N3A 420-pin Signal Pin-Out (Part 2 of 3)

19 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet AA5 PE2RP00 AC3 V DDCORE AD11 V DDPE AE19 PE0TP01 AA22 PE4RP07 AC4 V DDCORE AD12 V TTPE AE20 V SS AA23 PE4RN07 AC5 V DDCORE AD13 V DDPE AE21 PE0TP00 AA24 V DDPE AC6 V TTPE AD14 V TTPE AE22 V SS AA25 PE4TP07 AC7 PE0RN07 AD15 V DDPE AE23 V DDCORE AA26 PE4TN07 AC8 V DDAPE AD16 V DDAPE AE24 V DDCORE AB1 V SS AC9 PE0RN06 AD17 V SS AE25 V SS AB2 V SS AC10 V DDAPE AD18 V DDPE AE26 V SS AB3 V DDCORE AC11 PE0RN05 AD19 V DDPE AF1 V SS AB4 V DDCORE AC12 V TTPE AD20 V TTPE AF2 V SS AB5 V DDCORE AC13 PE0RN04 AD21 V DDPE AF3 V DDCORE AB6 V SS AC14 V TTPE AD22 V SS AF4 V DDCORE AB7 PE0RP07 AC15 PE0RN03 AD23 V DDCORE AF5 V DDCORE AB8 V SS AC16 V DDAPE AD24 V DDCORE AF6 V SS AB9 PE0RP06 AC17 PE0RN02 AD25 V SS AF7 PE0TN07 AB10 V DDAPE AC18 V DDAPE AD26 V SS AF8 V SS AB11 PE0RP05 AC19 PE0RN01 AE1 V SS AF9 PE0TN06 AB12 V SS AC20 V TTPE AE2 V SS AF10 V DDCORE AB13 PE0RP04 AC21 PE0RN00 AE3 V DDCORE AF11 PE0TN05 AB14 V DDAPE AC22 V SS AE4 V DDCORE AF12 V DDCORE AB15 PE0RP03 AC23 V DDCORE AE5 V SS AF13 PE0TN04 AB16 V SS AC24 V DDCORE AE6 V SS AF14 V DDCORE AB17 PE0RP02 AC25 V SS AE7 PE0TP07 AF15 PE0TN03 AB18 V DDAPE AC26 V SS AE8 V SS AF16 V DDCORE AB19 PE0RP01 AD1 V SS AE9 PE0TP06 AF17 PE0TN02 AB20 V SS AD2 V SS AE10 V SS AF18 V SS AB21 PE0RP00 AD3 V DDCORE AE11 PE0TP05 AF19 PE0TN01 AB22 V SS AD4 V DDCORE AE12 V SS AF20 V SS AB23 V DDCORE AD5 V DDCORE AE13 PE0TP04 AF21 PE0TN00 AB24 V DDCORE AD6 V TTPE AE14 V SS AF22 V SS AB25 V SS AD7 V SS AE15 PE0TP03 AF23 V DDCORE AB26 V SS AD8 V DDPE AE16 V SS AF24 V DDCORE AC1 V SS AD9 V SS AE17 PE0TP02 AF25 V SS AC2 V SS AD10 V DDPE AE18 V SS AF26 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES24N3A 420-pin Signal Pin-Out (Part 3 of 3)

20 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Power Pins VDDCore V DDCore V DDCore V DDIO V DDPE V DDAPE V TTPE C4 F2 AE3 B3 G3 F3 H3 C14 F25 AE4 B17 G24 F24 H4 C16 F26 AE23 B24 J3 K3 H23 D5 M1 AE24 C5 J24 K4 H24 D6 M26 AF3 C7 L3 K5 M3 D8 P1 AF4 C9 L24 K22 M4 D10 P26 AF5 C11 N3 K23 M23 D12 T1 AF10 C13 N24 K24 M24 D13 T26 AF12 C15 R3 T3 P3 D15 V1 AF14 C17 R24 T4 P4 D17 V26 AF16 C19 U3 T23 P23 D18 AB3 AF23 C21 U24 T24 P24 D19 AB4 AF24 C23 W3 V3 Y3 D21 AB5 W24 V4 Y4 D22 AB23 AA3 V5 Y23 E6 AB24 AA24 V22 Y24 E7 AC3 AD8 V23 AC6 E9 AC4 AD10 V24 AC12 E11 AC5 AD11 AB10 AC14 E13 AC23 AD13 AB14 AC20 E15 AC24 AD15 AB18 AD6 E17 AD3 AD18 AC8 AD12 E19 AD4 AD19 AC10 AD14 E20 AD5 AD21 AC16 AD20 E21 AD23 AC18 F1 AD24 AD16 Table 20 PES24N3A Power Pins

21 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Ground Pins Vss Vss V ss V ss V ss A1 D9 F22 Y1 AD22 A2 D11 F23 Y2 AD25 A3 D14 H1 Y5 AD26 A23 D16 H2 Y22 AE1 A24 D20 H5 Y25 AE2 A25 D23 H22 Y26 AE5 A26 D24 H25 AB1 AE6 B1 D25 H26 AB2 AE8 B2 E1 K1 AB6 AE10 B25 E2 K2 AB8 AE12 B26 E3 K25 AB12 AE14 C2 E4 K26 AB16 AE16 C3 E5 M2 AB20 AE18 C6 E8 M5 AB22 AE20 C8 E10 M22 AB25 AE22 C10 E12 M25 AB26 AE25 C12 E14 P2 AC1 AE26 C18 E16 P5 AC2 AF1 C20 E18 P22 AC22 AF2 C22 E22 P25 AC25 AF6 C24 E23 T2 AC26 AF8 C25 E24 T5 AD1 AF18 D2 E25 T22 AD2 AF20 D3 E26 T25 AD7 AF22 D4 F4 V2 AD9 AF25 D7 F5 V25 AD17 AF26 Table 21 PES24N3A Ground Pins

22 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet Alternate Signal Functions Signals Listed Alphabetically Pin GPIO Alternate B18 GPIO_00 P2RSTN A19 GPIO_01 P4RSTN B19 GPIO_02 IOEXPINTN0 B20 GPIO_04 IOEXPINTN2 A22 GPIO_07 GPEN Table 22 PES24N3A Alternate Signal Functions Signal Name I/O Type Location Signal Category CCLKDS I A13 System CCLKUS I A12 GPIO_00 I/O B18 General Purpose Input/Output GPIO_01 I/O A19 GPIO_02 I/O B19 GPIO_03 I/O A20 GPIO_04 I/O B20 GPIO_05 I/O A21 GPIO_06 I/O B21 GPIO_07 I/O A22 JTAG_TCK I B4 JTAG JTAG_TDI I A4 JTAG_TMS I A5 JTAG-TDO O B5 JTAG-TRST_N I B6 MSMBADDR_1 I A6 SMBus MSMBADDR_2 I B7 MSMBADDR_3 I A7 MSMBADDR_4 I B8 MSMBCLK I/O A8 MSMBDAT I/O B9 MSMBSMODE I B22 System Table 23 89PES24N3A Alphabetical Signal List (Part 1 of 5)

23 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet NC A14 PCI Express NC B13 NC B16 PE0RN00 I AC21 PE0RN01 I AC19 PE0RN02 I AC17 PE0RN03 I AC15 PE0RN04 I AC13 PE0RN05 I AC11 PE0RN06 I AC9 PE0RN07 I AC7 PE0RP00 I AB21 PE0RP01 I AB19 PE0RP02 I AB17 PE0RP03 I AB15 PE0RP04 I AB13 PE0RP05 I AB11 PE0RP06 I AB9 PE0RP07 I AB7 PE0TN00 O AF21 PE0TN01 O AF19 PE0TN02 O AF17 PE0TN03 O AF15 PE0TN04 O AF13 PE0TN05 O AF11 PE0TN06 O AF9 PE0TN07 O AF7 PE0TP00 O AE21 PE0TP01 O AE19 PE0TP02 O AE17 PE0TP03 O AE15 PE0TP04 O AE13 PE0TP05 O AE11 PE0TP06 O AE9 PE0TP07 O AE7 Signal Name I/O Type Location Signal Category Table 23 89PES24N3A Alphabetical Signal List (Part 2 of 5)

24 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet PE2RN00 I AA4 PCI Express (Cont.) PE2RN01 I W4 PE2RN02 I U4 PE2RN03 I R4 PE2RN04 I N4 PE2RN05 I L4 PE2RN06 I J4 PE2RN07 I G4 PE2RP00 I AA5 PE2RP01 I W5 PE2RP02 I U5 PE2RP03 I R5 PE2RP04 I N5 PE2RP05 I L5 PE2RP06 I J5 PE2RP07 I G5 PE2TN00 O AA1 PE2TN01 O W1 PE2TN02 O U1 PE2TN03 O R1 PE2TN04 O N1 PE2TN05 O L1 PE2TN06 O J1 PE2TN07 O G1 PE2TP00 O AA2 PE2TP01 O W2 PE2TP02 O U2 PE2TP03 O R2 PE2TP04 O N2 PE2TP05 O L2 PE2TP06 O J2 PE2TP07 O G2 PE4RN00 I G23 PE4RN01 I J23 PE4RN02 I L23 PE4RN03 I N23 Signal Name I/O Type Location Signal Category Table 23 89PES24N3A Alphabetical Signal List (Part 3 of 5)

25 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet PE4RN04 I R23 PCI Express (Cont.) PE4RN05 I U23 PE4RN06 I W23 PE4RN07 I AA23 PE4RP00 I G22 PE4RP01 I J22 PE4RP02 I L22 PE4RP03 I N22 PE4RP04 I R22 PE4RP05 I U22 PE4RP06 I W22 PE4RP07 I AA22 PE4TN00 O G26 PE4TN01 O J26 PE4TN02 O L26 PE4TN03 O N26 PE4TN04 O R26 PE4TN05 O U26 PE4TN06 O W26 PE4TN07 O AA26 PE4TP00 O G25 PE4TP01 O J25 PE4TP02 O L25 PE4TP03 O N25 PE4TP04 O R25 PE4TP05 O U25 PE4TP06 O W25 PE4TP07 O AA25 PEREFCLKN1 I C1 PEREFCLKN2 I D26 PEREFCLKP1 I D1 PEREFCLKP2 I C26 PERSTN I A17 System REFCLKM I B23 PCI Express RSTHALT I A18 System Signal Name I/O Type Location Signal Category Table 23 89PES24N3A Alphabetical Signal List (Part 4 of 5)

26 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet SSMBADDR_1 I A9 SMBus SSMBADDR_2 I B10 SSMBADDR_3 I A10 SSMBADDR_5 I B11 SSMBCLK I/O A11 SMBus SSMBDAT I/O B12 SWMODE_0 I B14 System SWMODE_1 I A15 SWMODE_2 I B15 SWMODE_3 I A16 V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 20 for a listing of power pins. VSS See Table 21 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 23 89PES24N3A Alphabetical Signal List (Part 5 of 5)

27 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet PES24N3A Pinout — Top View 12 3 4 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals Not connected

28 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet

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30 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet

Revision History

February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Added ZG device revision to Ordering Information. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 25, 2008: Added θJB and θJC parameters to Table 16, Thermal Specifications. April 23, 2008: Added 1ZC device revision to Ordering Information.

31 of 31 April 23, 2008 IDT 89HPES24N3A Data Sheet CORPORATE HEADQUARTERS

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San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208

Ordering Information

89HPES24N3AZCBX 420-pin BX420 package, Commercial Temperature 89HPES24N3AZGBX 420-pin BX420 package, Commercial Temperature 89HPES24N3A1ZCBX 420-pin BX420 package, Commercial Temperature 89HPES24N3AZCBXG 420-pin Green BX420 package, Commercial Temperature 89HPES24N3AZGBXG 420-pin Green BX420 package, Commercial Temperature 89HPES24N3A1ZCBXG 420-pin Green BX420 package, Commercial Temperature NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

24N3A 24-lane, 3-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BXG420 420-ball BGA, Green BXG AAA Device Revision ZC ZC revision ZG ZG revision 1ZC 1ZC revision

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