89HPES24N3

89HPES24N3 IDT | Alldatasheet

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Features

◆ High Performance PCI Express Switch – 24 PCI Express lanes (2.5Gbps), 3 switch ports – Delivers 12 GBps (96 Gbps) aggregate switching capacity – Low latency cut-through switch architecture – Supports 128 to 2048 byte maximum payload size – Supports one virtual channel – PCI Express Base specification Revision 1.0a compliant ◆ Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin or weighted round robin algorithms – Supports automatic per port link with negotiation (x8, x4, x2, or x1) – Supports static lane reversal on all ports – Supports polarity inversion – Supports locked transactions, allowing use with legacy soft- ware – Ability to load device configuration from serial EEPROM ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates 24 2.5 Gbps embedded SerDes, 8B/10B encoder/ decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC passed through – Supports PCI Express Native Hot-Plug

• Compatible with Hot-Plug I/O expanders used on PC moth- erboards – Supports Hot-Swap ◆ Power Management – Supports PCI Express Power Management Interface specifi- cation, Revision 1.1 (PCI-PM) – Unused SerDes are disabled – Supports Advanced Configuration and Power Interface Speci- fication, Revision 2.0 (ACPI) supporting active link state ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus Block Diagram Figure 1 Internal Block Diagram

24 PCI Express Lanes

x8 Upstream Port and Two x8 Downstream Ports SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer 3-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer 89HPES24N3 Data Sheet 24-Lane 3-Port PCI Express® Switch

2 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is also used by an external Hot-Plug I/O expander – Master and slave interfaces may be tied together so the PES24N3 can act as both master and slave ◆ 8 General Purpose Input/Output pins ◆ Packaged in 27x27mm 420 ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES24N3 provides the most efficient high-performance I/O connectivity solution for applica- tions requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 12 GBps (96 Gbps) of aggregated, full-duplex switching capacity through 24 integrated serial lanes, using proven and r obust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a. The PES24N3 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management. This includes system selectable algorithms such as round robin, weighted round-robin, and st rict priority schemes guaranteeing bandwidth allocation and/or latency for critical traffic classes in applica- tions such as high throughput 10 Gigabit I/Os, SATA controllers, and Fibre Channel HBAs. Switch Configuration The PES24N3 is a three port switch that contains 24 PCI Express lanes. Each of the three ports is statically allocated 8 lanes with ports labeled as A, B and C. Port A is always the upstream port while ports B and C are always downstream ports. The switch operating mode, as well as an optional initialization from a serial EEPROM, is selected via the Switch Mode (SWMODE[3:0]) inputs. During link training, link width is automatically negotiated. Each PES24N3 port is capable of independently negotiating to a x8, x4, x2 or x1 width. Thus, the PES24N3 may be used in virtually any three port switch configuration (e.g., {x8, x8, x8}, {x4, x4, x4}, {x4, x2, x1}, etc.). The PES24N3 supports static lane re versal. For example, lane reversal for upstream port A may be configured by asserting the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for ports B and C may be enabled via a configuration space r egister, serial EEPROM, or the SMBus. Figure 2 I/O Expansion Application MemoryMemoryMemory Processor MemoryNorth Bridge PES24N3PES24N3 PES24N3 I/O 10GbE I/O 10GbE I/O SATA I/O SATAPCI Express Slots

3 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES24N3. Some of the functions listed may be multiplexed on to the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PEALREV I PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modify- ing the value of the PALREV bit in the PA_SWCTL register. PEARP[7:0] PEARN[7:0] I PCI Express Port A Serial Data Receive. Differential PCI Express receive pairs for port A. PEATP[7:0] PEATN[7:0 O PCI Express Port A Serial Data Transmit. Differential PCI Express trans- mit pairs for port A PEBLREV I PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of PCI Express Port B are reversed. This value may be overridden by modify- ing the value of the PBLREV bit in the PA_SWCTL register. PEBRP[7:0] PEBRN[7:0] I PCI Express Port B Serial Data Receive. Differential PCI Express receive pairs for port B. PEBTP[7:0] PEBTN[7:0] O PCI Express Port B Serial Data Transmit. Differential PCI Express trans- mit pairs for port B PECLREV I PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of PCI Express Port C are reversed. This value may be overridden by modify- ing the value of the PCLREV bit in the PA_SWCTL register. PECRP[7:0] PECRN[7:0] I PCI Express Port C Serial Data Receive. Differential PCI Express receive pairs for port C. PECTP[7:0] PECTN[7:0] O PCI Express Port C Serial Data Transmit. Differential PCI Express trans- mit pairs for port C PEREFCLKP[1:0] PEREFCLKN[1:0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. These signals select the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 1 PCI Express Interface Pins

4 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 2 SMBus Interface Pins Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN Alternate function pin type: Input Alternate function: Hot-Plug I/O expander interrupt input GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PAABN Alternate function pin type: Input Alternate function: Port A attention button input GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PAAIN Alternate function pin type: Output Alternate function: Port A attention indicator output GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PAPIN Alternate function pin type: Output Alternate function: Port A power indicator output GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 3 General Purpose I/O Pins

5 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be override by modifying the SCLK bit in the PB_PCIELSTS or PC_PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS register. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES24N3 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES24N3 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. TSTRSVD I Reserved. Reserved for future test mode. Must be tied to ground. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES24N3 switch operating mode. 0x0 - Transparent mode 0x1 -Transparent mode with serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - 10-bit loopback test mode 0x9 - Reserved 0xA - Internal pseudo random bit stream self-test test mode 0xB - External pseudo random bit stream self-test test mode 0xC - Reserved 0xD - SerDes broadcast test mode 0xE - 0xF Reserved Table 4 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 5 Test Pins (Part 1 of 2)

6 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 6 Power and Ground Pins Signal Type Name/Description Table 5 Test Pins (Part 2 of 2)

7 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Pin Characteristics Note: Some input pads of the PES24N3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor Notes PCI Express Inter- face PEALREV I LVTTL Input pull-down PEARN[7:0] I CML Serial link PEARP[7:0] I PEATN[7:0] O PEATP[7:0] O PEBLREV I LVTTL Input pull-down PEBRN[7:0] I CML Serial link PEBRP[7:0] I PEBTN[7:0] O PEBTP[7:0] O PECLREV I LVTTL Input pull-down PECRN[7:0] I CML Serial link PECRP[7:0] I PECTN[7:0] O PECTP[7:0] O PEREFCLKN[1:0] I LVPECL/ CML Diff. Clock Input Refer to Table 8PEREFCLKP[1:0] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI MSMBDAT I/O SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI SSMBDAT I/O General Purpose I/O GPIO[7:0] I/O LVTTL Input, High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down PERSTN I RSTHALT I pull-down TSTRSVD I pull-down External pulldown SWMODE[3:0] I pull-up Table 7 Pin Characteristics (Part 1 of 2)

8 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I pull-up JTAG_TDO O Low Drive JTAG_TMS I STI pull-up JTAG_TRST_N I pull-up External pulldown Function Pin Name Type Buffer I/O Type Internal Resistor Notes Table 7 Pin Characteristics (Part 2 of 2)

9 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Logic Diagram — PES24N3 Figure 3 PES24N3 Logic Diagram Reference Clock PEREFCLKP PEREFCLKN PEATP[0] PEATN[0] JTAG_TCK GPIO[7:0]

8 General Purpose

PEARP[0] PEARN[0] PEARP[1] PEARN[1] PEARP[7] PEARN[7] PCI Express Switch SerDes Input PEATP[1] PEATN[1] PEATP[7] PEATN[7] PCI Express Switch SerDes Output ... MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[3:0] Port A Port A PEBTP[0] PEBTN[0] PEBRP[0] PEBRN[0] PEBRP[1] PEBRN[1] PEBRP[7] PEBRN[7] PCI Express Switch SerDes Input PEBTP[1] PEBTN[1] PEBTP[7] PEBTN[7] PCI Express Switch SerDes Output ... ...Port B Port B PECTP[0] PECTN[0] PECRP[0] PECRN[0] PECRP[1] PECRN[1] PECRP[7] PECRN[7] PCI Express Switch SerDes Input PECTP[1] PECTN[1] PECTP[7] PECTN[7] PCI Express Switch SerDes Output ... Port C Port C PES24N3 PEALREV CCLKDS PEBLREV PECLREV PERSTN REFCLKM MSMBSMODE TSTRSVD VTTPE

10 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. AC Timing Characteristics Parameter Description Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps Table 8 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps T TX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-IDLE-RCV-DET- MAX Max time spend in idle before initiating a RX detect sequence 20 100 ms TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI Table 9 PCIe AC Timing Characteristics (Part 1 of 2)

11 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[7:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 10 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 4. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset sta te. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 11 JTAG AC Timing Characteristics Parameter Description Min 1 Typical1 Max1 Units Table 9 PCIe AC Timing Characteristics (Part 2 of 2)

12 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Figure 4 JTAG AC Timing Waveform Recommended Operating Supply Voltages Recommended Operating Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termina- tion Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 12 PES24N3 Operating Voltages Grade Temperature Commercial 0 °C to +70°C Ambient Table 13 PES24N3 Operating Temperatures Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

13 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. For the PES24N3, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the rev erse order of the power-up sequence. Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow. Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. Number of Connected Lanes: Port-A/Port-B/Port-C Core (Watts) (1.0V supply) PCIe Digital (Watts) (1.0V supply) PCIe Analog (Watts) (1.0V supply) PCIe Termin- ation (Watts) (1.5V supply) I/O (Watts) (3.3V supply) Total (Watts) Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Table 14 PES24N3 Power Consumption I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV Table 15 DC Electrical Characteristics (Part 1 of 3)

14 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Serial Link (cont.) VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL — 12.0 — mA V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 15 DC Electrical Characteristics (Part 2 of 3)

15 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 15 DC Electrical Characteristics (Part 3 of 3)

16 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet The following table lists the pin numbers and signal names for the PES24N3 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B9 MSMBDAT C17 V DDIO D25 V SS A2 V SS B10 SSMBADDR_2 C18 V SS D26 PEREFCLKN2 A3 V SS B11 SSMBADDR_5 C19 V DDIO E1 V SS A4 JTAG_TDI B12 SSMBDAT C20 V SS E2 V SS A5 JTAG_TMS B13 PEALREV C21 V DDIO E3 V SS A6 MSMBADDR_1 B14 SWMODE_0 C22 V SS E4 V SS A7 MSMBADDR_3 B15 SWMODE_2 C23 V DDIO E5 V SS A8 MSMBCLK B16 PECLREV C24 V SS E6 V DDCORE A9 SSMBADDR_1 B17 V DDIO C25 V SS E7 V DDCORE A10 SSMBADDR_3 B18 GPIO_00 C26 PEREFCLKP2 E8 V SS A11 SSMBCLK B19 GPIO_02 1 D1 PEREFCLKP1 E9 V DDCORE A12 CCLKUS B20 GPIO_04 1 D2 V SS E10 V SS A13 CCLKDS B21 GPIO_06 D3 V SS E11 V DDCORE A14 PEBLREV B22 MSMBSMODE D4 V SS E12 V SS A15 SWMODE_1 B23 REFCLKM D5 V DDCORE E13 V DDCORE A16 SWMODE_3 B24 V DDIO D6 V DDCORE E14 V SS A17 PERSTN B25 V SS D7 V SS E15 V DDCORE A18 RSTHALT B26 V SS D8 V DDCORE E16 V SS A19 GPIO_01 C1 PEREFCLKN1 D9 V SS E17 V DDCORE A20 GPIO_03 1 C2 V SS D10 V DDCORE E18 V SS A21 GPIO_05 1 C3 V SS D11 V SS E19 V DDCORE A22 GPIO_07 C4 V DDCORE D12 V DDCORE E20 V DDCORE A23 TSTRSVD C5 V DDIO D13 V DDCORE E21 V DDCORE A24 V SS C6 V SS D14 V SS E22 V SS A25 V SS C7 V DDIO D15 V DDCORE E23 V SS A26 V SS C8 V SS D16 V SS E24 V SS B1 V SS C9 V DDIO D17 V DDCORE E25 V SS B2 V SS C10 V SS D18 V DDCORE E26 V SS B3 V DDIO C11 V DDIO D19 V DDCORE F1 V DDCORE B4 JTAG_TCK C12 V SS D20 V SS F2 V DDCORE B5 JTAG-TDO C13 V DDIO D21 V DDCORE F3 V DDAPE B6 JTAG-TRST_N C14 V DDCORE D22 V DDCORE F4 V SS B7 MSMBADDR_2 C15 V DDIO D23 V SS F5 V SS B8 MSMBADDR_4 C16 V DDCORE D24 V SS F22 V SS Table 16 PES24N3 420-pin Signal Pin-Out (Part 1 of 3)

17 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet F23 V SS K4 V DDAPE P1 V DDCORE U24 V DDPE F24 V DDAPE K5 V DDAPE P2 V SS U25 PECTP05 F25 V DDCORE K22 V DDAPE P3 V TTPE U26 PECTN05 F26 V DDCORE K23 V DDAPE P4 V TTPE V1 V DDCORE G1 PEBTN07 K24 V DDAPE P5 V SS V2 V SS G2 PEBTP07 K25 V SS P22 V SS V3 V DDAPE G3 V DDPE K26 V SS P23 V TTPE V4 V DDAPE G4 PEBRN07 L1 PEBTN05 P24 V TTPE V5 V DDAPE G5 PEBRP07 L2 PEBTP05 P25 V SS V22 V DDAPE G22 PECRP00 L3 V DDPE P26 V DDCORE V23 V DDAPE G23 PECRN00 L4 PEBRN05 R1 PEBTN03 V24 V DDAPE G24 V DDPE L5 PEBRP05 R2 PEBTP03 V25 V SS G25 PECTP00 L22 PECRP02 R3 V DDPE V26 V DDCORE G26 PECTN00 L23 PECRN02 R4 PEBRN03 W1 PEBTN01 H1 V SS L24 V DDPE R5 PEBRP03 W2 PEBTP01 H2 V SS L25 PECTP02 R22 PECRP04 W3 V DDPE H3 V TTPE L26 PECTN02 R23 PECRN04 W4 PEBRN01 H4 V TTPE M1 V DDCORE R24 V DDPE W5 PEBRP01 H5 V SS M2 V SS R25 PECTP04 W22 PECRP06 H22 V SS M3 V TTPE R26 PECTN04 W23 PECRN06 H23 V TTPE M4 V TTPE T1 V DDCORE W24 V DDPE H24 V TTPE M5 V SS T2 V SS W25 PECTP06 H25 V SS M22 V SS T3 V DDAPE W26 PECTN06 H26 V SS M23 V TTPE T4 V DDAPE Y1 V SS J1 PEBTN06 M24 V TTPE T5 V SS Y2 V SS J2 PEBTP06 M25 V SS T22 V SS Y3 V TTPE J3 V DDPE M26 V DDCORE T23 V DDAPE Y4 V TTPE J4 PEBRN06 N1 PEBTN04 T24 V DDAPE Y5 V SS J5 PEBRP06 N2 PEBTP04 T25 V SS Y22 V SS J22 PECRP01 N3 V DDPE T26 V DDCORE Y23 V TTPE J23 PECRN01 N4 PEBRN04 U1 PEBTN02 Y24 V TTPE J24 V DDPE N5 PEBRP04 U2 PEBTP02 Y25 V SS J25 PECTP01 N22 PECRP03 U3 V DDPE Y26 V SS J26 PECTN01 N23 PECRN03 U4 PEBRN02 AA1 PEBTN00 K1 V SS N24 V DDPE U5 PEBRP02 AA2 PEBTP00 K2 V SS N25 PECTP03 U22 PECRP05 AA3 V DDPE K3 V DDAPE N26 PECTN03 U23 PECRN05 AA4 PEBRN00 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 16 PES24N3 420-pin Signal Pin-Out (Part 2 of 3)

18 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet AA5 PEBRP00 AC3 V DDCORE AD11 V DDPE AE19 PEATP01 AA22 PECRP07 AC4 V DDCORE AD12 V TTPE AE20 V SS AA23 PECRN07 AC5 V DDCORE AD13 V DDPE AE21 PEATP00 AA24 V DDPE AC6 V TTPE AD14 V TTPE AE22 V SS AA25 PECTP07 AC7 PEARN07 AD15 V DDPE AE23 V DDCORE AA26 PECTN07 AC8 V DDAPE AD16 V DDAPE AE24 V DDCORE AB1 V SS AC9 PEARN06 AD17 V SS AE25 V SS AB2 V SS AC10 V DDAPE AD18 V DDPE AE26 V SS AB3 V DDCORE AC11 PEARN05 AD19 V DDPE AF1 V SS AB4 V DDCORE AC12 V TTPE AD20 V TTPE AF2 V SS AB5 V DDCORE AC13 PEARN04 AD21 V DDPE AF3 V DDCORE AB6 V SS AC14 V TTPE AD22 V SS AF4 V DDCORE AB7 PEARP07 AC15 PEARN03 AD23 V DDCORE AF5 V DDCORE AB8 V SS AC16 V DDAPE AD24 V DDCORE AF6 V SS AB9 PEARP06 AC17 PEARN02 AD25 V SS AF7 PEATN07 AB10 V DDAPE AC18 V DDAPE AD26 V SS AF8 V SS AB11 PEARP05 AC19 PEARN01 AE1 V SS AF9 PEATN06 AB12 V SS AC20 V TTPE AE2 V SS AF10 V DDCORE AB13 PEARP04 AC21 PEARN00 AE3 V DDCORE AF11 PEATN05 AB14 V DDAPE AC22 V SS AE4 V DDCORE AF12 V DDCORE AB15 PEARP03 AC23 V DDCORE AE5 V SS AF13 PEATN04 AB16 V SS AC24 V DDCORE AE6 V SS AF14 V DDCORE AB17 PEARP02 AC25 V SS AE7 PEATP07 AF15 PEATN03 AB18 V DDAPE AC26 V SS AE8 V SS AF16 V DDCORE AB19 PEARP01 AD1 V SS AE9 PEATP06 AF17 PEATN02 AB20 V SS AD2 V SS AE10 V SS AF18 V SS AB21 PEARP00 AD3 V DDCORE AE11 PEATP05 AF19 PEATN01 AB22 V SS AD4 V DDCORE AE12 V SS AF20 V SS AB23 V DDCORE AD5 V DDCORE AE13 PEATP04 AF21 PEATN00 AB24 V DDCORE AD6 V TTPE AE14 V SS AF22 V SS AB25 V SS AD7 V SS AE15 PEATP03 AF23 V DDCORE AB26 V SS AD8 V DDPE AE16 V SS AF24 V DDCORE AC1 V SS AD9 V SS AE17 PEATP02 AF25 V SS AC2 V SS AD10 V DDPE AE18 V SS AF26 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 16 PES24N3 420-pin Signal Pin-Out (Part 3 of 3)

19 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Power Pins VDDCore V DDCore V DDCore V DDIO V DDPE V DDAPE V TTPE C4 F2 AE3 B3 G3 F3 H3 C14 F25 AE4 B17 G24 F24 H4 C16 F26 AE23 B24 J3 K3 H23 D5 M1 AE24 C5 J24 K4 H24 D6 M26 AF3 C7 L3 K5 M3 D8 P1 AF4 C9 L24 K22 M4 D10 P26 AF5 C11 N3 K23 M23 D12 T1 AF10 C13 N24 K24 M24 D13 T26 AF12 C15 R3 T3 P3 D15 V1 AF14 C17 R24 T4 P4 D17 V26 AF16 C19 U3 T23 P23 D18 AB3 AF23 C21 U24 T24 P24 D19 AB4 AF24 C23 W3 V3 Y3 D21 AB5 W24 V4 Y4 D22 AB23 AA3 V5 Y23 E6 AB24 AA24 V22 Y24 E7 AC3 AD8 V23 AC6 E9 AC4 AD10 V24 AC12 E11 AC5 AD11 AB10 AC14 E13 AC23 AD13 AB14 AC20 E15 AC24 AD15 AB18 AD6 E17 AD3 AD18 AC8 AD12 E19 AD4 AD19 AC10 AD14 E20 AD5 AD21 AC16 AD20 E21 AD23 AC18 F1 AD24 AD16 Table 17 PES24N3 Power Pins

20 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Ground Pins Vss Vss V ss V ss V ss A1 D11 F23 Y2 AD25 A2 D14 H1 Y5 AD26 A3 D16 H2 Y22 AE1 A24 D20 H5 Y25 AE2 A25 D23 H22 Y26 AE5 A26 D24 H25 AB1 AE6 B1 D25 H26 AB2 AE8 B2 E1 K1 AB6 AE10 B25 E2 K2 AB8 AE12 B26 E3 K25 AB12 AE14 C2 E4 K26 AB16 AE16 C3 E5 M2 AB20 AE18 C6 E8 M5 AB22 AE20 C8 E10 M22 AB25 AE22 C10 E12 M25 AB26 AE25 C12 E14 P2 AC1 AE26 C18 E16 P5 AC2 AF1 C20 E18 P22 AC22 AF2 C22 E22 P25 AC25 AF6 C24 E23 T2 AC26 AF8 C25 E24 T5 AD1 AF18 D2 E25 T22 AD2 AF20 D3 E26 T25 AD7 AF22 D4 F4 V2 AD9 AF25 D7 F5 V25 AD17 AF26 D9 F22 Y1 AD22 — Table 18 PES24N3 Ground Pins

21 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet Alternate Signal Functions Signals Listed Alphabetically Pin GPIO Alternate B19 GPIO[2] IOEXPINTN A20 GPIO[3] PAABN B20 GPIO[4] PAAIN A21 GPIO[5] PAPIN Table 19 PES24N3 Alternate Signal Functions Signal Name I/O Type Location Signal Category CCLKDS I A13 System CCLKUS I A12 GPIO_00 I/O B18 General Purpose Input/Output GPIO_01 I/O A19 GPIO_02 I/O B19 GPIO_03 I/O A20 GPIO_04 I/O B20 GPIO_05 I/O A21 GPIO_06 I/O B21 GPIO_07 I/O A22 JTAG_TCK I B4 JTAG JTAG_TDI I A4 JTAG_TMS I A5 JTAG-TDO O B5 JTAG-TRST_N I B6 MSMBADDR_1 I A6 SMBus MSMBADDR_2 I B7 MSMBADDR_3 I A7 MSMBADDR_4 I B8 MSMBCLK I/O A8 MSMBDAT I/O B9 MSMBSMODE I B22 System Table 20 89PES24N3 Alphabetical Signal List (Part 1 of 5)

22 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet PEALREV I B13 PCI Express PEARN00 I AC21 PEARN01 I AC19 PEARN02 I AC17 PEARN03 I AC15 PEARN04 I AC13 PEARN05 I AC11 PEARN06 I AC9 PEARN07 I AC7 PEARP00 I AB21 PEARP01 I AB19 PEARP02 I AB17 PEARP03 I AB15 PEARP04 I AB13 PEARP05 I AB11 PEARP06 I AB9 PEARP07 I AB7 PEATN00 O AF21 PEATN01 O AF19 PEATN02 O AF17 PEATN03 O AF15 PEATN04 O AF13 PEATN05 O AF11 PEATN06 O AF9 PEATN07 O AF7 PEATP00 O AE21 PEATP01 O AE19 PEATP02 O AE17 PEATP03 O AE15 PEATP04 O AE13 PEATP05 O AE11 PEATP06 O AE9 PEATP07 O AE7 PEBLREV I A14 PEBRN00 I AA4 PEBRN01 I W4 Signal Name I/O Type Location Signal Category Table 20 89PES24N3 Alphabetical Signal List (Part 2 of 5)

23 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet PEBRN02 I U4 PCI Express PEBRN03 I R4 PEBRN04 I N4 PEBRN05 I L4 PEBRN06 I J4 PEBRN07 I G4 PEBRP00 I AA5 PEBRP01 I W5 PEBRP02 I U5 PEBRP03 I R5 PEBRP04 I N5 PEBRP05 I L5 PEBRP06 I J5 PEBRP07 I G5 PEBTN00 O AA1 PEBTN01 O W1 PEBTN02 O U1 PEBTN03 O R1 PEBTN04 O N1 PEBTN05 O L1 PEBTN06 O J1 PEBTN07 O G1 PEBTP00 O AA2 PEBTP01 O W2 PEBTP02 O U2 PEBTP03 O R2 PEBTP04 O N2 PEBTP05 O L2 PEBTP06 O J2 PEBTP07 O G2 PECLREV I B16 PECRN00 I G23 PECRN01 I J23 PECRN02 I L23 PECRN03 I N23 PECRN04 I R23 Signal Name I/O Type Location Signal Category Table 20 89PES24N3 Alphabetical Signal List (Part 3 of 5)

24 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet PECRN05 I U23 PCI Express PECRN06 I W23 PECRN07 I AA23 PECRP00 I G22 PECRP01 I J22 PECRP02 I L22 PECRP03 I N22 PECRP04 I R22 PECRP05 I U22 PECRP06 I W22 PECRP07 I AA22 PECTN00 O G26 PECTN01 O J26 PECTN02 O L26 PECTN03 O N26 PECTN04 O R26 PECTN05 O U26 PECTN06 O W26 PECTN07 O AA26 PECTP00 O G25 PECTP01 O J25 PECTP02 O L25 PECTP03 O N25 PECTP04 O R25 PECTP05 O U25 PECTP06 O W25 PECTP07 O AA25 PEREFCLKN1 I C1 PEREFCLKN2 I D26 PEREFCLKP1 I D1 PEREFCLKP2 I C26 PERSTN I A17 System REFCLKM I B23 PCI Express RSTHALT I A18 System Signal Name I/O Type Location Signal Category Table 20 89PES24N3 Alphabetical Signal List (Part 4 of 5)

25 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet SSMBADDR_1 I A9 SMBus SSMBADDR_2 I B10 SSMBADDR_3 I A10 SSMBADDR_5 I B11 TSTRSVD I A23 System SSMBCLK I/O A11 SMBus SSMBDAT I/O B12 SWMODE_0 I B14 System SWMODE_1 I A15 SWMODE_2 I B15 SWMODE_3 I A16 System V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 17 for a listing of power pins. VSS See Table 18 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 20 89PES24N3 Alphabetical Signal List (Part 5 of 5)

26 of 30 July 18, 2006 IDT 89HPES24N3 Data Sheet PES24N3 Pinout — Top View 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 41 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals

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Revision History

July 18, 2006: Publication of YC data sheet.

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Ordering Information

89HPES24N3YCBX 420-pin BX420 package, Commercial Temperature 89HPES24N3YCBXG 420-pin Green BX420 package, Commercial Temperature NN AA A A NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

24N3 24-lane, 3-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BXG420 420-ball BGA, Green BXG AA Revision ID YC Silicon revision