89HPES16T7

89HPES16T7 RENESAS | Alldatasheet

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Features

‹ High Performance PCI Express Switch – Sixteen 2.5 Gbps PCI Express lanes – Seven switch ports – Upstream port configurable up to x8 – Two downstream ports configur able up to x4, four downstream ports are x1 – Low-latency cut-through switch architecture – Support for Max Payload Sizes up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ‹ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device conf iguration from serial EEPROM ‹ Legacy Support – PCI compatible INTx emulation – Bus locking ‹ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) ‹ Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protec tion on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC and server motherboards ‹ Power Management – Utilizes advanced low-power desi gn techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI- PM 1.1)

• Supports device power management states: D0, D3 hot and D3cold – Unused SerDes are disabled Block Diagram Figure 1 Internal Block Diagram 7-Port Switch Core / 16 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer (Port 0) (Port 1) (Port 2) SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer (Port 6) SerDes Phy Logical Layer (Port 5) TL DLL Mux/Demux SerDes Phy Logical Layer TL DLL Mux/Demux 89HPES16T7 Data Sheet 16-Lane 7-Port PCI Express® Switch

3 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet SMBus Interface The PES16T7 contains two SMBus interfaces. T he slave interface provides full access to the configuration registers in the PES16 T7, allowing every configuration r egister in the device to be read or written by an exte rnal agent. The master interface allows the default configuration register values of the PES16T7 to be overridden following a reset with val ues programmed in an external se rial EEPROM. The master interf ace is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master in terface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corr esponding address pins. When the pins are sa mpled, the resulting address is assigned as shown in Table 1. As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 4(a), the master and slave SMBuses are tied together and the PES16T7 acts both as a SMBus master as well as a SMBus slave on th is bus. This requires that the SMBus master or processor that has access to PES16T7 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general pur pose I/O pins on a processor or micro c ontroller, and may not support SMBus arbitration. To support these systems, the PES16T7 may be configured to operate in a split configuration as shown in Figure 4(b). In the split configuration, the master and slave SMBuses oper ate as two independent buses and thus multi-master arbitration is never required. The PES16T7 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. Figure 4 SMBus Interface Configuration Examples Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment Processor PES16T7 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM Processor PES16T7 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses

4 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Hot-Plug Interface The PES16T7 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES 16T7 utilizes an external I/O expander, such as that used on PC mother boards, connected to the SMBus mast er interface. Following res et and configura- tion, whenever the state of a Hot-Plug out put needs to be modified, the PES16T7 generat es an SMBus transaction to the I/O expan der with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES16T7. In response to an I/O expander interrupt, the PES16T7 generates an SMBus transacti on to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES16T7 provides 12 General Purpose Inpu t/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip fu nctions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Pin Description The following tables lists the functions of the pins provided on the PES16T7. Some of the functions listed may be multiplexed o nto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. PE1RP[3:0] PE1RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. PE1TP[3:0] PE1TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 1. PE2RP[0] PE2RN[0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[0] PE2TN[0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE3RP[0] PE3RN[0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PE3TP[0] PE3TN[0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans- mit pair for port 3. PE4RP[0] PE4RN[0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair for port 4. PE4TP[0] PE4TN[0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pair for port 4. PE5RP[0] PE5RN[0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pair for port 5. PE5TP[0] PE5TN[0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans- mit pair for port 5. PE6RP[3:0] PE6RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pair for port 6. Table 2 PCI Express Interface Pins (Part 1 of 2)

5 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet PE6TP[3:0] PE6TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- mit pair for port 6. PEREFCLKP[2:1] PEREFCLKN[2:1] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input Table 4 General Purpose I/O Pins (Part 1 of 2) Signal Type Name/Description Table 2 PCI Express Interface Pins (Part 2 of 2)

6 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: I/O Expander interrupt 1 input GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: I/O Expander interrupt 3 input GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 Signal Type Name/Description Table 4 General Purpose I/O Pins (Part 2 of 2)

7 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 kHz. This value may not be overridden. P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each oper- ates as a single x4 port PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES16T7 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES16T7 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES16T7 switch operating mode. These pins should be static and not change after the negation of PERSTN. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Table 5 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 6 Test Pins (Part 1 of 2)

8 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Signal Type Name/Description Table 6 Test Pins (Part 2 of 2)

9 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Signal Type Name/Description VDDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 7 Power and Ground Pins

10 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Pin Characteristics Note: Some input pads of the PES16T7 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[3:0] I CML Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE1RN[3:0] I PE1RP[3:0] I PE1TN[3:0] O PE1TP[3:0] O PE2RN[0] I PE2RP[0] I PE2TN[0] O PE2TP[0] O PE3RN[0] I PE3RP[0] I PE3TN[0] O PE3TP[0] O PE4RN[0] I PE4RP[0] I PE4TN[0] O PE4TP[0] O PE5RN[0] I PE5RP[0] I PE5TN[0] O PE5TP[0] O PE6RN[3:0] I PE6RP[3:0] I PE6TN[3:0] O PE6TP[3:0] O PEREFCLKN[2:1] I LVPECL/ CML Diff Clock Input Refer to Table 9 PEREFCLKP[2:1] I REFCLKM I LVTTL Input pull-down Table 8 Pin Characteristics (Part 1 of 2)

11 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI 2 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[11:0] I/O LVTTL High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down P01MERGEN I pull-down PERSTN I RSTHALT I pull-down SWMODE[2:0] I pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-down 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2)

12 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Logic Diagram — PES16T7 Figure 5 PES16T7 Logic Diagram Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[11:0]

12 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[2:0] CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE1RP[0] PE1RN[0] PE1RP[3] PE1RN[3] PCI Express Switch SerDes Input PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PCI Express Switch SerDes Output ... Port 1 Port 1 ... PE3RP[0] PE3RN[0] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PCI Express Switch SerDes Output Port 3 Port 2 PES16T7 PE2RP[0] PE2RN[0] PCI Express Switch SerDes Input Port 2 PE4RP[0] PE4RN[0] PCI Express Switch SerDes Input Port 4 PE5RP[0] PE5RN[0] PCI Express Switch SerDes Input Port 5 PE6RP[0] PE6RN[0] PE6RP[3] PE6RN[3] PCI Express Switch SerDes Input ... Port 6 PE3TP[0] PE3TN[0] PCI Express Switch SerDes Output Port 3 PE4TP[0] PE4TN[0] PCI Express Switch SerDes Output Port 4 PE5TP[0] PE5TN[0] PCI Express Switch SerDes Output Port 5 PE6TP[0] PE6TN[0] PE6TP[3] PE6TN[3] PCI Express Switch SerDes Output Port 6 ... P01MERGEN

13 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. AC Timing Characteristics Parameter Description Min Typical Max Unit PEREFCLK RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 9 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns Table 10 PCIe AC Timing Characteristics

14 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Figure 6 GPIO AC Timing Waveform 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[11:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns See Figure 6. Table 11 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 7. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Tdo_13aTdo_13a Tpw_13b EXTCLK GPIO (synchronous output) GPIO (asynchronous input)

15 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Figure 7 JTAG AC Timing Waveform Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES16T7, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES16T7 Operating Voltages Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

16 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Am bient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Thermal Considerations This section describes thermal considerations for the PES16T7 (25mm2 BXG320 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES16T7 switch. Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card. Grade Temperature Commercial 0 °C to +70°C Ambient Table 14 PES16T7 Operating Temperatures Number of active Lanes per Port Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V Typ Power Max Power 8/4/1/1/1/1 mA 793 1013 974 1123 486 522 369 419 1 1 2.8W 3.6W Table 15 PES16T7 Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 12.8 oC/W Zero air flow 10.1 oC/W 1 m/S air flow 9.1 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 7.5 oC/W θJC Thermal Resistance, Junction-to-Case 0.7 oC/W P Power Dissipation of the Device 3.6 Watts Maximum Table 16 Thermal Specifications for PES16T7, 25x25 mm BXG320 Package

17 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES16T7 under two comm on usage scenarios. As shown in this table, a heat sink is not required in most cases. Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surrounding s in the absence of a heat sink. The general formula to determine θJA is: θJA = (TJ - TA)/P Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is: TJ(actual) = TA + P * θJA(eff) = 70oC + 3.6W * 10.1W/oC = 106oC The actual TJ of 106oC is well below the maximum T J of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should b e added to the device based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is: TA(allowed) = TJ(desired) - (P * θJA(effective)) TA(allowed) = 100oC - (3.6W * 10.1W/oC) = 100oC - 36oC = 64oC An appropriate level of increased air flow and/or a heat sink c an be added to achieve this lower ambient temperature. Please co ntact ssdhelp@idt.com for further assistance. Air Flow Board Size Board Layers Heat Sink Requirement Zero 3.9”x6.2” (ExpressModule form factor) or larger 10 or more No heat sink required 1 m/S or more Any Any No heat sink required Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics

18 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 18 DC Electrical Characteristics (Part 1 of 2)

19 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 18 DC Electrical Characteristics (Part 2 of 2)

20 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet The following table lists the pin numbers and signal names for the PES16T7 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B11 V SS C21 V DDCORE E23 V DDPE A2 V SS B12 PE6TP02 C22 V SS E24 V DDCORE A3 V DDCORE B13 V SS C23 V SS F1 V SS A4 V DDCORE B14 PE6TN03 C24 V DDCORE F2 V DDAPE A5 V SS B15 V SS D1 V DDCORE F3 V DDIO A6 V DDCORE B16 V DDAPE D2 V SS F4 V SS A7 V SS B17 V DDAPE D3 V DDCORE F21 V DDAPE A8 PE6TP00 B18 MSMBSMODE D4 V DDPE F22 V DDAPE A9 V DDCORE B19 V DDIO D5 V DDPE F23 V DDPE A10 PE6TN01 B20 V DDCORE D6 V SS F24 V SS A11 V SS B21 V SS D7 PE6RP00 G1 V DDCORE A12 PE6TN02 B22 V DDCORE D8 V SS G2 V DDAPE A13 V SS B23 V DDCORE D9 V TTPE G3 V DDPE A14 PE6TP03 B24 V SS D10 V SS G4 P01MERGEN A15 V SS C1 V SS D11 PE6RN01 G21 GPIO_11 1 A16 V DDCORE C2 V DDCORE D12 V DDAPE G22 GPIO_10 1 A17 V SS C3 V SS D13 PE6RP02 G23 V DDPE A18 V DDCORE C4 V DDAPE D14 V TTPE G24 V DDCORE A19 V DDCORE C5 V DDPE D15 PE6RP03 H1 V SS A20 V SS C6 V SS D16 V SS H2 V DDAPE A21 V DDCORE C7 PE6RN00 D17 V TTPE H3 V DDAPE A22 V SS C8 V SS D18 V DDPE H4 V TTPE A23 V DDCORE C9 V SS D19 V DDAPE H21 GPIO_09 1 A24 V SS C10 V DDPE D20 V DDCORE H22 GPIO_08 1 B1 V DDCORE C11 PE6RP01 D21 V SS H23 V DDAPE B2 V DDCORE C12 V DDAPE D22 V DDCORE H24 V SS B3 V DDCORE C13 PE6RN02 D23 V DDCORE J1 PEREFCLKN1 B4 V DDAPE C14 V SS D24 V SS J2 V SS B5 V DDCORE C15 PE6RN03 E1 V SS J3 V SS B6 V DDIO C16 V DDPE E2 V DDAPE J4 V SS B7 V SS C17 V DDPE E3 V DDIO J21 V DDAPE B8 PE6TN00 C18 REFCLKM E4 V DDCORE J22 V DDAPE B9 V SS C19 V DDPE E21 V DDIO J23 V DDAPE B10 PE6TP01 C20 V DDAPE E22 V DDIO J24 PEREFCLKP2 Table 19 PES16T7 320-pin Signal Pin-Out (Part 1 of 3)

21 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet K1 PEREFCLKP1 P22 PE5RN00 W3 SSMBADDR_3 AA24 V DDIO K2 V DDPE P23 V SS W4 SSMBADDR_5 AB1 V DDCORE K3 V DDPE P24 V SS W21 PERSTN AB2 V DDIO K4 V DDPE R1 V SS W22 SWMODE1 AB3 V DDPE K21 V SS R2 V SS W23 SWMODE_0 AB4 PE1RN03 K22 V SS R3 PE2RP00 W24 RSTHALT AB5 V SS K23 V SS R4 PE2RN00 Y1 SSMBDAT AB6 PE1RN02 K24 PEREFCKN2 R21 V TTPE Y2 V DDIO AB7 V DDAPE L1 V SS R22 V DDPE Y3 V DDPE AB8 PE1RP01 L2 V SS R23 PE5TN00 Y4 CCLKUS AB9 V SS L3 V DDAPE R24 PE5TP00 Y21 V SS AB10 V SS L4 V DDAPE T1 JTAG_TMS Y22 V DDAPE AB11 V SS L21 V SS T2 JTAG_TCK Y23 V DDIO AB12 PE1RN00 L22 V DDPE T3 JTAG_TDI Y24 CCLKDS AB13 V DDAPE L23 V DDPE T4 JTAG_TDO AA1 V DDCORE AB14 PE0RN03 L24 V SS T21 GPIO_07 1 AA2 V DDIO AB15 V SS M1 PE3TN00 T22 V DDAPE AA3 V SS AB16 V DDPE M2 PE3TP00 T23 V DDPE AA4 PE1RP03 AB17 PE0RN02 M3 V TTPE T24 GPIO_06 AA5 V TTPE AB18 V DDPE M4 V DDPE U1 MSMBADDR_3 AA6 PE1RP02 AB19 PE0RN01 M21 PE4RP00 U2 JTAG_TRST_N AA7 V SS AB20 V SS M22 PE4RN00 U3 MSMBADDR_1 AA8 PE1RN01 AB21 PE0RN00 M23 V SS U4 MSMBADDR_2 AA9 V DDAPE AB22 V DDAPE M24 V SS U21 GPIO_04 1 AA10 V SS AB23 V DDAPE N1 V SS U22 GPIO_05 1 AA11 V TTPE AB24 V DDCORE N2 V SS U23 GPIO_03 1 AA12 PE1RP00 AC1 V SS N3 PE3RP00 U24 GPIO_02 1 AA13 V SS AC2 V DDIO N4 PE3RN00 V1 SSMBADDR_ 1 AA14 PE0RP03 AC3 V DDAPE N21 V TTPE V2 MSMBADDR_4 AA15 V TTPE AC4 V SS N22 V SS V3 MSMBCLK AA16 V SS AC5 PE1TN03 N23 PE4TN00 V4 MSMBDAT AA17 PE0RP02 AC6 V SS N24 PE4TP00 V21 GPIO_00 1 AA18 V DDAPE AC7 PE1TP02 P1 PE2TN00 V22 GPIO_01 1 AA19 PE0RP01 AC8 V SS P2 PE2TP00 V23 V SS AA20 V TTPE AC9 PE1TP01 P3 V DDPE V24 SWMODE_2 AA21 PE0RP00 AC10 V SS P4 V DDPE W1 SSMBCLK AA22 V DDPE AC11 PE1TN00 P21 PE5RP00 W2 SSMBADDR_2 AA23 V DDPE AC12 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES16T7 320-pin Signal Pin-Out (Part 2 of 3)

22 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Alternate Signal Functions AC13 PE0TP03 AC22 V DDPE AD7 PE1TN02 AD16 PE0TN02 AC14 V SS AC23 V DDPE AD8 V SS AD17 V SS AC15 V SS AC24 V DDCORE AD9 PE1TN01 AD18 PE0TN01 AC16 PE0TP02 AD1 V SS AD10 V SS AD19 V SS AC17 V SS AD2 V DDCORE AD11 PE1TP00 AD20 PE0TP00 AC18 PE0TP01 AD3 V DDCORE AD12 V SS AD21 V SS AC19 V SS AD4 V SS AD13 PE0TN03 AD22 V DDCORE AC20 PE0TN00 AD5 PE1TP03 AD14 V SS AD23 V SS AC21 V SS AD6 V SS AD15 V DDCORE AD24 V SS Pin GPIO Alternate V21 GPIO_00 P2RSTN V22 GPIO_01 P4RSTN U24 GPIO_02 IOEXPINTN0 U23 GPIO_03 IOEXPINTN1 U21 GPIO_04 IOEXPINTN2 U22 GPIO_05 IOEXPINTN3 T21 GPIO_07 GPEN H22 GPIO_08 P1RSTN H21 GPIO_09 P3RSTN G22 GPIO_10 P5RSTN G21 GPIO_11 P6RSTN Table 20 PES16T7 Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES16T7 320-pin Signal Pin-Out (Part 3 of 3)

23 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Power Pins VDDCore V DDCore V DDIO V DDPE V DDAPE V TTPE A 3 A B 2 4 B 6C 5B 4D 9 A4 AC24 B19 C10 B16 D14 A6 AD2 E3 C16 B17 D17 A9 AD3 E21 C17 C4 H4 A 1 6A D 1 5E 2 2 C 1 9 C 1 2 M 3 A18 AD22 F3 D4 C20 N21 A19 Y2 D5 D12 R21 A21 Y23 D18 D19 AA5 A23 AA2 E23 E2 AA11 B1 AA24 F23 F2 AA15 B2 AB2 G3 F21 AA20 B3 AC2 G23 F22 B5 K2 G2 B20 K3 H2 B22 K4 H3 B23 L22 H23 C2 L23 J21 C21 M4 J22 C24 P3 J23 D1 P4 L3 D3 R22 L4 D20 T23 T22 D22 Y3 Y22 D23 AA22 AA9 E4 AA23 AA18 E24 AB3 AB7 G1 AB16 AB13 G24 AB18 AB22 AA1 AC22 AB23 AB1 AC23 AC3 Table 21 PES16T7 Power Pins

24 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Ground Pins Vss Vss V ss V ss V ss A1 C3 H24 R2 AC12 A2 C6 J2 V23 AC14 A5 C8 J3 Y21 AC15 A7 C9 J4 AA3 AC17 A11 C14 K21 AA7 AC19 A13 C22 K22 AA10 AC21 A15 C23 K23 AA13 AD1 A17 D2 L1 AA16 AD4 A20 D6 L2 AB5 AD6 A22 D8 L21 AB9 AD8 A24 D10 L24 AB10 AD10 B7 D16 M23 AB11 AD12 B9 D21 M24 AB15 AD14 B11 D24 N1 AB20 AD17 B13 E1 N2 AC1 AD19 B15 F1 N22 AC4 AD21 B21 F4 P23 AC6 AD23 B24 F24 P24 AC8 AD24 C1 H1 R1 AC10 Table 22 PES16T7 Ground Pins

25 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I Y24 System CCLKUS I Y4 GPIO_00 I/O V21 General Purpose Input/Output GPIO_01 I/O V22 GPIO_02 I/O U24 GPIO_03 I/O U23 GPIO_04 I/O U21 GPIO_05 I/O U22 GPIO_06 I/O T24 GPIO_07 I/O T21 GPIO_08 I/O H22 GPIO_09 I/O H21 GPIO_10 I/O G22 GPIO_11 I/O G21 JTAG_TCK I T2 JTAG JTAG_TDI I T3 JTAG_TDO O T4 JTAG_TMS I T1 JTAG_TRST_N I U2 MSMBADDR_1 I U3 SMBus MSMBADDR_2 I U4 MSMBADDR_3 I U1 MSMBADDR_4 I V2 MSMBCLK I/O V3 MSMBDAT I/O V4 MSMBSMODE I B18 System P01MERGEN I G4 PE0RN00 I AB21 PCI Express PEORN01 I AB19 PE0RN02 I AB17 PE0RN03 I AB14 PE0RP00 I AA21 PE0RP01 I AA19 PE0RP02 I AA17 Table 23 89PES16T7 Alphabetical Signal List (Part 1 of 4)

26 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet PE0RP03 I AA14 PCI Express (cont.) PE0TN00 O AC20 PE0TN01 O AD18 PE0TN02 O AD16 PE0TN03 O AD13 PE0TP00 O AD20 PE0TP01 O AC18 PE0TP02 O AC16 PE0TP03 O AC13 PE1RN00 I AB12 PE1RN01 I AA8 PE1RN02 I AB6 PE1RN03 I AB4 PE1RP00 I AA12 PE1RP01 I AB8 PE1RP02 I AA6 PE1RP03 I AA4 PE1TN00 O AC11 PE1TN01 O AD9 PE1TN02 O AD7 PE1TN03 O AC5 PE1TP00 O AD11 PE1TP01 O AC9 PE1TP02 O AC7 PE1TP03 O AD5 PE2RN00 I R4 PE2RP00 I R3 PE2TN00 I P1 PE2TP00 I P2 PE3RN00 I N4 PE3RP00 I N3 PE3TN00 O M1 PE3TP00 O M2 PE4RN00 O M22 PE4RP00 O M21 PE4TN00 O N23 Signal Name I/O Type Location Signal Category Table 23 89PES16T7 Alphabetical Signal List (Part 2 of 4)

27 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet PE4TP00 O N24 PCI Express (cont.) PE5RN00 I P22 PE5RP00 I P21 PE5TN00 I R23 PE5TP00 I R24 PE6RN00 I C7 PE6RN01 I D11 PE6RN02 I C13 PE6RN03 I C15 PE6RP00 I D7 PE6RP01 I C11 PE6RP02 I D13 PE6RP03 I D15 PE6TN00 O B8 PE6TN01 O A10 PE6TN02 O A12 PE6TN03 O B14 PE6TP00 O A8 PE6TP01 O B10 PE6TP02 O B12 PE6TP03 O A14 PEREFCLKN1 I J1 PEREFCLKN2 I K24 PEREFCLKP1 I K1 PEREFCLKP2 I J24 PERSTN I W21 System REFCLKM I C18 PCI Express RSTHALT I W24 System SSMBADDR_1 I V1 SMBus Interface SSMBADDR_2 I W2 SSMBADDR_3 I W3 SSMBADDR_5 I W4 SSMBCLK I/O W1 SSMBDAT I/O Y1 Signal Name I/O Type Location Signal Category Table 23 89PES16T7 Alphabetical Signal List (Part 3 of 4)

28 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet SWMODE_0 I W23 System SWMODE_1 I W22 SWMODE_2 I V24 V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 21 for a listing of power pins. VSS See Table 22 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 23 89PES16T7 Alphabetical Signal List (Part 4 of 4)

29 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet PES16T7 Pinout — Top View 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 C D E F G H J K L M N P R T U V W Y AA AB AC AD VTTPE (Power)VDDPE (Power) VDDAPE (Power) Signals 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 2 2 3 2 4 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD X X XX X X X X X X X X

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Revision History

February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 25, 2008: Added θJB and θJC parameters to Table 16, Thermal Specifications.

33 of 33 March 25, 2008 IDT 89HPES16T7 Data Sheet CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208

Ordering Information

89HPES16T7ZHBX 320-pin BX320 package, Commercial Temperature 89HPES16T7ZHBXG 320-pin Green BX320 package, Commercial Temperature NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

16T7 16-lane, 7-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BXG320 320-ball BGA, Green BXG AA Device Revision ZH ZH revision

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