89HPES16T4

89HPES16T4 IDT | Alldatasheet

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Features

‹ High Performance PCI Express Switch – Sixteen 2.5 Gbps PCI Express lanes – Four switch ports – Upstream port configurable up to x8 – Downstream ports configurable up to x4 – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ‹ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device conf iguration from serial EEPROM ‹ Legacy Support – PCI compatible INTx emulation – Bus locking ‹ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) ‹ Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protecti on on all TLPs ensures data integrity even in systems t hat do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram Figure 1 Internal Block Diagram 4-Port Switch Core / 16 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer (Port 0) (Port 1) (Port 7) SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer (Port 6) 89HPES16T4 Data Sheet 16-Lane 4-Port PCI Express® Switch

2 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet ‹ Power Management – Utilizes advanced low-power desi gn techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI-PM 1.1)

• Supports device power management states: D0, D3 hot and D3cold – Unused SerDes are disabled ‹ Testability and Debug Features – Ability to read and write any in ternal register via the SMBus ‹ Eleven General Purpose Input/Output Pins – Each pin may be individually co nfigured as an input or output – Each pin may be individually co nfigured as an interrupt input – Some pins have selectable alternate functions ‹ Packaged in a 23mm x 23mm 484-ball BCG with 1mm ball spacing Product Description Utilizing standard PCI Express in terconnect, the PES16T4 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides c onnectivity for up to 4 ports across 16 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specifica- tion revision 1.1. SMBus Interface The PES16T4 contains two SMBus interfaces. The slave interface provides full access to the conf iguration registers in the PES16T4, allowing every configuration register in the device to be read or written by an external agent. The master inte rface allows the default configura- tion register values of the PES16T 4 to be overridden following a reset with values programmed in an exte rnal serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the tw o SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interfac e, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pi ns allow the SMBus address of the serial configuration EEPROM from which data is loaded to be config- ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pi ns. When the pins are sampled, the resulting address is assigned as shown in Table 1. As shown in Figure 2, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 2(a), the master and slave SMBuses are tied together and the PES16T4 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES16T4 registers suppor ts SMBus arbitration. In some systems, this SMBus master in terface may be implemented using general purpose I/O pins on a proces sor or micro controller, and may not support SMBus arbitration. To support these systems, the PES16T4 may be configured to operate in a split configuration as shown in Figure 2(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi- master arbitration is never required. The PES16T4 supports r eading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment

4 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES16T4. Some of the functions listed may be multiplexed on to the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES16T4, the three downstream ports are labeled port 1, port 6, and port 7. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. Port 0 is the upstream port. PE1RP[3:0] PE1RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PE1TP[3:0] PE1TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PE6RP[3:0] PE6RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE6TP[3:0] PE6TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 6. PE7RP[3:0] PE7RN[3:0] I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. PE7TP[3:0] PE7TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each oper- ates as a single x4 port. P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 6 is merged with port 7 to form a single x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7 of port 6. When this pin is high, port 6 and port 7 are not merged, and each oper- ates as a single x4 port. PEREFCLKP[2:1] PEREFCLKN[2:1] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 2 PCI Express Interface Pins

5 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: I/O Expander interrupt 3 input GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output Table 4 General Purpose I/O Pins (Part 1 of 2)

6 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 GPIO[12] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P7RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 7 Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES16T4 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES16T4 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES16T4 switch operating mode. These pins should be static and not change after the negation of PERSTN. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Table 5 System Pins Signal Type Name/Description Table 4 General Purpose I/O Pins (Part 2 of 2)

7 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 7 Power and Ground Pins

8 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Pin Characteristics Note: Some input pads of the PES16T4 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[3:0] I CML Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE1RN[3:0] I PE1RP[3:0] I PE1TN[3:0] O PE1TP[3:0] O PE6RN[3:0] I PE6RP[3:0] I PE6TN[3:0] O PE6TP[3:0] O PE7RN[3:0] I PE7RP[3:0] I PE7TN[3:0] O PE7TP[3:0] O PEREFCLKN[2:1] I LVPECL/ CML Diff. Clock Input Refer to Table 9 PEREFCLKP[2:1] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI 2 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[12,11,8:0] I/O LVTTL High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down PERSTN I P01MERGEN I pull-down P67MERGEN I pull-down RSTHALT I pull-down SWMODE[2:0] I pull-down Table 8 Pin Characteristics (Part 1 of 2)

9 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Logic Diagram — PES16T4 Figure 4 PES16T4 Logic Diagram EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-down 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2) Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[12,11,8:0]

11 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[2:0] 3 CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE1RP[0] PE1RN[0] PE1RP[3] PE1RN[3] PCI Express Switch SerDes Input PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PCI Express Switch SerDes Output ... Port 1 Port 1 ... PE6RP[0] PE6RN[0] PE6RP[3] PE6RN[3] PCI Express Switch SerDes Input PE6TP[0] PE6TN[0] PE6TP[3] PE6TN[3] PCI Express Switch SerDes Output ... Port 6 Port 6 ... PE7RP[0] PE7RN[0] PE7RP[3] PE7RN[3] PCI Express Switch SerDes Input PE7TP[0] PE7TN[0] PE7TP[3] PE7TN[3] PCI Express Switch SerDes Output ... Port 7 Port 7 ... PES16T4 P67MERGEN P01MERGEN

10 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. AC Timing Characteristics Parameter Description Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 9 Input Clock Requirements Parameter Description Min 1 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns Table 10 PCIe AC Timing Characteristics

11 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[10:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 11 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics

12 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Figure 5 JTAG AC Timing Waveform Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES16T4, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for Se rDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digita l Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES16T4 Operating Voltages Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

13 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Am bient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Thermal Considerations This section describes thermal cons iderations for the PES16T4 (23mm2 BCG484 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES16T4 switch. Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card. Grade Temperature Commercial 0 °C to +70°C Ambient Table 14 PES16T4 Operating Temperatures Number of active Lanes per Port Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V Typ Power Max Power 4/4/4/4 mA 598 756 730 873 308 342 371 436 1 1 2.2W 2.9W 4/4/1/1 mA 528 642 548 631 279 298 220 270 1 1 1.69W 2.2W Table 15 PES16T4 Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 11.5 oC/W Zero air flow 9.6 oC/W 1 m/S air flow 9.0 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 10.9 oC/W θJC Thermal Resistance, Junction-to-Case 5 oC/W P Power Dissipation of the Device 2.9 Watts Maximum Table 16 Thermal Specifications for PES16T4, 23x23mm BCG484 Package

14 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES16T4 under three common usage scenarios. As shown in this table, a heat sink is not required in most cases. Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surrounding s in the absence of a heat sink. The general formula to determine θJA is: θJA = (TJ - TA)/P Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is: TJ(actual) = TA + P * θJA(eff) = 70oC + 2.9W * 9.6W/oC = 98oC The actual TJ of 98oC is well below the maximum TJ of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should be added to the device based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is: TA(allowed) = TJ(desired) - (P * θJA(effective)) TA(allowed) = 100oC - (2.9W * 9.6W/oC) = 100oC - 28oC = 72oC An appropriate level of increased air flow and/or a heat sink c an be added to achieve this lower ambient temperature. Please co ntact ssdhelp@idt.com for further assistance. Air Flow Board Size Board Layers Heat Sink Requirement Zero 3.9”x6.2” (ExpressModule form factor) or larger 6 or more No heat sink required Zero Any 10 or more No heat sink required 1 m/S or more Any Any No heat sink required Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics

15 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV Serial Link (cont.) PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 18 DC Electrical Characteristics (Part 1 of 2)

16 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 18 DC Electrical Characteristics (Part 2 of 2)

17 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet The following table lists the pin numbers and signal names for the PES16T4 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B13 V SS D3 SSMBCLK E15 V DDPE A2 V SS B14 PE0TP02 D4 V SS E16 V DDPE A3 V SS B15 V SS D5 PE1RP03 E17 V SS A4 PE1TN03 B16 PE0TP01 D6 V SS E18 V DDAPE A5 V SS B17 V SS D7 PE1RP02 E19 V SS A6 PE1TP02 B18 PE0TP00 D8 V SS E20 SWMODE_0 A7 V SS B19 V SS D9 PE1RN01 E21 SWMODE_1 A8 PE1TN01 B20 V SS D10 V SS E22 V DDCORE A9 V SS B21 V SS D11 PE1RP00 F1 V SS A10 PE1TP00 B22 V SS D12 V SS F2 V DDIO A11 V SS C1 V DDCORE D13 PE0RP03 F3 V DDIO A12 PE0TN03 C2 SSMBADDR_3 D14 V SS F4 V SS A13 V SS C3 SSMBDAT D15 PE0RN02 F5 V DDCORE A14 PE0TN02 C4 V SS D16 V TTPE F6 V DDIO A15 V SS C5 PE1RN03 D17 PE0RP01 F7 V SS A16 PE0TN01 C6 V SS D18 V SS F8 V DDPE A17 V SS C7 PE1RN02 D19 PE0RN00 F9 V DDAPE A18 PE0TN00 C8 V SS D20 V SS F10 V DDCORE A19 V SS C9 PE1RP01 D21 V DDIO F11 V DDPE A20 V SS C10 V SS D22 V SS F12 V DDIO A21 V SS C11 PE1RN00 E1 V DDCORE F13 V DDPE A22 V SS C12 V SS E2 SSMBADDR_1 F14 V DDCORE B1 V SS C13 PE0RN03 E3 SSMBADDR_5 F15 V DDAPE B2 V DDIO C14 V SS E4 CCLKUS F16 V DDCORE B3 V SS C15 PE0RP02 E5 V SS F17 V DDIO B4 PE1TP03 C16 V SS E6 V DDPE F18 CCLKDS B5 V SS C17 PE0RN01 E7 V TTPE F19 RSTHALT B6 PE1TN02 C18 V SS E8 V SS F20 PERSTN B7 V SS C19 PE0RP00 E9 V DDAPE F21 SWMODE_2 B8 PE1TP01 C20 V SS E10 V TTPE F22 V SS B9 V SS C21 V DDAPE E11 V DDPE G1 V DDCORE B10 PE1TN00 C22 V DDCORE E12 V DDPE G2 MSMBADDR_4 B11 V SS D1 V SS E13 V TTPE G3 MSMBCLK B12 PE0TP03 D2 SSMBADDR_2 E14 V DDAPE G4 MSMBDAT Table 19 PES16T4 484-pin Signal Pin-Out (Part 1 of 4)

18 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet G5 V SS H20 GPIO_00 K13 V DDCORE M6 V SS G6 V DDCORE H21 GPIO_01 K14 V SS M7 V DDCORE G7 V SS H22 V SS K15 V DDCORE M8 V SS G8 V SS J1 V DDCORE K16 V SS M9 V DDCORE G9 V SS J2 JTAG_TDO K17 V DDCORE M10 V SS G10 V DDCORE J3 JTAG_TMS K18 V SS M11 V DDCORE G11 V SS J4 JTAG_TRST_N K19 GPIO_07 1 M12 V SS G12 V SS J5 V SS K20 GPIO_06 M13 V DDCORE G13 V DDCORE J6 V SS K21 GPIO_05 1 M14 V SS G14 V SS J7 V SS K22 V SS M15 V DDCORE G15 V SS J8 V DDCORE L1 V DDCORE M16 V SS G16 V SS J9 V SS L2 V DDCORE M17 V DDCORE G17 V SS J10 V DDCORE L3 V SS M18 V SS G18 V DDAPE J11 V SS L4 V DDCORE M19 V SS G19 V SS J12 V DDCORE L5 V SS M20 V DDIO G20 V DDAPE J13 V SS L6 V DDCORE M21 V SS G21 V DDIO J14 V SS L7 V SS M22 V SS G22 V DDCORE J15 V SS L8 V DDCORE N1 PEREFCLKP1 H1 V SS J16 V SS L9 V SS N2 V SS H2 MSMBADDR_1 J17 V DDIO L10 V DDCORE N3 V DDCORE H3 MSMBADDR_2 J18 V DDCORE L11 V SS N4 V DDCORE H4 MSMBADDR_3 J19 GPIO_04 1 L12 V DDCORE N5 V SS H5 V DDCORE J20 GPIO_03 L13 V SS N6 V DDAPE H6 V SS J21 GPIO_02 L14 V DDCORE N7 V SS H7 V DDCORE J22 V DDCORE L15 V SS N8 V DDCORE H8 V SS K1 V SS L16 V SS N9 V SS H9 V DDCORE K2 V DDIO L17 V SS N10 V DDCORE H10 V SS K3 JTAG_TDI L18 V DDCORE N11 V SS H11 V DDCORE K4 JTAG_TCK L19 V SS N12 V DDCORE H12 V SS K5 V DDCORE L20 V SS N13 V SS H13 V DDCORE K6 V SS L21 V DDIO N14 V DDCORE H14 V SS K7 V DDCORE L22 V DDCORE N15 V SS H15 V DDCORE K8 V SS M1 V SS N16 V SS H16 V SS K9 V DDCORE M2 V SS N17 V DDAPE H17 V DDCORE K10 V SS M3 V SS N18 V DDCORE H18 V SS K11 V DDCORE M4 V SS N19 V DDCORE H19 V SS K12 V SS M5 V DDCORE N20 V DDCORE Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES16T4 484-pin Signal Pin-Out (Part 2 of 4)

19 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet N21 V SS R14 V DDCORE U7 V DDIO V22 V DDCORE N22 PEREFCLKN2 R15 V SS U8 V DDPE W1 V SS P1 PEREFCLKN1 R16 V SS U9 V DDAPE W2 V DDCORE P2 V SS R17 V DDIO U10 V DDPE W3 V SS P3 V SS R18 V DDCORE U11 V SS W4 V SS P4 V SS R19 GPIO_08 1 U12 V DDIO W5 PE6RP00 P5 V SS R20 GPIO_11 1 U13 V DDPE W6 V SS P6 V SS R21 GPIO_12 1 U14 V DDAPE W7 PE6RP01 P7 V DDCORE R22 V SS U15 V SS W8 V SS P8 V SS T1 V DDCORE U16 V DDIO W9 PE6RN02 P9 V DDCORE T2 V SS U17 V SS W10 V SS P10 V SS T3 V SS U18 V DDAPE W11 PE6RP03 P11 V DDCORE T4 V SS U19 REFCLKM W12 V SS P12 V SS T5 V SS U20 MSMBSMODE W13 PE7RP00 P13 V DDCORE T6 V DDIO U21 V SS W14 V SS P14 V SS T7 V DDCORE U22 V SS W15 PE7RN01 P15 V DDCORE T8 V SS V1 V DDCORE W16 V TTPE P16 V SS T9 V SS V2 V SS W17 PE7RP02 P17 V DDCORE T10 V DDCORE V3 V DDCORE W18 V SS P18 V SS T11 V SS V4 V SS W19 PE7RN03 P19 V SS T12 V SS V5 V SS W20 V SS P20 V SS T13 V DDCORE V6 V DDPE W21 V DDCORE P21 V SS T14 V SS V7 V TTPE W22 V SS P22 PEREFCLKP2 T15 V SS V8 V SS Y1 V DDCORE R1 V SS T16 V SS V9 V DDAPE Y2 V SS R2 V DDAPE T17 V DDCORE V10 V TTPE Y3 V DDCORE R3 P01MERGEN T18 V SS V11 V DDPE Y4 V SS R4 P67MERGEN T19 V SS V12 V DDPE Y5 PE6RN00 R5 V SS T20 V SS V13 V TTPE Y6 V SS R6 V DDIO T21 V DDAPE V14 V DDAPE Y7 PE6RN01 R7 V SS T22 V DDCORE V15 V DDPE Y8 V SS R8 V DDCORE U1 V SS V16 V DDPE Y9 PE6RP02 R9 V SS U2 V DDCORE V17 V SS Y10 V SS R10 V DDCORE U3 V SS V18 V DDAPE Y11 PE6RN03 R11 V SS U4 V DDAPE V19 V SS Y12 V SS R12 V DDCORE U5 V SS V20 V SS Y13 PE7RN00 R13 V SS U6 V DDAPE V21 V SS Y14 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES16T4 484-pin Signal Pin-Out (Part 3 of 4)

20 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Alternate Signal Functions Y15 PE7RP01 AA6 PE6TN01 AA19 V SS AB10 PE6TP03 Y16 V SS AA7 V SS AA20 V SS AB11 V SS Y17 PE7RN02 AA8 PE6TP02 AA21 V DDCORE AB12 PE7TN00 Y18 V SS AA9 V SS AA22 V SS AB13 V SS Y19 PE7RP03 AA10 PE6TN03 AB1 V SS AB14 PE7TN01 Y20 V DDCORE AA11 V SS AB2 V SS AB15 V SS Y21 V SS AA12 PE7TP00 AB3 V SS AB16 PE7TN02 Y22 V DDCORE AA13 V SS AB4 PE6TN00 AB17 V SS AA1 V SS AA14 PE7TP01 AB5 V SS AB18 PE7TN03 AA2 V DDCORE AA15 V SS AB6 PE6TP01 AB19 V SS AA3 V SS AA16 PE7TP02 AB7 V SS AB20 V SS AA4 PE6TP00 AA17 V SS AB8 PE6TN02 AB21 V SS AA5 V SS AA18 PE7TP03 AB9 V SS AB22 V SS Pin GPIO Alternate J19 GPIO_04 IOEXPINTN2 K21 GPIO_05 IOEXPINTN3 K19 GPIO_07 GPEN R19 GPIO_08 P1RSTN R20 GPIO_11 P6RSTN R21 GPIO_12 P7RSTN Table 20 PES16T4 Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES16T4 484-pin Signal Pin-Out (Part 4 of 4)

21 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Power Pins VDDCore V DDCore V DDCore V DDCore V DDIO V DDPE V DDAPE V TTPE C1 J10 M7 R10 B2 E6 C21 D16 C22 J12 M9 R12 D21 E11 E9 E7 E1 J18 M11 R14 F2 E12 E14 E10 E22 J22 M13 R18 F3 E15 E18 E13 F5 K5 M15 T1 F6 E16 F9 V7 F10 K7 M17 T7 F12 F8 F15 V10 F14 K9 N3 T10 F17 F11 G18 V13 F16 K11 N4 T13 G21 F13 G20 W16 G1 K13 N8 T17 J17 U8 N6 G6 K15 N10 T22 K2 U10 N17 G10 K17 N12 U2 L21 U13 R2 G 1 3L 1N 1 4V 1M 2 0V 6T 2 1 G22 L2 N18 V3 R6 V11 U4 H5 L4 N19 V22 R17 V12 U6 H7 L6 N20 W2 T6 V15 U9 H9 L8 P7 W21 U7 V16 U14 H11 L10 P9 Y1 U12 U18 H13 L12 P11 Y3 U16 V9 H15 L14 P13 Y20 V14 H17 L18 P15 Y22 V18 J1 L22 P17 AA2 J8 M5 R8 AA21 Table 21 PES16T4 Power Pins

22 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Ground Pins Vss Vss Vss Vss Vss Vss Vss A1 C16 H6 L15 P8 U3 Y16 A2 C18 H8 L16 P10 U5 Y18 A3 C20 H10 L17 P12 U11 Y21 A5 D1 H12 L19 P14 U15 AA1 A7 D4 H14 L20 P16 U17 AA3 A9 D6 H16 M1 P18 U21 AA5 A11 D8 H18 M2 P19 U22 AA7 A13 D10 H19 M3 P20 V2 AA9 A15 D12 H22 M4 P21 V4 AA11 A17 D14 J5 M6 R1 V5 AA13 A19 D18 J6 M8 R5 V8 AA15 A20 D20 J7 M10 R7 V17 AA17 A21 D22 J9 M12 R9 V19 AA19 A22 E5 J11 M14 R11 V20 AA20 B1 E8 J13 M16 R13 V21 AA22 B3 E17 J14 M18 R15 W1 AB1 B5 E19 J15 M19 R16 W3 AB2 B7 F1 J16 M21 R22 W4 AB3 B9 F4 K1 M22 T2 W6 AB5 B11 F7 K6 N2 T3 W8 AB7 B13 F22 K8 N5 T4 W10 AB9 B 1 5G 5K 1 0N 7 T 5W 1 2 A B 1 1 B 1 7G 7K 1 2N 9 T 8W 1 4 A B 1 3 B 1 9G 8K 1 4 N 1 1T 9W 1 8 A B 1 5 B 2 0G 9K 1 6 N 1 3 T 1 1 W 2 0 A B 1 7 B21 G11 K18 N15 T12 W22 AB19 B22 G12 K22 N16 T14 Y2 AB20 C4 G14 L3 N21 T15 Y4 AB21 C6 G15 L5 P2 T16 Y6 AB22 C8 G16 L7 P3 T18 Y8 C10 G17 L9 P4 T19 Y10 C12 G19 L11 P5 T20 Y12 C14 H1 L13 P6 U1 Y14 Table 22 PES16T4 Ground Pins

23 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I F18 System CCLKUS I E4 GPIO_00 I/O H20 General Purpose Input/Output GPIO_01 I/O H21 GPIO_02 I/O J21 GPIO_03 I/O J20 GPIO_04 I/O J19 GPIO_05 I/O K21 GPIO_06 I/O K20 GPIO_07 I/O K19 GPIO_08 I/O R19 GPIO_11 I/O R20 GPIO_12 I/O R21 JTAG_TCK I K4 JTAG JTAG_TDI I K3 JTAG_TDO O J2 JTAG_TMS I J3 JTAG_TRST_N I J4 MSMBADDR_1 I H2 SMBus MSMBADDR_2 I H3 MSMBADDR_3 I H4 MSMBADDR_4 I G2 MSMBCLK I/O G3 MSMBDAT I/O G4 MSMBSMODE I U20 System P01MERGEN I R3 PCI Express P67MERGEN I R4 PE0RN00 I D19 PE0RN01 I C17 PE0RN02 I D15 PE0RN03 I C13 PE0RP00 I C19 PE0RP01 I D17 PE0RP02 I C15 Table 23 89PES16T4 Alphabetical Signal List (Part 1 of 4)

24 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet PE0RP03 I D13 PCI Express (Cont.) PE0TN00 O A18 PE0TN01 O A16 PE0TN02 O A14 PE0TN03 O A12 PE0TP00 O B18 PE0TP01 O B16 PE0TP02 O B14 PE0TP03 O B12 PE1RN00 I C11 PE1RN01 I D9 PE1RN02 I C7 PE1RN03 I C5 PE1RP00 I D11 PE1RP01 I C9 PE1RP02 I D7 PE1RP03 I D5 PE1TN00 O B10 PE1TN01 O A8 PE1TN02 O B6 PE1TN03 O A4 PE1TP00 O A10 PE1TP01 O B8 PE1TP02 O A6 PE1TP03 O B4 PE6RN00 I Y5 PE6RN01 I Y7 PE6RN02 I W9 PE6RN03 I Y11 PE6RP00 I W5 PE6RP01 I W7 PE6RP02 I Y9 PE6RP03 I W11 PE6TN00 O AB4 PE6TN01 O AA6 PE6TN02 O AB8 Signal Name I/O Type Location Signal Category Table 23 89PES16T4 Alphabetical Signal List (Part 2 of 4)

25 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet PE6TN03 O AA10 PCI Express (Cont.) PE6TP00 O AA4 PE6TP01 O AB6 PE6TP02 O AA8 PE6TP03 O AB10 PE7RN00 I Y13 PE7RN01 I W15 PE7RN02 I Y17 PE7RN03 I W19 PE7RP00 I W13 PE7RP01 I Y15 PE7RP02 I W17 PE7RP03 I Y19 PE7TN00 O AB12 PE7TN01 O AB14 PE7TN02 O AB16 PE7TN03 O AB18 PE7TP00 O AA12 PE7TP01 O AA14 PE7TP02 O AA16 PE7TP03 O AA18 PEREFCLKN1 I P1 PEREFCLKN2 I N22 PEREFCLKP1 I N1 PEREFCLKP2 I P22 PERSTN I F20 System REFCLKM I U19 PCI Express RSTHALT I F19 System SSMBADDR_1 I E2 SMBus SSMBADDR_2 I D2 SSMBADDR_3 I C2 SSMBADDR_5 I E3 SSMBCLK I/O D3 SMBus SSMBDAT I/O C3 Signal Name I/O Type Location Signal Category Table 23 89PES16T4 Alphabetical Signal List (Part 3 of 4)

26 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet SWMODE_0 I E20 System SWMODE_1 I E21 SWMODE_2 I F21 V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 21 for a listing of power pins. VSS See Table 22 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 23 89PES16T4 Alphabetical Signal List (Part 4 of 4)

27 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet PES16T4 Pinout — Top View 12 3 4 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 Vss (Ground)VDDCore (Power) VDDI/O (Power) 17 18 19 20 21 22 VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals A B C D E F G H J K L M N P R T U V W Y AA AB X 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 41 51 6 17 18 19 20 21 22 A B C D E F G H J K L M N P R T U V W Y AA AB X X X X XX X X

28 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet

29 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet

30 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet

Revision History

February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 1, 2007: Changed package drawing to reflect correct ball/package dimensions. November 6, 2007: Updated package drawing with solder ball tolerance added. November 8, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 25, 2008: Added θJB and θJC parameters to Table 16, Thermal Specifications.

31 of 31 March 25, 2008 IDT 89HPES16T4 Data Sheet CORPORATE HEADQUARTERS

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Ordering Information

89HPES16T4ZHBC 484-ball CABGA package, Commercial Temperature 89HPES16T4ZHBCG 484-ball Green CABGA package, Commercial Temperature NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

16T4 16-lane, 4-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BCG484 484-ball CABGA, Green BCG AA Device Revision ZH ZH revision