PES16NT2 RENESAS | Alldatasheet
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Technical content
Features
◆ High Performance PCI Express Switch – Sixteen PCI Express lanes (2.5Gbps), two switch ports – Delivers 64 Gbps (8 GBps) of aggregate switching capacity – Low latency cut-through switch architecture – Support for Max Payload size up to 2048 bytes – Supports one virtual channel and eight traffic classes – PCI Express Base specification Revision 1.0a compliant ◆ Flexible Architecture with Numerous Configuration Options – Supports automatic per port link width negotiation (x8, x4, x2, or x1) – Static lane reversal on all ports – Automatic polarity inversion on all lanes – Supports locked transactions, al lowing use with legacy soft- ware – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus ◆ Non-Transparent Port – Crosslink support on NTB port – Four mapp ing windows supported
- Each may be configured as a 32-bit memory or I/O window
- May be paired to form a 64-bit memory window – Interprocessor communication
- Thirty-two inbound and outbound doorbells
- Four inbound and outbound message registers
- Two shared scratchpad registers – Allows up to sixteen masters to communicate through the non- transparent port – No limit on the number of supporte d outstanding transactions through the non-transparent bridge – Completely symmetric non-transparent bridge operation allows similar/same configuration software to be run – Supports direct connection to a transparent or non-transparent port of another switch ◆ Highly Integrated Solution – Requ ires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates sixteen 2.5 Gbps embedded full duplex SerDes, 8B/ 10B encoder/decoder (no separate transceivers needed) Block Diagram Figure 1 Internal Block Diagram
16 PCI Express Lanes
x8 Upstream Port and One x8 Downstream Port 2-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer... Multiplexer / Demultiplexer Transaction Layer Data Link Layer Non- Transparent Bridge 89HPES16NT2 Data Sheet 16-Lane 2-Port Non-Transparent PCI Express® Switch
2 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC pass-through – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) – Unused SerDes are disabled ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master and slave interfaces may be tied together so the switch can act as both master and slave ◆ Eight General Purpose Input/Output pins ◆ Packaged in a 23mm x 23mm 484-ball BCG with 1mm ball spacing Pr oduct Description Utilizing standard PCI Express interconnect, the PES16NT2 provides the most efficient high-performance I/O connectivity solution for applica- tions requiring high throughput, low latency, and simple board layout with a minimum number of board la yers. With support for non-trans- parent bridging, the PES16NT2 is part of the IDT PCIe System Intercon- nect Products that target multi-host and intelligent I/O applications requiring inter-domain communicati on. The PES16NT2 provides 64 Gbps (8 GBps) of aggregated, full- duplex switching capacity through 16 integrated serial lanes, using pr oven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a. The PES16NT2 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link, and Transaction layers in compliance with PCI Express Base specifica- tion Revision 1.0a. The PES16NT2 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management. Switch Configuration The PES16NT2 is a two port switch that contains sixteen PCI Express lanes. Each of the two ports is statically allocated eight lanes with ports labeled as A and C. Port A is the upstream port and port C is the non-transparent downstream port. During link training, link width is automatically negotiated. Each PES16NT2 port is capable of independently negotiating to a x8, x4, x2, or x1 width. Thus, the PES16NT2 may be used in virtually any two port switch configuration (e.g., {x8, x8}, {x4, x4}, {x4, x2}, etc.). The PES16NT2 supports static lane reversal. For example, lane reversal for upstream port A may be configured by asserting the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for port C may be enabled via a configuration space register, serial EEPROM, or the SMBus.
3 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Figure 2 PCIe System Interconnect Architecture Block Diagram Pin Description The following tables list the functions of the pins provided on the PES16NT2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PEALREV I PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modify- ing the value of the PALREV bit in the PA_SWCTL register. PEARP[7:0] PEARN[7:0] I PCI Express Port A Serial Data Receive. Differential PCI Express receive pairs for port A. PEATP[7:0] PEATN[7:0] O PCI Express Port A Serial Data Transmit. Differential PCI Express trans- mit pairs for port A PECLREV I PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of PCI Express Port C are reversed. This value may be overridden by modify- ing the value of the PCLREV bit in the PA_SWCTL register. PECRP[7:0] PECRN[7:0] I PCI Express Port C Serial Data Receive. Differential PCI Express receive pairs for port C. PECTP[7:0] PECTN[7:0] O PCI Express Port C Serial Data Transmit. Differential PCI Express trans- mit pairs for port C PEREFCLKP[1:0] PEREFCLKN[1:0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. These signals select the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 1 PCI Express Interface Pins PES16NT2 CPU PCIe System Interconnect Switch PES16NT2 CPU PES16NT2 CPU Embedded FC CPU Embedded SATA / SAS CPU Embedded GbE / 10GigE CPU
4 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM is being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 2 SMBus Interface Pins Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PECRSTN Alternate function pin type: Output Alternate function: Reset output for downstream port C GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PALINKUPN Alternate function pin type: Output Alternate function: Port A link up status output GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCLINKUPN Alternate function pin type: Output Alternate function: Port C link up status output GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: FAILOVERP Alternate function pin type: Input Alternate function: NTB upstream port failover GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 3 General Purpose I/O Pins
5 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PENTBRSTN I Non-Transparent Bridge Reset. Assertion of this signal indicates a reset on the external side of the non-transparent bridge. This signal is only used when the switch mode selects a non-transparent mode and has no effect otherwise. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES16NT2 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES16NT2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES16NT2 switch operating mode. 0x0 - Transparent mode 0x1 -Transparent mode with serial EEPROM initialization 0x2 - Non-transparent mode 0x3 - Non-transparent mode with serial EEPROM initialization 0x4 - Non-transparent failover mode 0x5 - Non-transparent failover mode with serial EEPROM initialization 0x6 through 0xF - Reserved Table 4 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 5 Test Pins (Part 1 of 2)
6 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 6 Power and Ground Pins Signal Type Name/Description Table 5 Test Pins (Part 2 of 2)
7 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Pin Characteristics Note: Some input pads of the PES16NT2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor Notes PCI Express Inter- face PEALREV I LVTTL Input pull-down PEARN[7:0] I CML Serial link PEARP[7:0] I PEATN[7:0] O PEATP[7:0] O PECLREV I LVTTL Input pull-down PECRN[7:0] I CML Serial link PECRP[7:0] I PECTN[7:0] O PECTP[7:0] O PEREFCLKN[1:0] I LVPECL/ CML Diff. Clock Input Refer to Table 8PEREFCLKP[1:0] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI MSMBDAT I/O SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI SSMBDAT I/O General Purpose I/O GPIO[7:0] I/O LVTTL Input, High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down PENTBRSTN I PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-up JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I pull-up JTAG_TDO O Low Drive JTAG_TMS I STI pull-up JTAG_TRST_N I pull-up External pull-down Table 7 Pin Characteristics
8 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Logic Diagram — PES16NT2 Figure 3 PES16NT2 Logic Diagram Reference Clocks PEREFCLKP PEREFCLKN PEATP[0] PEATN[0] JTAG_TCK GPIO[7:0]
8 General Purpose
PEARP[0] PEARN[0] PEARP[1] PEARN[1] PEARP[7] PEARN[7] PCI Express Switch SerDes Input PEATP[1] PEATN[1] PEATP[7] PEATN[7] PCI Express Switch SerDes Output ... MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[3:0] Port A Port A PECTP[0] PECTN[0] PECRP[0] PECRN[0] PECRP[1] PECRN[1] PECRP[7] PECRN[7] PCI Express Switch SerDes Input PECTP[1] PECTN[1] PECTP[7] PECTN[7] PCI Express Switch SerDes Output ... ...Port C Port C PES16NT2 PEALREV CCLKDS PECLREV PERSTN REFCLKM MSMBSMODE PENTBRSTN ... VTTPEPENTBRSTN
9 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. AC Timing Characteristics Parameter Description Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 1251 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 8 Input Clock Requirements Parameter Description Min1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI Table 9 PCIe AC Timing Characteristics (Part 1 of 2)
10 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[7:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 10 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 4. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 11 JTAG AC Timing Characteristics Parameter Description Min 1 Typical1 Max1 Units Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
11 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Figure 4 JTAG AC Timing Waveform Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper functionality. For the PES16NT2, the power-up sequence must be as follows: 1. VDDI/O — 3.3V 2. VDDCore, VDDPE, VDDAPE — 1.0V 3. VTTPE — 1.5V When powe ring up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digita l Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termina- tion Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 12 PES16NT2 Operating Voltages Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16a Tlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N
12 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow. Thermal Considerations This section describes thermal considerations for the PES16NT2 (23mm2 BCG484 package). The data in Table 15 below contains information that is relevant to the thermal performance of the PES16NT2 switch. Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card. Grade Temperature Commercial 0°C to +70°C Ambient Table 13 PES16NT2 Operating Temperatures Number of Connected Lanes: Port-A/Port-C Core (Watts) (1.0V supply) PCIe Digital (Watts) (1.0V supply) PCIe Analog (Watts) (1.0V supply) PCIe Termin- ation (Watts) (1.5V supply) I/O (Watts) (3.3V supply) Total (Watts) Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max 8/8 472 546 697 905 266 345 354 440 1 3 Table 14 PES16NT2 Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM aximum TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 11.5 oC/W Zero air flow 9.6 oC/W 1 m/S air flow 9.0 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 10.9 oC/W θJC Thermal Resistance, Junction-to-Case 5 oC/W P Power Dissipation of the Device 2.68 Watts Maximum Table 15 Thermal Specifications for PES16NT2, 23x23mm BCG484 Package
13 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV V TX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV Serial Link (cont.) VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω V RX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 16 DC Electrical Characteristics (Part 1 of 2)
14 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. I/O Type Parameter Description Min1 Typ1 Max1 Unit Conditions Table 16 DC Electrical Characteristics (Part 2 of 2)
15 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet The following table lists the pin numbers and signal names for the PES16NT2 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B13 PEATN03 D3 V SS E15 V TTPE A2 V SS B14 V SS D4 PEARN07 E16 V DDPE A3 V DDCORE B15 PEATP02 D5 V SS E17 V SS A4 V SS B16 V SS D6 PEARP06 E18 V SS A5 PEATN07 B17 PEATN01 D7 V TTPE E19 PECRN07 A6 V SS B18 V SS D8 PEARN05 E20 PECRP07 PEATN06 B19 PEATP00 D9 V TTPE E21 V SS A8 V SS B20 V SS D10 PEARP04 E22 V SS A9 PEATN05 B21 V SS D11 V DDPE F1 V SS A10 V SS B22 V SS D12 PEARP03 F2 V SS A11 PEATN04 C1 V DDCORE D13 V SS F3 V DDCORE A12 V SS C2 V DDCORE D14 PEARN02 F4 V SS A13 PEATP03 C3 V DDCORE D15 V SS F5 V SS A14 V SS C4 PEARP07 D16 PEARP01 F6 V DDIO A15 PEATN02 C5 V SS D17 V SS F7 V SS A16 V SS C6 PEARN06 D18 PEARN00 F8 V DDPE A17 PEATP01 C7 V SS D19 V SS F9 V DDAPE A18 V SS C8 PEARP05 D20 V SS F10 V DDAPE A19 PEATN00 C9 V SS D21 PECTP07 F11 V DDPE A20 V SS C10 PEARN04 D22 PECTN07 F12 V DDPE A21 V SS C11 V SS E1 V DDCORE F13 V DDAPE A22 V SS C12 PEARN03 E2 V DDCORE F14 V DDAPE B1 V SS C13 V TTPE E3 V SS F15 V DDPE B2 V SS C14 PEARP02 E4 V DDCORE F16 V SS B3 V DDCORE C15 V TTPE E5 V SS F17 V SS B4 V SS C16 PEARN01 E6 V SS F18 V DDPE B5 PEATP07 C17 V SS E7 V TTPE F19 V SS B6 V SS C18 PEARP00 E8 V DDPE F20 V SS B7 PEATP06 C19 V SS E9 V DDAPE F21 PECTP06 B8 V SS C20 V DDCORE E10 V TTPE F22 PECTN06 B9 PEATP05 C21 V DDCORE E11 V SS G1 V DDCORE B10 V SS C22 V DDCORE E12 V DDPE G2 V DDCORE B11 PEATP04 D1 V SS E13 V TTPE G3 V SS B12 V SS D2 V SS E14 V SS G4 V DDCORE Table 17 PES16NT2 484-pin Signal Pin-Out (Part 1 of 4)
16 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet G5 V SS H20 V SS K13 V DDCORE M6 V DDCORE G6 V SS H21 PECTP05 K14 V SS M7 V SS G7 V DDIO H22 PECTN05 K15 V DDCORE M8 V SS G8 V SS J1 V SS K16 V SS M9 V DDCORE G9 V SS J2 V DDCORE K17 V DDAPE M10 V SS G10 V SS J3 V SS K18 V SS M11 V DDCORE G11 V DDIO J4 V DDCORE K19 V TTPE M12 V SS G12 V SS J5 V SS K20 V TTPE M13 V DDCORE G13 V SS J6 V DDIO K21 PECTN04 M14 V SS G14 V DDAPE J7 V SS K22 PECTP04 M15 V DDCORE G15 V SS J8 V DDCORE L1 V SS M16 V SS G16 V DDIO J9 V SS L2 V DDCORE M17 V DDCORE G17 V DDIO J10 V DDCORE L3 V SS M18 V SS G18 V SS J11 V SS L4 V DDCORE M19 V SS G19 PECRP06 J12 V DDCORE L5 V SS M20 V SS G20 PECRN06 J13 V SS L6 V DDIO M21 PECTP03 G21 V SS J14 V DDCORE L7 V SS M22 PECTN03 G22 VSS J15 V SS L8 V DDCORE N1 V SS H1 V SS J16 V DDAPE L9 V SS N2 V SS H2 V SS J17 V SS L10 V DDCORE N3 V DDCORE H3 V DDCORE J18 V DDAPE L11 V SS N4 V DDCORE H4 V SS J19 PECRN05 L12 V DDCORE N5 V DDAPE H5 V SS J20 PECRP05 L13 V SS N6 V DDAPE H6 V DDCORE J21 V SS L14 V DDCORE N7 V SS H7 V SS J22 V SS L15 V SS N8 V DDCORE H8 V DDCORE K1 V SS L16 V SS N9 V SS H9 V SS K2 V SS L17 V DDPE N10 V DDCORE H10 V DDCORE K3 V DDCORE L18 V DDPE N11 V SS H11 V SS K4 V SS L19 PECRN04 N12 V DDCORE H12 V SS K5 V SS L20 PECRP04 N13 V SS H13 V DDCORE K6 V DDCORE L21 V SS N14 V DDCORE H14 V SS K7 V SS L22 V SS N15 V SS H15 V DDCORE K8 V SS M1 V SS N16 V SS H16 V SS K9 V DDCORE M2 V SS N17 V DDAPE H17 V DDPE K10 V SS M3 V SS N18 V DDAPE H18 V TTPE K11 V DDCORE M4 V SS N19 PECRP03 H19 VTTPE K12 V SS M5 V SS N20 PECRN03 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 17 PES16NT2 484-pin Signal Pin-Out (Part 2 of 4)
17 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet N21 V TTPE R14 V SS U7 V SS V22 PECTN00 N22 VTTPE R15 V SS U8 V SS W1 V SS P1 PEREFCLKP0 R16 V SS U9 V SS W2 V DDCORE P2 PEREFCLKN0 R17 V DDAPE U10 V SS W3 V SS P3 V SS R18 V DDAPE U11 V SS W4 V DDCORE P4 V SS R19 PECRN02 U12 V SS W5 V SS P5 V SS R20 PECRP02 U13 V SS W6 V DDIO P6 V DDIO R21 V SS U14 V SS W7 V SS P7 V SS R22 V SS U15 V SS W8 V DDIO P8 V SS T1 V SS U16 V DDCORE W9 V DDCORE P9 V DDCORE T2 V SS U17 V DDCORE W10 V SS P10 V SS T3 V SS U18 V DDCORE W11 V DDIO P11 V DDCORE T4 V SS U19 PECRP01 W12 V SS P12 V SS T5 V SS U20 PECRN01 W13 V SS P13 V DDCORE T6 V DDIO U21 V DDPE W14 V DDIO P14 V SS T7 V DDIO U22 V TTPE W15 V SS P15 V DDCORE T8 V DDIO V1 V DDCORE W16 V DDIO P16 V SS T9 V DDCORE V2 V SS W17 V SS P17 V DDPE T10 V DDIO V3 V DDCORE W18 V SS P18 V DDPE T11 V DDCORE V4 V SS W19 PECRN00 P19 VSS T12 V DDCORE V5 V SS W20 PECRP00 P20 VSS T13 V DDIO V6 V SS W21 V SS P21 PECTP02 T14 V DDIO V7 V DDCORE W22 V SS P22 PECTN02 T15 V DDCORE V8 V SS Y1 V DDCORE R1 V SS T16 V DDIO V9 V SS Y2 V SS R2 V SS T17 V DDIO V10 V DDCORE Y3 V DDCORE R3 V DDCORE T18 V SS V11 V SS Y4 V DDCORE R4 V DDCORE T19 V SS V12 V DDCORE Y5 JTAG_TDO R5 V SS T20 V DDAPE V13 V SS Y6 MSMBADDR_1 VDDCORE T21 PECTP01 V14 V DDCORE Y7 MSMBADDR_4 R7 V SS T22 PECTN01 V15 V SS Y8 SSMBADDR_1 VSS U1 V SS V16 V DDCORE Y9 SSMBADDR_5 R9 V SS U2 V SS V17 V SS Y10 CCLKUS R10 VSS U3 V SS V18 V DDCORE Y11 CCLKDS R11 V SS U4 V DDCORE V19 V DDPE Y12 PEALREV R12 V SS U5 V SS V20 V TTPE Y13 SWMODE_1 R13 V SS U6 V SS V21 PECTP00 Y14 PECLREV Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 17 PES16NT2 484-pin Signal Pin-Out (Part 3 of 4)
18 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Alternate Signal Functions Y15 RSTHALT AA6 JTAG_TRST_N AA19 REFCLKM AB10 SSMBCLK Y16 GPIO_02 1 AA7 MSMBADDR_3 AA20 V DDCORE AB11 V SS Y17 GPIO_05 1 AA8 MSMBDAT AA21 V SS AB12 V SS Y18 MSMBSMODE AA9 SSMBADDR_3 AA22 V SS AB13 V SS Y19 V SS AA10 SSMBDAT AB1 V SS AB14 SWMODE_2 Y20 VSS AA11 V SS AB2 V SS AB15 PERSTN Y21 PEREFCLKP1 AA12 V DDCORE AB3 V SS AB16 GPIO_00 Y22 PEREFCLKN1 AA13 SWMODE_0 AB4 V SS AB17 GPIO_03 AA1 VSS AA14 SWMODE_3 AB5 JTAG_TCK AB18 GPIO_06 AA2 VSS AA15 PENTBRSTN AB6 JTAG_TMS AB19 V SS AA3 V DDCORE AA16 GPIO_01 1 AB7 MSMBADDR_2 AB20 V SS AA4 V DDCORE AA17 GPIO_04 1 AB8 MSMBCLK AB21 V SS AA5 JTAG_TDI AA18 GPIO_07 AB9 SSMBADDR_2 AB22 V SS Pin GPIO Alternate AA16 GPIO_1 PECRSTN Y16 GPIO_2 PALINKUPN AA17 GPIO_4 PCLINKUPN Y17 GPIO_5 FAILOVERP Table 18 PES16NT2 Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 17 PES16NT2 484-pin Signal Pin-Out (Part 4 of 4)
19 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Power Pins VDDCore V DDCore V DDCore V DDCore V DDIO V DDPE V DDAPE V TTPE A 3 J 2M 1 3 U 1 6F 6D 1 1E 9C 1 3 B3 J4 M15 U17 G7 E8 F9 C15 C1 J8 M17 U18 G11 E12 F10 D7 C2 J10 N3 V1 G16 E16 F13 D9 C3 J12 N4 V3 G17 F8 F14 E7 C20 J14 N8 V7 J6 F11 G14 E10 C21 K3 N10 V10 L6 F12 J16 E13 C22 K6 N12 V12 P6 F15 J18 E15 E1 K9 N14 V14 T6 F18 K17 H18 E2 K11 P9 V16 T7 H17 N5 H19 E4 K13 P11 V18 T8 L17 N6 K19 F3 K15 P13 W2 T10 L18 N17 K20 G1 L2 P15 W4 T13 P17 N18 N21 G2 L4 R3 W9 T14 P18 R17 N22 G4 L8 R4 Y1 T16 U21 R18 U22 H3 L10 R6 Y3 T17 V19 T20 V20 H6 L12 T9 Y4 W6 H8 L14 T11 AA3 W8 H10 M6 T12 AA4 W11 H13 M9 T15 AA12 W14 H15 M11 U4 AA20 W16 Table 19 PES16TN2 Power Pins
20 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Ground Pins Vss Vss Vss Vss Vss Vss Vss A1 D2 G13 K10 N9 T3 W10 A2 D3 G15 K12 N11 T4 W12 A4 D5 G18 K14 N13 T5 W13 A6 D13 G21 K16 N15 T18 W15 A8 D15 G22 K18 N16 T19 W17 A10 D17 H1 L1 P3 U1 W18 A12 D19 H2 L3 P4 U2 W21 A14 D20 H4 L5 P5 U3 W22 A16 E 3H 5L 7P 7U 5Y 2 A18 E 5H 7L 9P 8U 6 Y 19 A20E 6 H 9L 11 P 10U 7Y 20 A21 E11 H11 L13 P12 U8 AA1 A22 E14 H12 L15 P14 U9 AA2 B1 E17 H14 L16 P16 U10 AA11 B2 E18 H16 L21 P19 U11 AA21 B4 E21 H20 L22 P20 U12 AA22 B6 E22 J1 M1 R1 U13 AB1 B8 F1 J3 M2 R2 U14 AB2 B10 F2 J5 M3 R5 U15 AB3 B12 F4 J7 M4 R7 V2 AB4 B14 F5 J9 M5 R8 V4 AB11 B16 F7 J11 M7 R9 V5 AB12 B18 F16 J13 M8 R10 V6 AB13 B20 F17 J15 M10 R11 V8 AB19 B21 F19 J17 M12 R12 V9 AB20 B22 F20 J21 M14 R13 V11 AB21 C5 G3 J22 M16 R14 V13 AB22 C7 G5 K1 M18 R15 V15 C9 G6 K2 M19 R16 V17 C11 G8 K4 M20 R21 W1 C17 G9 K5 N1 R22 W3 C19 G10 K7 N2 T1 W5 D1 G12 K8 N7 T2 W7 Table 20 PES16NT2 Ground Pins
21 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I Y11 System CCLKUS I Y10 GPIO_00 I/O AB16 General Purpose Input/Output GPIO_01 I/O AA16 GPIO_02 I/O Y16 GPIO_03 I/O AB17 GPIO_04 I/O AA17 GPIO_05 I/O Y17 GPIO_06 I/O AB18 GPIO_07 I/O AA18 JTAG_TCK I AB05 JTAG JTAG_TDI I AA05 JTAG_TDO O Y5 JTAG_TMS I AB6 JTAG_TRST_N I AA6 MSMBADDR_1 I Y6 SMBus MSMBADDR_2 I AB7 MSMBADDR_3 I AA7 MSMBADDR_4 I Y7 MSMBCLK I/O AB8 MSMBDAT I/O AA8 MSMBSMODE I Y18 System PEALREV I Y12 PCI Express PEARN00 I D18 PEARN01 I C16 PEARN02 I D14 PEARN03 I C12 PEARN04 I C10 PEARN05 I D8 PEARN06 I C6 PEARN07 I D4 PEARP00 I C18 PEARP01 I D16 PEARP02 I C14 Table 21 89PES16NT2 Alphabetical Signal List (Part 1 of 4)
22 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet PEARP03 I D12 PCI Express (cont.) PEARP04 I D10 PEARP05 I C8 PEARP06 I D6 PEARP07 I C4 PEATN00 0 A19 PEATN01 O B17 PEATN02 O A15 PEATN03 O B13 PEATN04 O A11 PEATN05 O A9 PEATN06 O A7 PEATN07 O A5 PEATP00 O B19 PEATP01 O A17 PEATP02 O B15 PEATP03 O A13 PEATP04 O B11 PEATP05 O B9 PEATP06 O B7 PEATP07 O B5 PECLREV I Y14 PECRN00 I W19 PECRN01 I U20 PECRN02 I R19 PECRN03 I N20 PECRN04 I L19 PECRN05 I J19 PECRN06 I G20 PECRN07 I E19 PECRP00 I W20 PECRP01 I U19 PECRP02 I R20 PECRP03 I N19 PECRP04 I L20 PECRP05 I J20 Signal Name I/O Type Location Signal Category Table 21 89PES16NT2 Alphabetical Signal List (Part 2 of 4)
23 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet PECRP06 I G19 PCI Express (cont. PECRP07 I E20 PECTN00 O V22 PECTN01 O T22 PECTN02 O P22 PECTN03 O M22 PECTN04 O K21 PECTN05 O H22 PECTN06 O F22 PECTN07 O D22 PECTP00 O V21 PECTP01 O T21 PECTP02 O P21 PECTP03 O M21 PECTP04 O K22 PECTP05 O H21 PECTP06 O F21 PECTP07 O D21 PENTBRSTN I AA15 System PEREFCLKN0 I P2 PCI Express PEREFCLKN1 I Y22 PEREFCLKP0 I P1 PEREFCLKP1 I Y21 PERSTN I AB15 System REFCLKM I AA19 PCI Express RSTHALT I Y15 System SSMBADDR_1 I Y8 SMBus SSMBADDR_2 I AB9 SSMBADDR_3 I AA9 SSMBADDR_5 I Y9 SSMBCLK I/O AB10 SSMBDAT I/O AA10 Signal Name I/O Type Location Signal Category Table 21 89PES16NT2 Alphabetical Signal List (Part 3 of 4)
24 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet SWMODE_0 I AA13 System SWMODE_1 I Y13 SWMODE_2 I AB14 SWMODE_3 I AA14 VDDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 19 for a listing of power pins. VSS See Table 20 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 21 89PES16NT2 Alphabetical Signal List (Part 4 of 4)
25 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet PES16NT2 Pinout — Top View 12 3 4 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 Vss (Ground)VDDCore (Power) VDDI/O (Power) 17 18 19 20 21 22 VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals A B C D E F G H J K L M N P R T U V W Y AA AB X 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 41 51 6 17 18 19 20 21 22 A B C D E F G H J K L M N P R T U V W Y AA AB X X X XX X X X X X X X X X X X
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Revision History
April 15, 2008: Initial publication of data sheet. January 5, 2009: On the Ordering Information page, changed silicon revision from ZA to ZB.
29 of 29 January 5, 2009 IDT 89HPES16NT2 Data Sheet CORPORATE HEADQUARTERS
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San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208
Ordering Information
89HPES16NT2ZBBC 484-ball CABGA package, Commercial Temperature 89HPES16NT2ZBBCG 484-ball Green CABG A package, Commercial Temperature NN A AAA NNAAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family
89 Serial Switching Product
16NT2 16-lane, 2-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BCG484 484-ball CABGA, Green BCG AA Revision ID ZB Silicon revision Non-Transparent
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