89HPES12N3

89HPES12N3 IDT | Alldatasheet

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Technical content

Features

◆ High Performance PCI Express Switch – Three x4 ports with 12 PCI Express lanes total – Delivers 6 GBps (48 Gbps) aggregate switching capacity – Low latency cut-through switch architecture – Supports 128 to 2048 byte maximum payload size – Supports one virtual channel – PCI Express Base specification Revision 1.0a compliant ◆ Flexible Architecture with Numerous Configuration Options – Port arbitration schemes ut ilizing round robin or weighted round robin algorithms – Supports automatic per port link with negotiation (x4, x2, or x1) – Supports static lane reversal on all ports – Supports polarity inversion – Supports locked transactions, al lowing use with legacy soft- ware – Ability to load device conf iguration from serial EEPROM ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/ decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protecti on on all TLPs ensures data integrity even in systems t hat do not implement end-to-end CRC (ECRC) – Supports ECRC passed through – Supports PCI Express Native Hot-Plug

• Compatible with Hot-Plug I/O expanders used on PC moth- erboards – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) – Unused SerDes are disabled – Supports Advanced Configuration and Power Interface Speci- fication, Revision 2.0 (ACPI) supporting active link state ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any in ternal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters Block Diagram Figure 1 Internal Block Diagram

12 PCI Express Lanes

One x4 Upstream Port and Two x4 Downstream Ports 3-Port Switch Core Frame Buffer Scheduler Multiplexer/Demultiplexer Transaction Layer Data Link Layer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer/Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer/Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer 89HPES12N3 Data Sheet 12-lane 3-Port PCI Express® Switch

2 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is also used by an external Hot-Plug I/O expander – Master and slave interfaces may be tied together so the PES12N3 can act as both master and slave ◆ 8 General Purpose Input/Output pins ◆ Packaged in 19x19mm 324 ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES12N3 provides the most efficient high-performance I/O connectivity solution for applica- tions requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 6 GBps (48 Gbps) of aggregated, full-duplex switching capacity through 12 integrated serial lanes, using proven and robust IDT te chnology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a. The PES12N3 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification or cut-through switch and is designed to switch memory and I/O transac- tions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management. This includes system selectable algorithms such as r ound robin, weighted round-robin, and strict priority schemes guaranteeing bandwidth allocation and/or latency for critical traffic classes in applic ations such as high throughput Quad/ Dual Gigabit I/Os, SATA controllers, and Fibre Channel HBAs. Switch Configuration The PES12N3 is a three port switch that contains 12 PCI Express lanes. Each of the three ports is st atically allocated 4 lanes with ports labeled as A, B and C. Port A is always the upstream port while ports B and C are always downstream ports. The switch operating mode, as well as an optional initialization from a serial EEPROM, is selected via the Switch Mode (SWMODE[3:0]) inputs. During link training, link width is automatically negotiated. Each PES12N3 port is capable of independently negotiating to a x4, x2 or x1 width. Thus, the PES12N3 may be used in virtually any three port switch configuration (e.g., {x4, x4, x4}, {x4, x2, x1}, etc.). The PES12N3 supports static lane reversal. For ex ample, lane reversal for upstream port A may be configured by assert ing the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for ports B and C may be enabled via a configuration space register, serial EEPROM, or the SMBus. Figure 2 I/O Expansion Application MemoryMemoryMemory Processor MemoryNorth Bridge PES12N3PES12N3 PES12N3 I/O 10GbE I/O 10GbE I/O SATA I/O SATAPCI Express Slots

3 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12N3. Some of the functions listed may be multiplexed on to the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PEALREV I PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modify- ing the value of the PALREV bit in the PA_SWCTL register. PEARP[3:0] PEARN[3:0] I PCI Express Port A Serial Data Receive. Differential PCI Express receive pairs for port A. PEATP[3:0] PEATN[3:0] O PCI Express Port A Serial Data Transmit. Differential PCI Express trans- mit pairs for port A PEBLREV I PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of PCI Express Port B are reversed. This value may be overridden by modify- ing the value of the PBLREV bit in the PA_SWCTL register. PEBRP[3:0] PEBRN[3:0] I PCI Express Port B Serial Data Receive. Differential PCI Express receive pairs for port B. PEBTP[3:0] PEBTN[3:0] O PCI Express Port B Serial Data Transmit. Differential PCI Express trans- mit pairs for port B PECLREV I PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of PCI Express Port C are reversed. This value may be overridden by modify- ing the value of the PCLREV bit in the PA_SWCTL register. PECRP[3:0] PECRN[3:0] I PCI Express Port C Serial Data Receive. Differential PCI Express receive pairs for port C. PECTP[3:0] PECTN[3:0] O PCI Express Port C Serial Data Transmit. Differential PCI Express trans- mit pairs for port C PEREFCLKP[1:0] PEREFCLKN[1:0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. These signals select the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 1 PCI Express Interface Pins Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. This signal is active only when EEPROM data is being loaded. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. Table 2 SMBus Interface Pins (Part 1 of 2)

4 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN Alternate function pin type: Input Alternate function: Hot-Plug I/O expander interrupt input GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PAABN Alternate function pin type: Input Alternate function: Port A attention button Input GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PAAIN Alternate function pin type: Output Alternate function: Port A attention indicator output GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PAPIN Alternate function pin type: Output Alternate function: Port A power indicator output GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 3 General Purpose I/O Pins Signal Type Name/Description Table 2 SMBus Interface Pins (Part 2 of 2)

5 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES12N3 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12N3 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. TSTRSVD I Reserved. Reserved for future test mode. Must be tied to ground. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES12N3 switch operating mode. 0x0 - Transparent mode 0x1 -Transparent mode with serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - 10-bit loopback test mode 0x9 - Reserved 0xA - Internal pseudo random bit stream self-test test mode 0xB - External pseudo random bit stream self-test test mode 0xC - Reserved 0xD - SerDes broadcast test mode 0xE - 0xF Reserved Table 4 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 5 Test Pins (Part 1 of 2)

6 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Signal Type Name/Description V DDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 6 Power and Ground Pins Signal Type Name/Description Table 5 Test Pins (Part 2 of 2)

7 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Pin Characteristics Note: Some input pads of the PES12N3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor Notes PCI Express Inter- face PEALREV I LVTTL Input pull-down PEARN[3:0] I CML Serial link PEARP[3:0] I PEATN[3:0] O PEATP[3:0] O PEBLREV I LVTTL Input pull-down PEBRN[3:0] I CML Serial link PEBRP[3:0] I PEBTN[3:0] O PEBTP[3:0] O PECLREV I LVTTL Input pull-down PECRN[3:0] I CML Serial link PECRP[3:0] I PECTN[3:0] O PECTP[3:0] O PEREFCLKN[1:0] I LVPECL/ CML Diff. Clock Input Refer to Table 8PEREFCLKP[1:0] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI MSMBDAT I/O SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI SSMBDAT I/O General Purpose I/O GPIO[7:0] I/O LVTTL Input, High Drive pull-up Table 7 Pin Characteristics (Part 1 of 2)

8 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down PERSTN I RSTHALT I pull-down TSTRSVD I pull-down External pulldown SWMODE[3:0] I pull-up JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I pull-up JTAG_TDO O Low Drive JTAG_TMS I STI pull-up JTAG_TRST_N I pull-up External pulldown Function Pin Name Type Buffer I/O Type Internal Resistor Notes Table 7 Pin Characteristics (Part 2 of 2)

9 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Logic Diagram — PES12N3 Figure 3 PES12N3 Logic Diagram Reference Clock PEREFCLKP PEREFCLKN PEATP[0] PEATN[0] JTAG_TCK GPIO[7:0]

8 General Purpose

PEARP[0] PEARN[0] PEARP[1] PEARN[1] PEARP[3] PEARN[3] PCI Express Switch SerDes Input PEATP[1] PEATN[1] PEATP[3] PEATN[3] PCI Express Switch SerDes Output ... MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[3:0] Port A Port A PEBTP[0] PEBTN[0] PEBRP[0] PEBRN[0] PEBRP[1] PEBRN[1] PEBRP[3] PEBRN[3] PCI Express Switch SerDes Input PEBTP[1] PEBTN[1] PEBTP[3] PEBTN[3] PCI Express Switch SerDes Output ... ...Port B Port B PECTP[0] PECTN[0] PECRP[0] PECRN[0] PECRP[1] PECRN[1] PECRP[3] PECRN[3] PCI Express Switch SerDes Input PECTP[1] PECTN[1] PECTP[3] PECTN[3] PCI Express Switch SerDes Output ... Port C Port C PES12N3 PEALREV CCLKDS PEBLREV PECLREV PERSTN REFCLKM MSMBSMODE TSTRSVD VTTPE

10 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. AC Timing Characteristics Parameter Description Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 8 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-IDLE-RCV-DET- MAX Max time spend in idle before initiating a RX detect sequence 20 100 ms TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI Table 9 PCIe AC Timing Characteristics (Part 1 of 2)

11 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[7:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 —n s Table 10 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 4. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 11 JTAG AC Timing Characteristics Parameter Description Min 1 Typical1 Max1 Units Table 9 PCIe AC Timing Characteristics (Part 2 of 2)

12 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Figure 4 JTAG AC Timing Waveform Recommended Operating Supply Voltages Recommended Operating Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for Se rDes LVPECL/CML 3.135 3.3 3.465 V VDDPE PCI Express Digita l Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 12 PES12N3 Operating Voltages Grade Temperature Commercial 0 °C to +70°C Ambient Table 13 PES12N3 Operating Temperatures Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

13 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES12N3, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow. Number of Connected Lanes: Port-A/Port-B/Port-C Core (Watts) (1.0V supply) PCIe Digital (Watts) (1.0V supply) PCIe Analog (Watts) (1.0V supply) PCIe Termin- ation (Watts) (1.5V supply) I/O (Watts) (3.3V supply) Total (Watts) Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Table 14 PES12N3 Power Consumption

14 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 15 DC Electrical Characteristics (Part 1 of 2)

15 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 15 DC Electrical Characteristics (Part 2 of 2)

16 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet The following table lists the pin numbers and signal names for the PES12N3 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS E10 V DDPE K1 V DDCORE P10 V DDIO A2 V SS E11 V SS K2 V SS P11 V DDIO A3 PEARP03 E12 V DDPE K3 V TTPE P12 V DDIO A4 V DDCORE E13 V SS K4 V DDCORE P13 V DDIO A5 PEATN03 E14 V DDCORE K5 V DDPE P14 V DDIO A6 V DDCORE E15 V DDAPE K6 V SS P15 V SS A7 PEATP02 E16 V SS K7 V SS P16 V TTPE A8 V DDCORE E17 PECTP03 K8 V SS P17 V SS A9 PEARN02 E18 PECTN03 K9 V SS P18 V DDCORE A10 V DDCORE F1 V DDCORE K10 V SS R1 PEBTN03 A11 PEARP01 F2 V SS K11 V SS R2 PEBTP03 A12 V DDCORE F3 V DDCORE K12 V SS R3 V SS A13 PEATP01 F4 V DDAPE K13 V SS R4 V DDIO A14 V DDCORE F5 V SS K14 V SS R5 V SS A15 V DDCORE F6 V DDCORE K15 V DDPE R6 V DDCORE A16 PEATN00 F7 V SS K16 V TTPE R7 MSMBDAT A17 V SS F8 V DDCORE K17 V SS R8 SSMBADDR_5 A18 V SS F9 V SS K18 V DDCORE R9 PEALREV B1 V DDCORE F10 V DDCORE L1 PEBRN02 R10 SWMODE_2 B2 V DDCORE F11 V SS L2 PEBRP02 R11 RSTHALT B3 PEARN03 F12 V SS L3 V SS R12 GPIO_04 1 B4 V SS F13 V DDPE L4 V DDPE R13 V DDCORE B5 PEATP03 F14 V SS L5 V SS R14 V SS B6 V SS F15 V DDIO L6 V DDCORE R15 V DDIO B7 PEATN02 F16 V SS L7 V DDCORE R16 V SS B8 V SS F17 V SS L8 V DDCORE R17 PECTP00 B9 PEARP02 F18 V DDCORE L9 V DDCORE R18 PECTN00 B10 V SS G1 PEBTP01 L10 V DDCORE T1 V DDCORE B11 PEARN01 G2 PEBTN01 L11 V DDCORE T2 V SS B12 V SS G3 V SS L12 V DDCORE T3 V SS B13 PEATN01 G4 V DDPE L13 V DDCORE T4 JTAG_TCK B14 V SS G5 V DDAPE L14 V SS T5 JTAG_TDO B15 V SS G6 V SS L15 V DDPE T6 MSMBADDR_1 B16 PEATP00 G7 V SS L16 V SS T7 MSMBCLK Table 16 PES12N3 324-pin Signal Pin-Out (Part 1 of 3)

17 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet B17 V DDCORE G8 V DDIO L17 PECRP01 T8 SSMBADDR_2 B18 V DDCORE G9 V SS L18 PECRN01 T9 CCLKDS C1 PEBRP00 G10 V DDIO M1 V DDCORE T10 SWMODE_1 C2 PEBRN00 G11 V SS M2 V SS T11 PERSTN C3 V SS G12 V DDCORE M3 V SS T12 GPIO_03 1 C4 V DDCORE G13 V SS M4 V DDAPE T13 GPIO_07 C5 V SS G14 V DDAPE M5 V SS T14 TSTRSVD C6 V TTPE G15 V DDPE M6 V DDCORE T15 REFCLKM C7 V SS G16 V SS M7 V SS T16 V SS C8 V TTPE G17 PECTN02 M8 V SS T17 V SS C9 V SS G18 PECTP02 M9 V DDCORE T18 V DDCORE C10 V TTPE H1 V DDCORE M10 V DDCORE U1 PEBRP03 C11 V SS H2 V SS M11 V SS U2 PEBRN03 C12 V TTPE H3 V TTPE M12 V SS U3 V SS C13 V DDCORE H4 V DDAPE M13 V DDCORE U4 JTAG_TDI C14 PEARP00 H5 V SS M14 V SS U5 JTAG_TMS C15 PEARN00 H6 V SS M15 V DDAPE U6 MSMBADDR_2 C16 V DDCORE H7 V DDCORE M16 V SS U7 MSMBADDR_4 C17 PECRN03 H8 V SS M17 V SS U8 SSMBADDR_3 C18 PECRP03 H9 V DDCORE M18 V DDCORE U9 CCLKUS D1 V DDCORE H10 V DDCORE N1 PEBTP02 U10 SWMODE_0 D2 V SS H11 V SS N2 PEBTN02 U11 PECLREV D3 V SS H12 V DDCORE N3 V TTPE U12 GPIO_00 D4 V DDCORE H13 V SS N4 V DDAPE U13 GPIO_02 1 D5 V SS H14 V DDAPE N5 V SS U14 GPIO_06 D6 V DDAPE H15 V DDPE N6 V SS U15 MSMBSMODE D7 V SS H16 V TTPE N7 V SS U16 V SS D8 V DDAPE H17 V SS N8 V SS U17 PECRN00 D9 V SS H18 V DDCORE N9 V SS U18 PECRP00 D10 V DDAPE J1 PEBRP01 N10 V SS V1 V DDCORE D11 V SS J2 PEBRN01 N11 V SS V2 V SS D12 V DDAPE J3 V SS N12 V SS V3 PEREFCLKP1 D13 V SS J4 V DDPE N13 V SS V4 PEREFCLKN1 D14 V DDCORE J5 V SS N14 V SS V5 JTAG_TRST_N D15 V SS J6 V DDCORE N15 V DDAPE V6 MSMBADDR_3 D16 V SS J7 V SS N16 V TTPE V7 SSMBADDR_1 D17 V SS J8 V SS N17 PECTN01 V8 SSMBCLK Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 16 PES12N3 324-pin Signal Pin-Out (Part 2 of 3)

18 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Alternate Signal Functions D18 V DDCORE J9 V DDCORE N18 PECTP01 V9 SSMBDAT E1 PEBTN00 J10 V DDCORE P1 V DDCORE V10 PEBLREV E2 PEBTP00 J11 V SS P2 V SS V11 SWMODE_3 E3 V DDCORE J12 V SS P3 V TTPE V12 V DDIO E4 V SS J13 V DDCORE P4 V SS V13 GPIO_01 E5 V DDCORE J14 V SS P5 V DDIO V14 GPIO_05 1 E6 V SS J15 V DDCORE P6 V DDIO V15 PEREFCLKP2 E7 V SS J16 V SS P7 V DDIO V16 PEREFCLKN2 E8 V DDPE J17 PECRP02 P8 V DDIO V17 V SS E9 V SS J18 PECRN02 P9 V DDIO V18 V DDCORE Pin GPIO Alternate U13 GPIO[2] IOEXPINTN T12 GPIO[3] PAABN R12 GPIO[4] PAAIN V14 GPIO[5] PAPIN Table 17 PES12N3 Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 16 PES12N3 324-pin Signal Pin-Out (Part 3 of 3)

19 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Power Pins VDDCore V DDCore V DDCore V DDIO V DDPE V DDAPE V TTPE A4 F3 L8 F15 E8 D6 C6 A6 F6 L9 G8 E10 D8 C8 A8 F8 L10 G10 E12 D10 C10 A10 F10 L11 P5 F13 D12 C12 A12 F18 L12 P6 G4 E15 H3 A14 G12 L13 P7 G15 F4 H16 A 1 5H 1 M 1 P 8H 1 5G 5 K 3 B1 H7 M6 P9 J4 G14 K16 B2 H9 M9 P10 K5 H4 N3 B17 H10 M10 P11 K15 H14 N16 B18 H12 M13 P12 L4 M4 P3 C4 H18 M18 P13 L15 M15 P16 C13 J6 P1 P14 N4 C16 J9 P18 R4 N15 D1 J10 R6 R15 D4 J13 R13 V12 D14 J15 T1 D18 K1 T18 E3 K4 V1 E5 K18 V18 E14 L6 F1 L7 Table 18 PES12N3 Power Pins

20 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Ground Pins Vss Vss V ss V ss V ss A1 D15 G11 K10 N8 A2 D16 G13 K11 N9 A17 D17 G16 K12 N10 A18 E4 H2 K13 N11 B4 E6 H5 K14 N12 B6 E7 H6 K17 N13 B8 E9 H8 L3 N14 B10 E11 H11 L5 P2 B12 E13 H13 L14 P4 B14 E16 H17 L16 P15 B15 F2 J3 M2 P17 C3 F5 J5 M3 R3 C5 F7 J7 M5 R5 C7 F9 J8 M7 R14 C9 F11 J11 M8 R16 C11 F12 J12 M11 T2 D2 F14 J14 M12 T3 D3 F16 J16 M14 T16 D5 F17 K2 M16 T17 D7 G3 K6 M17 U3 D9 G6 K7 N5 U16 D11 G7 K8 N6 V2 D13 G9 K9 N7 V17 Table 19 PES12N3 Ground Pins

21 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I T9 System CCLKUS I U9 GPIO_00 I/O U12 General Purpose Input/Output GPIO_01 I/O V13 GPIO_02 I/O U13 GPIO_03 I/O T12 GPIO_04 I/O R12 GPIO_05 I/O V14 GPIO_06 I/O U14 GPIO_07 I/O T13 JTAG_TCK I T4 JTAG JTAG_TDI I U4 JTAG_TDO O T5 JTAG_TMS I U5 JTAG_TRST_N I V5 MSMBADDR_1 I T6 SMBus MSMBADDR_2 I U6 MSMBADDR_3 I V6 MSMBADDR_4 I U7 MSMBCLK I/O T7 MSMBDAT I/O R7 MSMBSMODE I U15 System PEALREV I R9 PCI Express PEARN00 I C15 PEARN01 I B11 PEARN02 I A9 PEARN03 I B3 PEARP00 I C14 PEARP01 I A11 PEARP02 I B9 PEARP03 I A3 PEATN00 O A16 PEATN01 O B13 PEATN02 O B7 Table 20 PES12N3 Alphabetical Signal List (Part 1 of 3)

22 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet PEATN03 O A5 PCI Express PEATP00 O B16 PEATP01 O A13 PEATP02 O A7 PEATP03 O B5 PEBLREV I V10 PEBRN00 I C2 PEBRN01 I J2 PEBRN02 I L1 PEBRN03 I U2 PEBRP00 I C1 PEBRP01 I J1 PEBRP02 I L2 PEBRP03 I U1 PEBTN00 O E1 PEBTN01 O G2 PEBTN02 O N2 PEBTN03 O R1 PEBTP00 O E2 PEBTP01 O G1 PEBTP02 O N1 PEBTP03 O R2 PECLREV I U11 PECRN00 I U17 PECRN01 I L18 PECRN02 I J18 PECRN03 I C17 PECRP00 I U18 PECRP01 I L17 PECRP02 I J17 PECRP03 I C18 PECTN00 O R18 PECTN01 O N17 PECTN02 O G17 PECTN03 O E18 PECTP00 O R17 Signal Name I/O Type Location Signal Category Table 20 PES12N3 Alphabetical Signal List (Part 2 of 3)

23 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet PECTP01 O N18 PCI Express PECTP02 O G18 PECTP03 O E17 PEREFCLKN1 I V4 PCI Express PEREFCLKN2 I V16 PEREFCLKP1 I V3 PEREFCLKP2 I V15 PERSTN I T11 System REFCLKM I T15 PCI Express RSTHALT I R11 System SSMBADDR_1 I V7 SMBus SSMBADDR_2 I T8 SSMBADDR_3 I U8 SSMBADDR_5 I R8 TSTRSVD I T14 System SSMBCLK I/O V8 SMBus SSMBDAT I/O V9 SWMODE_0 I U10 System SWMODE_1 I T10 SWMODE_2 I R10 SWMODE_3 I V11 System V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 18 for a listing of power pins. VSS See Table 19 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 20 PES12N3 Alphabetical Signal List (Part 3 of 3)

24 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet PES12N3 Pinout — Top View 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 C D E F G H J K L M N P R T U V VTTPE (Power) VDDPE (Power) VDDAPE (Power) Signals

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Revision History

July 18, 2006: Publication of YC data sheet. April 4, 2007: In Table 2, revised description for MSMBCLK signal to include “active only when EEPROM data is being loaded.” November 14, 2007: Added new parameter, Termination Resistor, to Table 8, Input Clock Requirements. April 9, 2010: Revised package drawing on pages 25 and 26.

28 of 28 April 9, 2010 IDT 89HPES12N3 Data Sheet CORPORATE HEADQUARTERS

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San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208

Ordering Information

89HPES12N3YCBC 324-pin BC324 package, Commercial Temperature 89HPES12N3YCBCG 324-pin Green BC324 package, Commercial Temperature NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

12N3 12-lane, 3-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BCG324 324-ball BGA, Green BCG AA Revision ID YC Silicon revision