89HPES10T4G2

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◆ High Performance PCI Express Switch – T en 5 Gbps Gen2 PCI Express lanes – Four switch ports  One x4 upstream port  Three x2 downstream ports – Low latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 2.0 compliant ◆ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion – Ability to load device configuration from serial EEPROM ◆ Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution – Incorporates on-chip internal memory for packet buffering and queueing – Integrates ten 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed)  Receive equalization (RxEQ) ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC mother- boards – Supports Hot-Swap Block Diagram Figure 1 Internal Block Diagram 4-Port Switch Core / 10 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer (Port 0) (Port 2) SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer (Port 4) (Port 6) 89HPES10T4G2 Data Sheet 10-Lane 4-Port Gen2 PCI Express® Switch

2 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Express Power Management Interface specifica- tion (PCI-PM 1.2) – Supports PCI Express Active State Power Management (ASPM) link state – Supports PCI Express Power Budgeting Capability – Supports the optional PCI Express SerDes Transmit Low- Swing Voltage Mode – Unused SerDes are disabled and can be powered-off. ◆ Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Nine General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in a 19mm x 19mm 324-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES10T4G2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 12 GBps (96 Gbps) of aggregated, full-duplex switching capacity through 10 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of band- width in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. The PES10T4G2 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable effi- cient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. Figure 2 I/O Expansion Application SMBus Interface The PES10T4G2 contains two SMBus interfaces. The slave inter- face provides full access to the configuration registers in the PES10T4G2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES10T4G2 to be over- ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be config- ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment MemoryMemoryMemory Processor MemoryNorth Bridge PES10T4G2 I/O 10GbE I/O 10GbE I/O SATAPCI Express Slot Processor x2 x2 x2

3 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuratio n, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES10T4G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES10T4G2 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBu s arbitration. To support these systems, the PES10T4G2 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operat e as two independent buses and thus multi-master arbitration is never required. The PES10T4G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system pro gramming of the serial EEPROM. Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES10T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES10T4G2 utilizes an external I/O expander, such as that used on PC mother boards, connected to the SMBus master interface. Following res et and configura- tion, whenever the state of a Hot-Plug output needs to be modifi ed, the PES10T4G2 generates an SMBus transaction to the I/O exp ander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received o n the IOEXPINTN input pin (alternate function of GPIO) of the PES10T4G2. In response to an I/O expander interrupt, the PES10T4G2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES10T4G2 provides 9 General Purpose Input/Output (GPIO) pi ns that may be used by the system designer as bit I/O ports. Eac h GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip fu nctions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Processor PES10T4G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM Processor PES10T4G2 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses

4 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES10T4G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Si gnals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES10T4G2, the three downstream ports are labeled ports 2, 4, and 6. Signal Type Name/Description PE0RN[3:0] PE0RP[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TN[3:0] PE0TP[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. Port 0 is the upstream port. PE2RN[1:0] PE2RP[1:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TN[1:0] PE2TP[1:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE4RN[1:0] PE4RP[1:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TN[1:0] PE4TP[1:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 4. PE6RN[1:0] PE6RP[1:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE6TN[1:0] PE6TP[1:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 6. PEREFCLKP[0] PEREFCLKN[0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN. Table 2 PCI Express Interface Pins Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. Table 3 SMBus Interface Pins (Part 1 of 2)

5 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O expander interrupt 0 input. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input. GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output. GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6. Table 4 General Purpose I/O Pins Signal Type Name/Description Table 3 SMBus Interface Pins (Part 2 of 2)

6 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each down- stream port’s PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES10T4G2 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES10T4G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES10T4G2 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. Table 5 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 6 Test Pins (Part 1 of 2)

7 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Signal Type Name/Description REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES4 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES6 I/O Port 6 External Reference Resistor. Provides a reference for the Port 6 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. V DDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V). VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS I Ground. Table 7 Power, Ground, and SerDes Resistor Pins Signal Type Name/Description Table 6 Test Pins (Part 2 of 2)

8 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Pin Characteristics Note: Some input pads of the PES10T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[3:0] I PCIe differential2 Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE2RN[1:0] I PE2RP[1:0] I PE2TN[1:0] O PE2TP[1:0] O PE4RN[1:0] I PE4RP[1:0] I PE4TN[1:0] O PE4TP[1:0] O PE6RN[1:0] I PE6RP[1:0] I PE6TN[1:0] O PE6TP[1:0] O PEREFCLKN[0] I HCSL Diff. Clock Input Refer to Table 9 PEREFCLKP[0] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI 3 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[11,7:0] I/O LVTTL STI, High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I Input pull-up MSMBSMODE I Input pull-down PERSTN I STI RSTHALT I Input pull-down SWMODE[2:0] I Input pull-down Table 8 Pin Characteristics (Part 1 of 2)

9 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up SerDes Reference Resistors REFRES0 I/O Analog REFRES2 I/O REFRES4 I/O REFRES6 I/O 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. 3. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2)

10 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Logic Diagram — PES10T4G2 Figure 4 PES10T4G2 Logic Diagram PE0TP[0] Reference Clocks PEREFCLKP[0] PEREFCLKN[0] JTAG_TCK GPIO[11,7:0]

9 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[2:0] CCLKDS PERSTN REFCLKM MSMBSMODE PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PCI Express Switch SerDes Input PE0TN[0] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE2RP[0] PE2RN[0] PE2RP[1] PE2RN[1] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PE2TP[1] PE2TN[1] PCI Express Switch SerDes Output Port 2 Port 2 PE4RP[0] PE4RN[0] PE4RP[1] PE4RN[1] PCI Express Switch SerDes Input PE4TP[0] PE4TN[0] PE4TP[1] PE4TN[1] PCI Express Switch SerDes Output Port 4 Port 4 PES10T4G2 REFRES0 SerDes Reference Resistors REFRES2 REFRES4 VDDPEHA Reference Clock Frequency Selection VDDPETA PE6RP[0] PE6RN[0] PE6RP[1] PE6RN[1] PCI Express Switch SerDes Input Port 6 PE6TP[0] PE6TN[0] PE6TP[1] PE6TN[1] PCI Express Switch SerDes Output Port 6 REFRES6

11 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15. AC Timing Characteristics Parameter Description Condition Min Typical Max Unit RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz TC-RISE Rising edge rate Differential 0.6 4 V/ns TC-FALL Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 mV VIL Differential input low voltage Differential -150 mV voltage Single-ended +250 +550 mV VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended +140 mV VRB Ring back voltage margin Differential -100 +100 mV TSTABLE Time before VRB is allowed Differential 500 ps TPERIOD-AVG Average clock period accuracy -300 2800 ppm trum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps Duty Cycle Duty cycle 40 60 % Rise/Fall Matching Single ended rising Refclk edge rate ver- sus falling Refclk edge rate 20 % Z C-DC Clock source output DC impedance 40 60 Ω Table 9 Input Clock Requirements Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 PCIe Transmit UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps TTX-EYE Minimum Tx Eye Width 0.75 0.75 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.125 UI TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI TTX- IDLE-MIN Minimum time in idle 20 20 UI Table 10 PCIe AC Timing Characteristics (Part 1 of 2)

12 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 88 n s TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 8 8 ns TTX-SKEW Transmitter data skew between any 2 lanes 1.3 1.3 ns TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA 0.9 UI TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI PCIe Receive UI Unit Interval 399.88 400 400.12 199.94 200.06 ps TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-SKEW Lane to lane input skew 20 8 ns TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps TRX-HF-DJ-DD Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[11,7:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns Table 11 GPIO AC Timing Characteristics Parameter Description Gen 1 Gen 2 Units Min1 Typ1 Max1 Min1 Typ1 Max1 Table 10 PCIe AC Timing Characteristics (Part 2 of 2)

13 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Figure 5 JTAG AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 5. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset sta te. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

14 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Recommended Operating Supply Voltages Absolute Maximum Voltage Rating Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating vol tages in Table 13. The absolute maximum operating voltages in Table 14 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability. Power-Up/Power-Down Sequence During power supply ramp-up, V DDCORE must remain at least 1.0V below V DDI/O at all times. There are no other power-up sequence require- ments for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V VDDPEA1 1. VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. PCI Express Analog Power 0.95 1.0 1.1 V VDDPEHA2 2. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. PCI Express Analog High Power 2.25 2.5 2.75 V VDDPETA1 PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V Table 13 PES10T4G2 Operating Voltages Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply Table 14 PES10T4G2 Absolute Maximum Voltage Rating Grade Temperature Commercial 0 °C to +70°C Ambient Industrial -40 °C to +85°C Ambient Table 15 PES10T4G2 Operating Temperatures

15 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Thermal Considerations This section describes thermal considerations for the PES10T4G2 (19mm2 CABGA324 package). The data in Table 17 below contains information that is relevant to the thermal performance of the PES10T4G2 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 17. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 17), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. Number of active Lanes per Port Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.1V Typ 3.3V Max 3.465V Typ Power Max Power 4/2/2/2 (Full swing) mA 531 781 402 484 194 275 207 238 3 4 2/2/2/2 (Full swing) mA 440 550 320 352 138 165 108 117 3 4 Table 16 PES10T4G2 Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oC Maximum TA(max) Ambient Temperature 70 oC Maximum θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 23.6 oC/W Zero air flow 16.8 oC/W 1 m/S air flow 15.4 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 14.5 oC/W θJC Thermal Resistance, Junction-to-Case 7.6 oC/W P Power Dissipation of the Device 2.43 Watts Maximum Table 17 Thermal Specifications for PES10T4G2, 19x19 mm CABGA324 Package

16 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- 3.5dB De-emphasized differential output voltage VTX-DE-RATIO- 6.0dB De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage 0 3.6 0 3.6 V VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC-active- idle-delta Abs delta of DC common mode voltage between L0 and idle 100 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 66 d B ZTX-DIFF-DC DC Differential TX impedance 80 100 120 120 Ω VTX-CM-ACpp Peak-Peak AC Common NA 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 0 3.6 0 3.6 V VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detec- tion 600 600 mV ITX-SHORT Transmitter Short Circuit Current Limit 09 0 9 0 m A Table 18 DC Electrical Characteristics (Part 1 of 2)

17 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Serial Link (cont.) PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to- peak) 175 1200 120 1200 mV RLRX-DIFF Receiver Differential Return Loss 10 10 dB 0.05 - 1.25GHz 8 1.25 - 2.5GHz RLRX-CM Receiver Common Mode Return Loss 66 d B ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Refer to return loss spec Ω ZRX--DC DC common mode impedance 40 50 60 40 60 Ω ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 50k Ω ZRX-HIGH-IMP-DC- POS DC input CM input impedance for V>0 during reset or power down 50k 50k Ω ZRX-HIGH-IMP-DC- NEG DC input CM input impedance for V<0 during reset or power down 1.0k 1.0k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 65 175 mV VRX-CM-ACp Receiver AC common-mode peak voltage 150 150 mV V RX-CM-ACp PCIe REFCLK CIN Input Capacitance 1.5 — 1.5 — pF Other I/Os LOW Drive Output IOL —2 . 5— —2 . 5 — m A V OL = 0.4v IOH —- 5 . 5— —- 5 . 5 — m A V OH = 1.5V High Drive Output IOL — 12.0 — — 12.0 — mA V OL = 0.4v Schmitt Trig- ger Input (STI) VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Input V IL -0.3 — 0.8 -0.3 — 0.8 V — VIH 2.0 — V DDI/O + 0.5 2.0 — V DDI/O + 0.5 Capacitance C IN — — 8.5 — — 8.5 pF — Leakage Inputs — — + 10 — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 — — + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 — — + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. I/O Type Parameter Description Gen1 Gen2 Unit Condi- tions Min1 Typ1 Max1 Min1 Typ1 Max1 Table 18 DC Electrical Characteristics (Part 2 of 2)

18 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet The following table lists the pin numbers and signal names for the PES10T4G2 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B17 SWMODE_1 D15 GPIO_01 1 F13 V SS A2 V SS B18 SWMODE_2 D16 PE4TP00 F14 V DDCORE A3 PE0RN00 C1 JTAG_TCK D17 V DDPETA F15 V DDI/O A4 PE0RP00 C2 PE0TP00 D18 GPIO_03 F16 V SS A5 V SS C3 PE0TN00 E1 V SS F17 V DDPEA A6 PE0RN01 C4 V SS E2 V DDPEA F18 PE4RP00 A7 PE0RP01 C5 PE0TP01 E3 NC G1 V SS A8 V SS C6 PE0TN01 E4 JTAG_TMS G2 V DDPEA A9 PEREFCLKP0 C7 V DDPEA E5 V DDCORE G3 V DDPETA A10 PEREFCLKN0 C8 V DDPETA E6 V DDI/O G4 V SS A11 V SS C9 V SS E7 V DDPEHA G5 V DDCORE A12 PE0RN02 C10 PE0TP02 E8 V DDPEHA G6 V DDI/O A13 PE0RP02 C11 PE0TN02 E9 V DDPEHA G7 V SS A14 V SS C12 V DDPETA E10 V DDCORE G8 V SS A15 PE0RN03 C13 PE0TP03 E11 V DDPEHA G9 V DDCORE A16 PE0RP03 C14 PE0TN03 E12 V DDI/O G10 V SS A17 CCLKDS C15 V SS E13 V DDCORE G11 V SS A18 SWMODE_0 C16 CCLKUS E14 V DDI/O G12 V SS B1 JTAG_TDI C17 PERSTN E15 GPIO_00 1 G13 V DDI/O B2 V SS C18 GPIO_02 1 E16 PE4TN00 G14 V DDPEHA B3 V SS D1 V SS E17 V SS G15 V SS B4 V SS D2 JTAG_TDO E18 PE4RN00 G16 PE4TP01 B5 V SS D3 V DDPETA F1 V SS G17 V DDPETA B6 V SS D4 JTAG_TRST_N F2 V DDPEHA G18 V SS B7 V SS D5 V DDI/O F3 NC H1 V SS B8 V SS D6 V DDPEHA F4 V DDCORE H2 V SS B9 V DDPEA D7 V SS F5 V DDI/O H3 NC B10 V DDPEA D8 V DDCORE F6 V SS H4 V SS B11 V DDPETA D9 V DDCORE F7 V DDCORE H5 V DDPEHA B12 V SS D10 REFRES0 F8 V SS H6 V SS B13 V SS D11 V DDPEA F9 V SS H7 V DDCORE B14 V DDCORE D12 V DDCORE F10 V SS H8 V SS B15 V SS D13 V SS F11 V SS H9 V SS B16 V DDPEA D14 RSTHALT F12 V DDCORE H10 V SS Table 19 PES10T4G2 324-pin Signal Pin-Out (Part 1 of 3)

19 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet H11 V DDCORE K13 V SS M15 V SS P17 V SS H12 V SS K14 V DDCORE M16 V DDPETA P18 V SS H13 V SS K15 V SS M17 V DDPEA R1 PE2RP00 H14 V DDPEHA K16 NC M18 V SS R2 V SS H15 V DDCORE K17 REFRES4 N1 PE2RN01 R3 PE2TP00 H16 PE4TN01 K18 V SS N2 V DDPEA R4 SSMBADDR_2 H17 V SS L1 V SS N3 V SS R5 V DDI/O H18 PE4RN01 L2 V DDPEA N4 V SS R6 MSMBSMODE J1 V SS L3 PE2TN01 N5 V DDCORE R7 V DDCORE J2 V DDPETA L4 V DDCORE N6 V SS R8 V SS J3 NC L5 V DDPEHA N7 V DDI/O R9 V SS J4 REFRES2 L6 V SS N8 V SS R10 V SS J5 V DDCORE L7 V SS N9 V SS R11 V DDCORE J6 V SS L8 V SS N10 V SS R12 V SS J7 V SS L9 V SS N11 V SS R13 V DDI/O J8 V SS L10 V SS N12 V DDI/O R14 V SS J9 V DDCORE L11 V SS N13 V SS R15 V SS J10 V SS L12 V DDCORE N14 V DDCORE R16 GPIO_04 1 J11 V SS L13 V SS N15 V DDCORE R17 V DDPEA J12 V DDCORE L14 V DDPEHA N16 NC R18 V SS J13 V SS L15 V SS N17 V DDPEHA T1 PE2RN00 J14 V DDPEHA L16 NC N18 V SS T2 V DDPETA J15 V SS L17 V DDPETA P1 V SS T3 V SS J16 V DDPEA L18 V SS P2 V SS T4 SSMBADDR_5 J17 V DDPEA M1 PE2RP01 P3 PE2TN00 T5 V SS J18 PE4RP01 M2 V DDPETA P4 SSMBADDR_1 T6 MSMBDAT K1 V SS M3 PE2TP01 P5 V DDCORE T7 MSMBADDR_3 K2 V DDPEA M4 V SS P6 V DDI/O T8 V DDPEA K3 V SS M5 V DDPEHA P7 V DDCORE T9 PE6TN01 K4 V SS M6 V DDI/O P8 V DDPEHA T10 PE6TP01 K5 V DDPEHA M7 V DDCORE P9 V DDPEHA T11 V DDPEA K6 V SS M8 V SS P10 V DDCORE T12 PE6TN00 K7 V DDCORE M9 V DDCORE P11 V DDPEHA T13 PE6TP00 K8 V SS M10 V SS P12 V DDCORE T14 V DDPETA K9 V SS M11 V DDCORE P13 V DDCORE T15 V SS K10 V DDCORE M12 V SS P14 V DDI/O T16 GPIO_06 K11 V SS M13 V DDI/O P15 V SS T17 GPIO_05 K12 V SS M14 V DDCORE P16 NC T18 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES10T4G2 324-pin Signal Pin-Out (Part 2 of 3)

20 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Alternate Signal Functions No Connection Pins U1 V SS U10 V DDPETA V1 V SS V10 V SS U2 V SS U11 V SS V2 V SS V11 PE6RP00 U3 SSMBCLK U12 V SS V3 SSMBDAT V12 PE6RN00 U4 SSMBADDR_3 U13 V SS V4 V SS V13 V SS U5 V SS U14 V SS V5 MSMBADDR_4 V14 V SS U6 MSMBCLK U15 REFCLKM V6 MSMBADDR_2 V15 V SS U7 MSMBADDR_1 U16 GPIO_07 1 V7 REFRES6 V16 GPIO_11 1 U8 V DDPEA U17 V SS V8 PE6RP01 V17 V SS U9 V SS U18 V SS V9 PE6RN01 V18 V SS Pin GPIO Alternate E15 GPIO_00 P2RSTN D15 GPIO_01 P4RSTN C18 GPIO_02 IOEXPINTN0 R16 GPIO_04 IOEXPINTN2 U16 GPIO_07 GPEN V16 GPIO_11 P6RSTN Table 20 PES10T4G2 Alternate Signal Functions NC Pins K16 L16 N16 P16 Table 21 PES10T4G2 No Connection Pins Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES10T4G2 324-pin Signal Pin-Out (Part 3 of 3)

21 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Power Pins VDDCore V DDCore V DDI/O V DDPEA V DDPEHA V DDPETA B 1 4 K 7D 5B 9D 6 B 1 1 D 8K 1 0E 6B 1 0E 7 C 8 D9 K14 E12 B16 E8 C12 D12 L4 E14 C7 E9 D3 E5 L12 F5 D11 E11 D17 E10 M7 F15 E2 F2 G3 E13 M9 G6 F17 G14 G17 F4 M11 G13 G2 H5 J2 F7 M14 M6 J16 H14 L17 F12 N5 M13 J17 J14 M2 F14 N14 N7 K2 K5 M16 G5 N15 N12 L2 L5 T2 G9 P5 P6 M17 L14 T14 H7 P7 P14 N2 M5 U10 H11 P10 R5 R17 N17 H15 P12 R13 T8 P8 J5 P13 T11 P9 J9 R7 U8 P11 J12 R11 Table 22 PES10T4G2 Power Pins

22 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Ground Pins Vss Vss Vss Vss Vss Vss A1 E1 H6 K12 N6 T15 A2 E17 H8 K13 N8 T18 A5 F1 H9 K15 N9 U1 A8 F6 H10 K18 N10 U2 A11 F8 H12 L1 N11 U5 A14 F9 H13 L6 N13 U9 B2 F10 H17 L7 N18 U11 B3 F11 J1 L8 P1 U12 B4 F13 J6 L9 P2 U13 B5 F16 J7 L10 P15 U14 B6 G1 J8 L11 P17 U17 B7 G4 J10 L13 P18 U18 B8 G7 J11 L15 R2 V1 B12 G8 J13 L18 R8 V2 B13 G10 J15 M4 R9 V4 B15 G11 K1 M8 R10 V10 C4 G12 K3 M10 R12 V13 C9 G15 K4 M12 R14 V14 C15 G18 K6 M15 R15 V15 D1 H1 K8 M18 R18 V17 D7 H2 K9 N3 T3 V18 D13 H4 K11 N4 T5 Table 23 PES10T4G2 Ground Pins

23 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I A17 System CCLKUS I C16 GPIO_00 I/O E15 General Purpose Input/Output GPIO_01 I/O D15 GPIO_02 I/O C18 GPIO_03 I/O D18 GPIO_04 I/O R16 GPIO_05 I/O T17 GPIO_06 I/O T16 GPIO_07 I/O U16 GPIO_11 I/O V16 JTAG_TCK I C1 JTAG JTAG_TDI I B1 JTAG_TDO O D2 JTAG_TMS I E4 JTAG_TRST_N I D4 MSMBADDR_1 I U7 SMBus MSMBADDR_2 I V6 MSMBADDR_3 I T7 MSMBADDR_4 I V5 MSMBCLK I/O U6 MSMBDAT I/O T6 MSMBSMODE I R6 System No Connection See Table 21 for a list of NC pins PE0RN00 I A3 PCI Express PE0RN01 I A6 PE0RN02 I A12 PE0RN03 I A15 PE0RP00 I A4 PE0RP01 I A7 PE0RP02 I A13 PE0RP03 I A16 PE0TN00 O C3 PE0TN01 O C6 Table 24 89PES10T4G2 Alphabetical Signal List (Part 1 of 3)

24 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet PE0TN02 O C11 PCI Express (Cont.) PE0TN03 O C14 PE0TP00 O C2 PE0TP01 O C5 PE0TP02 O C10 PE0TP03 O C13 PE2RN00 I T1 PE2RN01 I N1 PE2RP00 I R1 PE2RP01 I M1 PE2TN00 O P3 PE2TN01 O L3 PE2TP00 O R3 PE2TP01 O M3 PE4RN00 I E18 PE4RN01 I H18 PE4RP00 I F18 PE4RP01 I J18 PE4TN00 O E16 PE4TN01 O H16 PE4TP00 O D16 PE4TP01 O G16 PE6RN00 I V12 PE6RN01 I V9 PE6RP00 I V11 PE6RP01 I V8 PE6TN00 O T12 PE6TN01 O T9 PE6TP00 O T13 PE6TP01 O T10 PEREFCLKN0 I A10 PEREFCLKP0 I A9 PERSTN I C17 System REFCLKM I U15 PCI Express Signal Name I/O Type Location Signal Category Table 24 89PES10T4G2 Alphabetical Signal List (Part 2 of 3)

25 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet REFRES0 I/O D10 SerDes Reference Resistors REFRES2 I/O J4 REFRES4 I/O K17 REFRES6 I/O V7 RSTHALT I D14 System SSMBADDR_1 I P4 SMBus SSMBADDR_2 I R4 SSMBADDR_3 I U4 SSMBADDR_5 I T4 SSMBCLK I/O U3 SMBus SSMBDAT I/O V3 SWMODE_0 I A18 System SWMODE_1 I B17 SWMODE_2 I B18 V DDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA See Table 22 for a listing of power pins. VSS See Table 23 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 24 89PES10T4G2 Alphabetical Signal List (Part 3 of 3)

26 of 30 August 10, 2011 IDT 89HPES10T4G2 Data Sheet PES10T4G2 Pinout — Top View 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 A B 17 18 C D E F G H J K L M N P R T U V 1 2 3 4 5 6 7 8 9 1 01 1 1 21 31 4 1 51 6 17 18 A B C D E F G H J K L M N P R T U V Vss (Ground) VDDCore (Power) VDDI/O (Power) VDDPETA (Transmitter Power) VDDPEA (Analog Power) VDDPEHA (High Analog Power) SignalsX No Connect X X X X X X X X X X X X X X

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Revision History

August 10, 2011: Publication of final data sheet.

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Ordering Information

89HPES10T4G2ZABC 324-ball BGA package, Commercial Temperature 89HPES10T4G2ZABCG 324-ball Green BGA package, Commercial Temperature 89HPES10T4G2ZABCI 324-ball BGA package, Industrial Temperature 89HPES10T4G2ZABCGI 324-ball Green BGA package, Industrial Temperature NN A AAA NNAN AAA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

10T4 10-lane, 4-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character AA Device Revision ZA ZA revision AN Generation Series G2 PCIe Gen 2 BC324 324-ball CABGA BC BCG324 324-ball CABGA, Green BCG I Industrial Temperature (-40° C to +85° C Ambient)