894D115I-04 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Integrated Device Technology
  • PDF pages: 16

Technical content

Features

  • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3)
  • Input: NRZ data (622.08 or 155.52 Mbit/s)
  • Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s
  • Internal PLL for clock generation and clock recovery
  • Differential inputs can accept LVPECL levels
  • Differential LVDS data and clock outputs
  • Lock reference input and PLL lock output
  • 19.44MHz reference clock input
  • Full 3.3V supply mode
  • -40°C to 85°C operating temperature
  • Available in lead-free (RoHS 6) package
  • See 894D115I for a clock/data recovery circuit with a TSSOP EPAD package and LVPECL outputs
  • See 894D115I-01 for a clock/data recovery circuit with LVPECL outputs Block Diagram Pin Assignment 894D115I-04 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View GND LOCK_REFN REF_CLK STS12 LOCK_DET GND_PLL nDATA_IN DATA_IN VDDA VDD VDDA GND_PLL CAP nCAP BYPASS SD DATA_OUT nDATA_OUT CLK_OUT nCLK_OUT 894D115I-04 Data Sheet OC-12/STM-4 AND OC-3/STM-1 Clock/Data Recovery Device

Table 1. Signal Detect/PLL BYPASS Operation Control Table Table 2. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.

1011 D A T A _ I N P L L C l o c k

1010 L O W P L L C l o c k

1001 L O W P L L C l o c k

1000 L O W P L L C l o c k

0011 D A T A _ I N P L L C l o c k

0010 L O W P L L C l o c k

0001 L O W P L L C l o c k

0000 L O W P L L C l o c k

DDA Power Analog supply pins. 2 DATA_IN Input Pulldown Non-inverting differential signal input. Pulldown Inverting differential signal input. VDD/2 default when left floating. 4, 19 GND_PLL Power Power supply ground. 5 LOCK_DT Output Lock detect output. See Table 4A. Single-ended LVPECL interface levels. 6 STS12 Input Pulldown STM-4 (OC-12, STS-12) or STM-1 (OC-3, STS-3) selection mode. See Table 4B. LVCMOS/LVTTL interface levels. 7 REF_CLK Input Pulldown Reference clock input of 19.44MHz. LVCMOS/LVTTL interface levels. 8 LOCK_REFN Input Pullup Lock to REF_CLK input. S ee Table 4C. LVCMOS/LVTTL interface levels. 9 GND Power Power supply ground. 10 V DD Power Core supply pin. CLK_OUT Output Differential clock output pair. LVDS interface levels. DATA_OUT Output Differential clock output pair. LVDS interface levels. electro-optical module. See Table 4D. Single-ended LVPECL interface levels. 16 BYPASS Input Pulldown PLL bypass mode. See Table 4E. LVCMOS/LVTTL interface levels. 17, 18 nCAP , CAP Input External loop filter (1.0µF ±10%).

Table 3. Pin Characteristics A. Internal oscillator and REF_CLK input frequency are not within 500ppm of each other. B. SD input is at logic LOW state. C. LOCK_REFN is at logic LOW state. input data stream. The output clock frequency is 155.52MHz. input data stream. The output clock frequency is 622.08MHz. of the reference clock (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state. (DATA_OUT = L, nDATA_OUT = H).

5©2016 Integrated Device Technology, Inc Revision C January 27, 2016 894D115I-04 Data Sheet Table 4E. BYPASS Mode Configuration Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, T = -40°C to 85°C Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, T = -40°C to 85°C Input OperationBYPASS 0 Normal operation. 1 PLL bypassed (for factory test). The inverted RE F_CLK input signal is output at CLK_OUT/nCLK_OUT. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current Outputs, IO (LVPECL) Continuous Current Surge Current 10mA 15mA 50mA 100mA Package Thermal Impedance,  JA 81.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.10 3.3 V DD V IDD Power Supply Current 112 mA IDDA Analog Supply Current 10 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V

6©2016 Integrated Device Technology, Inc Revision C January 27, 2016 894D115I-04 Data Sheet Table 5C. Differential DC Characteristics, VDD = 3.3V ± 5%, T = -40°C to 85°C Table 5D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, T = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDD – 2V. Table 5E. LVDS DC Characteristics, VDD = 3.3V ± 5%, T = -40°C to 85°C IIH Input High Current REF_CLK, STS12, BYPASS VDD = VIN = 3.465V 150 µA LOCK_REFN V DD = VIN = 3.465V 10 µA IIL Input Low Current REF_CLK, STS12, BYPASS VDD = 3.465V, VIN = 0V -10 µA LOCK_REFN V DD = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current DATA_IN/nDATA_IN V DD = VIN = 3.465V 150 µA IIL Input Low Current DATA_IN V DD = 3.465V, VIN = 0V -10 µA nDATA_IN V DD = 3.465V, VIN = 0V -150 µA VIH Input High Voltage V DD – 1.75 V DD – 0.4 V VIL Input Low Voltage V DD – 2.0 V DD – 0.7 V VIN Differential Input Voltage 250 mV Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage SD V DD – 1.125 V VIL Input Low Voltage SD VDD – 1.5 V IIH Input High Current SD V DD = VIN = 3.465V 150 µA IIL Input Low Current SD V DD = 3.465V, VIN = 0V -10 µA VOH Output High Voltage; NOTE 1 LOCK_DT V DD – 1.4 V DD – 0.9 V VOL Output Low Voltage NOTE 1 LOCK_DT V DD – 2.0 V DD – 1.7 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 247 380 454 mV VOD VOD Magnitude Change 5 50 mV VOS Offset Voltage 1.125 1.25 1.375 V VOS VOS Magnitude Change 5 50 mV Symbol Parameter Test Conditio ns Minimum Typical Maximum Units

Table 6. AC Characteristics, VDD = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C NOTE 1: See diagram in Parameter Measurement Information section.

8©2016 Integrated Device Technology, Inc Revision C January 27, 2016 894D115I-04 Data Sheet Parameter Measurement Information LVDS 3.3V Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period Jitter Tolerance Specification Setup/Hold Time Differential Input Level 3.3V ±5% VDD VDDA nCLK_OUT, nDATA_OUT CLK_OUT, DATA_OUT Requirement Mask Input Jitter Amplitude (UIpp) Jitter Frequency (Hz) slope = -20dB/decade 1.5 0.15 10 30 300 25k 250k 5M tH tSU The re-timed data output (DATA_OUT) can be captured with the rising edge of the clock output signal (CLOCK_OUT). DATA_OUT is valid the specified setup time before the rising CLK_OUT signal and remains valid the specified hold time after nDATA_OUT DATA_OUT CLK_OUT nCLK_OUT VIH Cross Points VPP ΔVIN = DATA_IN - nDATA_IN VDD nDATA_IN DATA_IN GND

9©2016 Integrated Device Technology, Inc Revision C January 27, 2016 894D115I-04 Data Sheet Parameter Measurement Information, continued Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup 20% 80% 80% 20% tR tF VOD nCLK_OUT, CLK_OUT, nDATA_OUT DATA_OUT

This section provides information on power dissipation and junction temperature for the 894D115I-04. Equations and example calculations are also provided. The total power dissipation for the 894D115I-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. Lower temperature refers to ambient temperature, maximum temperature refers to case temperature. Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection

Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP

13©2016 Integrated Device Technology, Inc Revision C January 27, 2016 894D115I-04 Data Sheet

Ordering Information

Table 10. Ordering Information

14©2016 Integrated Device Technology, Inc Revision C January 27, 2016 894D115I-04 Data Sheet Revision History Sheet Rev Table Page Description of Change Date B T6 7 AC Characteristics Table - corrected typo for Hold Time, STS-3 spec. from 300ps to 3000ps max. 6/24/08 C T5C 6 Differential DC Characteristics Table - deleted VPP and VCMR specs and added VIH, VIL, VIN specs. Parameter Measurement Information Section - updated Differential Input Level diagram. 10/15/08 C T10 Removed ICS from part numbers where needed. General Description - Deleted ICS chip. Ordering Information - Deleted quantity from tape and reel. Deleted LF note below table. Updated header and footer. 1/27/16

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