894D115I-01 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3)
  • Input: NRZ data (622.08 or 155.52 Mbit/s)
  • Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s
  • Internal PLL for clock generation and clock recovery
  • Differential inputs can accept LVPECL levels
  • Differential LVPECL data and clock outputs
  • Lock reference input and PLL lock output
  • 19.44MHz reference clock input
  • Full 3.3V supply mode
  • -40°C to 85°C operating temperature
  • Available in lead-free (RoHS 6) package
  • See ICS894D115I for a clock/data recovery circuit with a TSSOP EPAD package
  • See ICS894D115I-04 for a clock/data recovery circuit with LVDS outputs Block Diagram Pin Assignment 894D115I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View VEE LOCK_REFN REF_CLK STS12 LOCK_DET VEE_PLL nDATA_IN DATA_IN VCCA VCC VCCA VEE_PLL CAP nCAP BYPASS SD DATA_OUT nDATA_OUT CLK_OUT nCLK_OUT LOCK_DET DATA_OUT nDATA_OUT CLK_OUT nCLK_OUT STS12 nCAP CAP BYPASS DATA_IN nDATA_IN SD LOCK_REFN REF_CLK PLL Pullup/Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pullup

Table 1. Signal Detect/PLL BYPASS Operation Control Table Table 2. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values. 1, 20 V CCA Power Analog supply pins. 2 DATA_IN Input Pulldown Non-inverting differential signal input. Pulldown Inverting differential signal input. VCC/2 default when left floating. 4, 19 V EE_PLL Power Negative supply pins. 5 LOCK_DT Output Lock detect output. See Table 4A. Single-ended LVPECL interface levels. 6 STS12 Input Pulldown STM-4 (OC-12, STS-12) or STM-1 (OC-3, STS-3) selection mode. See Table 4B. LVCMOS/LVTTL interface levels. 7 REF_CLK Input Pulldown Reference clock input of 19.44MHz. LVCMOS/LVTTL interface levels. 8 LOCK_REFN Input Pullup Lock to REF_CLK input. S ee Table 4C. LVCMOS/LVTTL interface levels. 9V EE Power Negative supply pin. 10 V CC Power Core supply pin. CLK_OUT Output Differential clock output pair. LVPECL interface levels. DATA_OUT Output Differential clock output pair. LVPECL interface levels. electro-optical module. See Table 4D. Single-ended LVPECL interface levels. 16 BYPASS Input Pulldown PLL bypass mode. See Table 4E. LVCMOS/LVTTL interface levels. 17, 18 nCAP , CAP Input External loop filter (1.0µF ±10%).

Table 3. Pin Characteristics A. Internal oscillator and REF_CLK input frequency are not within 500ppm of each other. B. SD input is at logic LOW state. C. LOCK_REFN is at logic LOW state. input data stream. The output clock frequency is 155.52MHz. input data stream. The output clock frequency is 622.08MHz. of the reference clock (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state. (DATA_OUT = L, nDATA_OUT = H).

OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 5 Rev C 2/19/15 894D115I-01 DATA SHEET Table 4E. BYPASS Mode Configuration Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Table 5B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Input OperationBYPASS 0 Normal operation. 1 PLL bypassed (for factory test). The inverted RE F_CLK input signal is output at CLK_OUT/nCLK_OUT. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 81.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.10 3.3 V CC V IEE Power Supply Current 80 mA ICCA Analog Supply Current 10 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_CLK, STS12, BYPASS VCC = VIN = 3.465V 150 µA LOCK_REFN V CC = VIN = 3.465V 10 µA IIL Input Low Current REF_CLK, STS12, BYPASS VCC = 3.465V, VIN = 0V -10 µA LOCK_REFN V CC = 3.465V, VIN = 0V -150 µA

Rev C 2/19/15 6 OC-12/STM-4 AND OC-3 /STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Table 5C. Differential DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Table 5D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VCC – 2V. Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current DATA_IN/nDATA_IN V CC = VIN = 3.465V 150 µA IIL Input Low Current DATA_IN V CC = 3.465V, VIN = 0V -10 µA nDATA_IN V CC = 3.465V, VIN = 0V -150 µA VIH Input High Voltage VDD – 1.75 V DD – 0.4 V VIL Input Low Voltage VDD – 2.0 V DD – 0.7 V VIN Differential Input Voltage 250 mV Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage SD VCC – 1.125 V VIL Input Low Voltage SD VCC – 1.5 V IIH Input High Current SD V CC = VIN = 3.465V 150 µA IIL Input Low Current SD V CC = 3.465V, VIN = 0V -10 µA VOH Output High Voltage; NOTE 1 VCC – 1.4 V CC – 0.9 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 V CC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

Table 6. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C Parameter Measurement Information section.

Rev C 2/19/15 8 OC-12/STM-4 AND OC-3 /STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Parameter Measurement Information 3.3V Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period Jitter Tolerance Specification Setup/Hold Time Differential Input Level VCC .2V -1.3V±0.165V VCCA nCLK_OUT, nDATA_OUT CLK_OUT, DATA_OUT Requirement Mask Input Jitter Amplitude (UIpp) Jitter Frequency (Hz) slope = -20dB/decade 1.5 0.15 10 30 300 25k 250k 5M tH tSU The re-timed data output (DATA_OUT) can be captured with the rising edge of the clock output signal (CLOCK_OUT). DATA_OUT is valid the specified setup time before the rising CLK_OUT signal and remains valid the specified hold time after the rising edge of the CLK_OUT signal. nDATA_OUT DATA_OUT CLK_OUT nCLK_OUT VIH Cross Points VPP ∆ VIN = DATA_IN - nDATA_IN VCC nDATA_IN DATA_IN VEE

OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 9 Rev C 2/19/15 894D115I-01 DATA SHEET Parameter Measurement Information, continued Output Rise/Fall Time

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The 894D115I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VCCA pin. Figure 2. Power Supply Filtering protection. A 1k resistor can be used. pair should either be left floating or terminated.

Rev C 2/19/15 10 OC-12/STM-4 AND OC-3 /STM-1 CLOCK/DATA RECOVERY DEVICE 894D115I-01 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

This section provides information on power dissipation and junction temperature for the 894D115I-01. Equations and example calculations are also provided. The total power dissipation for the 894D115I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for HiPerClockS devices is 125°C. Lower temperature refers to ambient temperature, maximum temperature refers to case temperature. Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 4. Figure 4. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP Table 9. Package Dimensions

OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 14 Rev C 2/19/15 894D115I-01 DATA SHEET

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE 15 Rev C 2/19/15 894D115I-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B T6 7 AC Characteristics Table - corrected typo for Hold Time, STS-3 spec. from 300ps to 3000ps max. 6/24/08 C T5C 6 Differential DC Characteristics Table - deleted VPP and VCMR specs and added VIH, VIL, VIN specs. Parameter Measurement Information Section - updated Differential Input Level diagram. 10/15/08 Updated data sheet format 2/19/15

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