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2:1 LVDS Multiplexer With 1:2 Fanout and Internal Termination 889474 DATA SHEET 889474 REVISION A 11/11/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 889474 is a high speed 2-to-1 differential multiplexer with integrated 2 output LVDS fanout buffer and internal termination and is a member of the family of high performance clock solutions from IDT. The 889474 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and V REF_AC pins allow other differential signal families such as LVPECL, LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The 889474 is packaged in a small 4mm x 4mm 24-pin VFQFN package which makes it ideal for use in space-constrained applications.

FEATURES

  • Two differential LVDS outputs
  • INx, nINx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, CML
  • 50Ω internal input termination to V T
  • Maximum output frequency: 2GHz (maximum)
  • Additive phase jitter, RMS: 0.06ps (typical)
  • Output skew: 20ps (maximum)
  • Propagation delay: 700ps (maximum)
  • 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS-complaint package BLOCK DIAGRAM P IN ASSIGNMENT IN0 V nIN0 nQ0 nQ1 V REF_AC0 889474 24-Lead VFQFN 4mm x 4mm x 0.925mm package body K Package Top View 50Ω 50Ω 50Ω 50Ω MUX SEL GND GND nc SEL GND V DD VDD IN1 VT1 VREF_AC1 nIN1 VDD 7 8 9 10 11 12 24 23 22 21 20 19Q0 nQ0 VDD VDD nQ1 VDD nIN0 VREF_AC0 VT0 IN0 VDD IN1 V nIN1 V REF_AC1

889474 DATA SHEET

2 REVISION A 11/11/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. TRUTH TABLE Output Reference voltage for AC-coupled applications. 7, 8 Q0, nQ0 Output Differential output pair. LVDS interface levels. 11, 12 Q1, nQ1 Output Differential output pair. LVDS interface levels. 14, 17, 18 GND Power Power supply ground. 15 SEL Input Pullup Input select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD ABSOLUTE MAXIMUM RATINGS NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, I O (LVDS) Continuous Current 10mA Surge Current 15mA Input Current, INx, nINx ±50mA V T Current, I VT ±100mA Input Sink/Source, I REF_AC ± 0.5mA Operating Temperature Range, T A -40°C to +85°C Storage Temperature, T STG -65°C to 150°C Package Thermal Impedance, θ JA 49.5°C/W (0 mps) (Junction-to-Ambient) TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V DD TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 80 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 1.7 V DD + 0.3 V V IL Input Low Voltage 0 0.7 V I IH Input High Current V DD = V IN = 2.625V 5 µA I IL Input Low Current V DD = 2.625V, V IN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units R IN Input Resistance IN-to-V T IN-to-VT 45 50 55 Ω R DIFF_IN Differential Input Resistance INx, nINx 90 100 110 Ω V IH Input High Voltage INx, nINx 1.2 V DD V V IL Input Low Voltage INx, nINx 0 V IN – 0.1 V V IN Input Voltage Swing INx, nINx 0.1 V DD V V DIFF_IN Differential Input Voltage Swing INx, nINx 0.2 V V T_IN IN-to-V T INx, nINx 1.28 V V REF_AC Output Reference Voltage V DD – 1.4 V DD – 1.3 V DD – 1.2 V

4 REVISION A 11/11/15

TABLE 5. AC CHARACTERISTICS, V

4 Gpbs

NOTE: All parameters are characterized at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. at the differential cross points. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 5: Driving only one input clock.

5 2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION ADDITIVE PHASE JITTER Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.06ps typical The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements has issues relating to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. SSB PHASE NOISE dBc/HZ OFFSET FROM CARRIER FREQUENCY (HZ)

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

6 REVISION A 11/11/15

PARAMETER MEASUREMENT INFORMATION OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEWPART-TO-PART SKEW OUTPUT RISE/FALL TIME PROPAGATION DELAY

7 2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING OFFSET VOLTAGE SETUP DIFFERENTIAL OUTPUT VOLTAGE SETUP

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

8 REVISION A 11/11/15

APPLICATION INFORMATION

LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE The IN /nIN with built-in 50 Ω terminations accepts LVDS, LVPECL, CML and other differential signals. The signal must meet the V PP and V CMR input requirements. Figures 1A to 1E show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confi rm the driver termination requirements. FIGURE 1A. H IPERCLOCKS IN/nIN INPUT WITH B UILT-IN 50Ω DRIVEN BY AN LVDS DRIVER FIGURE 1B. H IPERCLOCKS IN/nIN INPUT WITH B UILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER IN nIN VT 2.5V LVDS 3.3V or 2.5V Zo = 50 Ohm Zo = 50 Ohm Receiver With Built-In

50 Ohm

Zo = 50 Ohm Receiver With Built-In Zo = 50 Ohm IN nIN VT 2.5V2.5V 2.5V LVPECL FIGURE 1E. H IPERCLOCKS IN/nIN INPUT WITH B UILT-IN 50Ω DRIVEN BY AN SSTL DRIVER FIGURE 1C. H IPERCLOCKS IN/nIN INPUT WITH B UILT-IN 50Ω DRIVEN BY A CML DRIVER FIGURE 1D. H IPERCLOCKS IN/nIN INPUT WITH B UILT-IN 50Ω DRIVEN BY A CML DRIVER WITH BUILT-IN 50Ω PULLUP Zo = 50 Ohm 2.5V Zo = 50 Ohm IN nIN VT Receiver With Built-In 2.5V CML - Open Collector IN nIN VT Receiver With Built-In 2.5V Zo = 50 Ohm Zo = 50 Ohm CML - Built-in 50 Ohm Pull-up 2.5V

protection, a 1kΩ resistor can be tied from IN to ground. FIGURE 2. TYPICAL LVDS DRIVER TERMINATION

100 Ohm Differential Transmission Line

driver, it is recommended to terminate the unused outputs. FIGURE 3. UNUSED INPUT HANDLING

10 REVISION A 11/11/15

FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) and the inner edges of pad pattern for the leads to avoid any shorts. achieved when an array of vias is incorporated in the land pattern. Enhance Leadfame Base Package, Amkor Technology.

TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN VFQFN, FORCED CONVECTION This section provides information on power dissipation and junction temperature for the 889474. Equations and example calculations are also provided. The total power dissipation for the 889474 is the sum of the core power plus the power dissipated in the load(s). = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V DD_MAX * I DD_MAX = 2.625V * 80mA = 210mW
  • Power Dissipation at built-in terminations: Assume the input is driven by a 2.5V SSTL driver as shown in Figure 1E and estimated approximately 1.75V drop across IN and nIN. Total Power Dissipation for the two 50Ω built-in terminations is: (1.75V) Input pair for both inputs is 2 * 30.6mW = 61.2mW Total Power _MAX (2.625V, with all outputs switching) = 210mW + 61.2mW = 271.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 49.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

12 REVISION A 11/11/15

TABLE 7. θ

TABLE 8. PACKAGE DIMENSIONS package dimensions are in Table 8 below.

14 REVISION A 11/11/15

TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

15 2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION REVISION HISTORY SHEET Rev Table Page Description of Change Date Updated data sheet format. 11/11/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.