8832I

DAC8832 TI | Alldatasheet

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DAC8832 ® /C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115

FEATURES

DESCRIPTION

APPLICATIONS

V OUT VO VDD R FBR INV VREF −FVREF −S Serial Interface and Control Logic CS DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converter 16-Bit Resolution The DAC8832 is a single, 16-bit, serial-input, voltage-output digital-to-analog converter (DAC) 2.7 V to 5.5 V Single-Supply Operation operating from a single V to V power supply. The Very Low Power: µ W for V Power DAC8832 provides excellent linearity LSB INL), High Accuracy, INL: LSB low glitch, low noise, and fast settling (1.0 µ S to Low Glitch: nV-s LSB of full-scale output) over the specified temperature range of C to +85 The output is Low Noise: 18n Hz unbuffered, which reduces the power consumption Fast Settling: 1.0 µ S and the error introduced by the buffer. Fast SPI Interface, up to MHz This device a standard high-speed (clock up Reset to Mid-Code to 50MHz), V or V SPI serial interface to Schmitt-Trigger Inputs for Direct Optocoupler communicate with the DSP or microprocessors. Interface The DAC8832 provides unipolar or bipolar output V REF when working with an external buffer, and is reset to mid-code after power-up. For optimum Portable Equipment performance, a set of Kelvin connections to the external reference and the analog ground input are Automatic Test Equipment provided. Industrial Process Control The DAC8832 is available in a QFN-14 package, Data Acquisition Systems and is pin-to-pin compatible with the DAC8831IRGY, Optical Networking which is reset to zero-code after power-up. Functional Block Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) MINIMUM POWER- RELATIVE DIFFERENTIAL ON SPECIFIED TRANSPORT ACCURACY NONLINEARITY RESET TEMPERATURE PACKAGE PACKAGE- PACKAGE ORDERING MEDIA, PRODUCT (LSB) (LSB) VALUE RANGE MARKING LEAD DESIGNATOR NUMBER QUANTITY DAC8832IRGYT Tape and Reel, 250 DAC8832IRGY Mid-Code C to +85 C 8832I QFN-14 RGY DAC8832IRGYR Tape and Reel, 1000 DAC8832IBRGYT Tape and Reel, 250 DAC8832IBRGY Mid-Code C to +85 C 8832I QFN-14 RGY DAC8832IBRGYR Tape and Reel, 1000 DAC8832ICRGYT Tape and Reel, 250 DAC8832ICRGY Mid-Code C to +85 C 8832I QFN-14 RGY DAC8832ICRGYR Tape and Reel, 1000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. over operating free-air temperature range (unless otherwise noted) (1) DAC8832 UNIT V DD to AGND 0.3 to V Digital input voltage to DGND 0.3 to DD 0.3 V V OUT to AGND 0.3 to DD 0.3 V AGND, AGNDF, AGNDS to DGND 0.3 to +0.3 V Operating temperature range to +85 C Storage temperature range to +150 C Junction temperature range J max) +150 C Power dissipation J max T A θ JA W Thermal impedance, θ JA 54.9 C/W (1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 All specifications at T A T MIN to T MAX V DD V or V DD +5V, V REF +2.5 V unless otherwise noted; specifications subject to change without notice. DAC8832 PARAMETER CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution bits DAC8832ICRGY 0.5 Linearity error DAC8832IBRGY 0.5 LSB DAC8832IRGY 0.5 Differential linearity error All grades 0.5 LSB T A +25 C Gain error LSB T A C to +85 C Gain drift 0.1 ppm/ C T A +25 C 0.25 Zero code error LSB T A C to +85 C Zero code drift 0.05 ppm/ C OUTPUT CHARACTERISTICS Unipolar operation REF V Voltage output (1) Bipolar operation V REF REF V Output impedance 6.25 k Ω Settling time To LSB of FS, C L pF µ s Slew rate (2) C L pF µ s Digital-to-analog glitch LSB change around major carry nV-s Digital feedthrough (3) 0.2 nV-s Output noise T A +25 C nV/ Hz Power-supply rejection V DD varies 10% LSB R FB R INV Ω Ω Bipolar resistor matching Ratio error 0.0015 0.0076 T A +25 C 0.25 Bipolar zero error LSB T A C to +85 C Bipolar zero drift 0.2 ppm/ C (1) See the Bipolar Output Operation section for details. (2) Slew Rate is measure from 10% to 90% of transition when the output changes from to full-scale. (3) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output does not change; CS is held high, while SCLK and DIN signals are toggled. Submit Documentation Feedback

www.ti.com DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A T MIN to T MAX V DD V or V DD +5V, V REF +2.5 V unless otherwise noted; specifications subject to change without notice. DAC8832 PARAMETER CONDITIONS MIN TYP MAX UNIT REFERENCE INPUT Reference input voltage range 1.25 V DD V Unipolar mode Reference input impedance (4) k Ω Bipolar mode 7.5 Reference dB bandwidth, BW Code FFFFh 1.3 MHz Reference feedthrough Code 0000h, V REF V PP at 100 kHz mV Signal-to-noise ratio, SNR dB Code 0000h Reference input capacitance pF Code FFFFh 120 DIGITAL INPUTS V DD 2.7 V 0.6 V IL Input low voltage V V DD V 0.8 V DD 2.7 V 2.1 V IH Input high voltage V V DD V 2.4 Input current µ A Input capacitance pF Hysteresis voltage 0.4 V POWER SUPPLY V DD Power-supply voltage 2.7 5.5 V V DD V I DD Power-supply current µ A V DD V V DD V Power µ W V DD V 100 TEMPERATURE RANGE Specified performance +85 C (4) Reference input resistance is code-dependent, minimum at 8555h. Submit Documentation Feedback

www.ti.com PIN CONFIGURATION (NOT TO SCALE) DAC8832 Thermal Pad(1) INV DGND LDAC SDI NC VOUT AGNDF AGNDS VREF −S VREF −F NOTE: (1) Exposed thermal pad must be connected to analog ground. 3 5 64 13 12 10 911 VDD RFB SCLK CS DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 RGY PACKAGE QFN-14 (TOP VIEW) TERMINAL FUNCTIONS TERMINAL NO. NAME RFB Feedback resistor. Connect to the output of external operational amplifier in bipolar mode. V OUT Analog output of DAC AGNDF Analog ground (Force) AGNDS Analog ground (Sense) V REF- S Voltage reference input (Sense). Connect to external voltage reference V REF- F Voltage reference input (Force). Connect to external voltage reference CS Chip select input (active low). Data is not clocked into SDI unless CS is low. SCLK Serial clock input. NC No internal connection SDI Serial data input. Data is latched into input register on the rising edge of SCLK. Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the LDAC content of the input register. DGND Digital ground Junction point of internal scaling resistors. Connect to external operational amplifier inverting input in bipolar INV mode. V DD Analog power supply, V to Submit Documentation Feedback

www.ti.com DAC Updated − − −Don’t□Care tDelay t Lead twsck ttd twsck tLag tDSCLK tsu tho CS SCLK SDI LOWLDAC DAC Updated− − −Don’t□Care t Delay t Lead twsck ttd twsck tLag tDSCLK tsu tho CS SCLK SDI HIGH LDAC Case1: LDAC tied□to□LOW Case2: LDAC Active tDLADC tWLDAC tsck tsck BIT 15□(MSB) BIT 14 BIT 13,□.□.□.□,1 BIT 0 BIT 15□(MSB) BIT 14 BIT 13,□.□.□.□,1 BIT 0 DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 Figure DAC8832 Timing Diagram Submit Documentation Feedback

www.ti.com TIMING CHARACTERISTICS: V DD V (1) (2) TIMING CHARACTERISTICS: V DD V (1) (2) DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 At C to +85 unless otherwise noted. PARAMETER MIN MAX UNIT t sck SCLK period ns t wsck SCLK high or low time ns t Delay Delay from SCLK high to CS low ns t Lead CS enable lead time ns t Lag CS enable lag time ns t DSCLK Delay from CS high to SCLK high ns t td CS high between active period ns t su Data setup time (input) ns t ho Data hold time (input) ns t WLDAC LDAC width ns t DLDAC Delay from CS high to LDAC low ns V DD high to CS low (power-up delay) µ s (1) Assured by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter. At C to +85 unless otherwise noted. PARAMETER MIN MAX UNIT t sck SCLK period ns t wsck SCLK high or low time ns t Delay Delay from SCLK high to CS low ns t Lead CS enable lead time ns t Lag CS enable lag time ns t DSCLK Delay from CS high to SCLK high ns t td CS high between active period ns t su Data setup time (input) ns t ho Data hold time (input) ns t WLDAC LDAC width ns t DLDAC Delay from CS high to LDAC low ns V DD high to CS low (power-up delay) µ s (1) Assured by design. Not production tested. (2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: V DD V 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 2.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 INL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 2.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) 81920 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 65536573444915240960327682457616384 Digital Input Code INL (LSB) TA = −40/C0095C VREF = 2.5 V 81920 65536573444915240960327682457616384 Digital Input Code TA = −40/C0095C VREF = 2.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +85/C0095C VREF = 2.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 INL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +85/C0095C VREF = 2.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 At T A +25 V REF +2.5 V unless otherwise noted. LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure Figure LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure Figure LINEARITY ERROR DIFFERENTIAL LINEARY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure Figure Submit Documentation Feedback

www.ti.com 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 INL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) 0.75 0.50 0.25 −0.25 −0.50 Linearity Error (LSB) Reference Voltage (V) 0 2 4 6 531 INL DNL 0.75 0.50 0.25 −0.25 −0.50 Linearity Error (LSB) Supply Voltage (V) VREF = 2.5 V DNL INL −60 −40 −20 0 20 40 60 80 140 120100 T emperature (/C0095C) VREF = 2.5 V Bipolar Mode Unipolar Mode 1.25 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 Gain Error (LSB) −60 −40 −20 0 20 40 60 80 140 120100 T emperature (/C0095C) VREF = 2.5 V Bipolar Mode Unipolar Mode 0.50 0.25 −0.25 −0.50 Zero−Code Error (LSB) DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 TYPICAL CHARACTERISTICS: V DD V (continued) At T A +25 V REF +2.5 V unless otherwise noted. LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure Figure LINEARITY ERROR LINEARITY ERROR vs REFERENCE VOLTAGE vs SUPPLY VOLTAGE Figure 10. Figure 11. GAIN ERROR ZERO-CODE ERROR vs TEMPERATURE vs TEMPERATURE Figure 12. Figure 13. Submit Documentation Feedback

www.ti.com 81920 300 250 200 150 100 65536573444915240960327682457616384 Digital Input Code Reference Current (µA) VREF = 2.5 V 81920 300 250 200 150 100 65536573444915240960327682457616384 Digital Input Code Reference Current (µA) VREF = 2.5 V 0 1 2 3 4 5 Digital Input Voltage (V) VDD = 5 V VDD = 3 V 800 700 600 500 400 300 200 100 Supply Current (µA) −60 −40 −20 0 20 40 60 80 140 120100 Temperature (/C0095C) VDD = 5 V VLOGIC = 5 V VDD = 3 V VLOGIC = 3 V VREF = 2.5 V Supply Current (µA) Supply Voltage (V) VREF = 2.5 V 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Supply Current (µA) Reference Voltage (V) VDD = 5 V VDD = 3 V 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Supply Current (µA) DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 TYPICAL CHARACTERISTICS: V DD V (continued) At T A +25 V REF +2.5 V unless otherwise noted. REFERENCE CURRENT REFERENCE CURRENT vs CODE (UNIPOLAR MODE) vs CODE (BIPOLAR MODE) Figure 14. Figure 15. SUPPLY CURRENT SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE vs TEMPERATURE Figure 16. Figure 17. SUPPLY CURRENT SUPPLY CURRENT vs SUPPLY VOLTAGE vs REFERENCE VOLTAGE Figure 18. Figure 19. Submit Documentation Feedback

www.ti.com 5V/div 0.1V/div Time (0.5µs/div) LDAC VREF = 2.5 V VOUT 5V/div 0.1V/div Time (0.5µs/div) LDAC VREF = 2.5 V VOUT Time (0.2µs/div) VREF = 2.5 V LDAC VOUT 5V/div 1V/div Time (0.2µs/div) VREF = 2.5 V LDAC VOUT 5V/div 1V/div Time (50ns/div) VREF = 2.5 V SDI VOUT 5V/div 20mV/div DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 TYPICAL CHARACTERISTICS: V DD V (continued) At T A +25 V REF +2.5 V unless otherwise noted. MAJOR-CARRY GLITCH MAJOR-CARRY GLITCH (FALLING) (RISING) Figure 20. Figure 21. DAC SETTLING TIME DAC SETTLING TIME (FALLING) (RISING) Figure 22. Figure 23. DIGITAL FEEDTHROUGH Figure 24. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: V DD V 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 1.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 INL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 1.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) 81920 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 65536573444915240960327682457616384 Digital Input Code INL (LSB) TA = −40/C0095C VREF = 1.5 V 81920 65536573444915240960327682457616384 Digital Input Code TA = −40/C0095C VREF = 1.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +85/C0095C VREF = 1.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 INL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +85/C0095C VREF = 1.5 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 At T A +25 V REF +2.5 V unless otherwise noted. LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure 25. Figure 26. LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure 27. Figure 28. LINEARITY ERROR DIFFERENTIAL LINEARY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure 29. Figure 30. Submit Documentation Feedback

www.ti.com 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 3 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 INL (LSB) 81920 65536573444915240960327682457616384 Digital Input Code TA = +25/C0095C VREF = 3 V 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 DNL (LSB) −60 −40 −20 0 20 40 60 80 140 120100 T emperature (/C0095C) VDD = 3 V VREF = 2.5 V Bipolar Mode Unipolar Mode 1.00 0.75 0.50 0.25 −0.25 −0.50 −0.75 −1.00 Gain Error (LSB) 0.75 0.50 0.25 −0.25 −0.50 Linearity Error (LSB) Reference Voltage (V) DNL INL −60 −40 −20 0 20 40 60 80 140 120100 T emperature (/C0095C) VDD = 3 V VREF = 2.5 V Bipolar Mode Unipolar Mode 0.50 0.25 −0.25 −0.50 −0.75 Zero−Code Error (LSB) 81920 300 250 200 150 100 65536573444915240960327682457616384 Digital Input Code Reference Current (µA) VREF = 1.5 V DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 TYPICAL CHARACTERISTICS: V DD V (continued) At T A +25 V REF +2.5 V unless otherwise noted. LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE Figure 31. Figure 32. LINEARITY ERROR GAIN ERROR vs REFERENCE VOLTAGE vs TEMPERATURE Figure 33. Figure 34. ZERO-CODE ERROR REFERENCE CURRENT vs TEMPERATURE vs CODE (UNIPOLAR MODE) Figure 35. Figure 36. Submit Documentation Feedback

www.ti.com Time (50ns/div) VREF = 2.5 V SDI VOUT 5V/div 20mV/div 81920 300 250 200 150 100 65536573444915240960327682457616384 Digital Input Code Reference Current (µA) VREF = 1.5 V 5V/div 0.1V/div Time (0.5µs/div) LDAC VREF = 2.5 V VOUT 5V/div 0.1V/div Time (0.5µs/div) LDAC VREF = 2.5 V VOUT Time (0.2µs/div) VREF = 2.5 V LDAC VOUT 5V/div 1V/div Time (0.2µs/div) VREF = 2.5 V LDAC VOUT 5V/div 1V/div DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 TYPICAL CHARACTERISTICS: V DD V (continued) At T A +25 V REF +2.5 V unless otherwise noted. REFERENCE CURRENT DIGITAL vs CODE (BIPOLAR MODE) FEEDTHROUGH Figure 37. Figure 38. MAJOR-CARRY GLITCH MAJOR-CARRY GLITCH (FALLING) (RISING) Figure 39. Figure 40. DAC SETTLING TIME DAC SETTLING TIME (FALLING) (RISING) Figure 41. Figure 42. Submit Documentation Feedback

www.ti.com THEORY OF OPERATION GENERAL 12−Bit R−2R Ladder Four MSBs Decoded into

15 Equal Segments

a single, 16-bit, serial-input, voltage-output DAC. It operates from a single supply ranging from 2.7 V to and typically consumes µ Data are written to this device in a 16-bit word format, via an SPI serial interface. To ensure a known power-up state, the DAC8832 is designed with a power-on reset function. The DAC8832 is reset to mid-scale code. In unipolar mode, the DAC8832 is reset to V REF and in bipolar mode, is reset to Kelvin sense connections for the reference and analog ground are also included. The DAC architecture consists of two matched DAC sections and is segmented. A simplified circuit diagram is shown in Figure The four MSBs of the 16-bit data word are decoded to drive switches, to E15. Each of these switches connects one of matched resistors to either AGND or V REF The remaining bits of the data word drive switches to S11 of a 12-bit voltage mode R-2R ladder network. Figure 43. DAC Architecture The output of the DAC is: V OUT REF Code)/65536 Where Code is the decimal data word loaded to the DAC latch. Submit Documentation Feedback

www.ti.com POWER-ON RESET SERIAL INTERFACE DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 THEORY OF OPERATION (continued) The DAC8832 has a power-on reset function to ensure the output is at a known state upon power-up. Upon power-up, the DAC latch and input register contain mid-scale code until new data is loaded from the input serial shift register. Therefore, after power-up, the output from pin V OUT is 0.5 V REF in unipolar mode, and in bipolar mode. However, the serial register is not cleared on power-up, so its

contents

undefined. When loading data initially to the device, bits or more should be loaded to prevent erroneous data appearing on the output. If more than bits are loaded, the last are kept; if less than are loaded, bits will remain from the previous word. If the device must be interfaced with data shorter than bits, the data should be padded with at the LSBs. The digital interface is standard 3-wire connection compatible with SPI, QSPI Microwire and TI DSP interfaces, which can operate at speeds up to 50M-bits/sec. The data transfer is framed by CS the chip select signal. The DAC works as a bus slave. The bus master generates the synchronize clock, SCLK, and initiates the transmission. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are ignored. The bus master accesses the DAC by driving pin CS low. Immediately following the high-to-low transition of CS the serial input data on pin SDI is shifted out from the bus master synchronously on the falling edge of SCLK, and latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high transition of CS transfers the register. All data registers are 16-bit. It takes clocks of SCLK to transfer one data word to the parts. To complete a whole data word, CS must go high immediately after SCLKs are clocked in. If more than SCLKs are applied during the low state of CS the last bits are transferred to the input register on the rising edge of CS However, if CS is not kept low during the entire SCLK cycles, data is corrupted. In this case, reload the DAC with a new 16-bit word. The DAC8832 has an LDAC pin allowing the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. In this case, LDAC must be maintained high while CS is low. If LDAC is tied permanently low, the DAC latch is updated immediately after the input register is loaded (caused by the low-to-high transition of CS Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION UNIPOLAR OUTPUT OPERATION 0.1µF VDD +5 V RFB INV AGNDF AGNDS DAC DAC Latch Input Register DAC8832 SDI SCLK LDAC VOUT R FBR INV VREF −S V REF −F Serial Interface and Control Logic CS +2.5 V 0.1µF 10 µF DGND VO = 0 to +VREF OPA277 OPA704 OPA727 V OUT_UNI /C0043D 216 /C0032/C0466V REF /C0041V GE /C0467/C0041V ZSE /C0041INL DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 The DAC8832 is capable of driving unbuffered loads of 60k Ω Unbuffered operation results in low supply current (typically µ and a low offset error. The DAC8832 can be configured to output both unipolar and bipolar voltages. Figure shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table Figure 44. Unipolar Output Mode Table Unipolar Code DAC LATCH V REF (65,535/65,536) 1000 0000 0000 0000 V REF (32,768/65,536) V REF 0000 0000 0000 0001 V REF (1/65,536) 0000 0000 0000 0000 Assuming a perfect reference, the worst-case output voltage may be calculated in the following equation: Unipolar Mode Worst-Case Output: Where: V OUT_UNI Unipolar mode worst-case output D Code loaded to DAC V REF Reference voltage applied to part V GE Gain error in volts V ZSE Zero scale error in volts INL Integral nonlinearity in volts Submit Documentation Feedback

www.ti.com BIPOLAR OUTPUT OPERATION 0.1µF VDD +5 V RFB INV AGNDF AGNDS DAC DAC LatchInput Register DAC8832 SDI SCLK LDAC VOUT R INV R FB VREF −S V REF −F Serial Interface and Control Logic CS +2.5 V 0.1µF 10 µF DGND VO = −VREF to +VREF OPA277 OPA704 OPA727 V OUT_BIP /C0043 /C0426/C0466V OUT_UNI /C0041V OS /C0467(2 /C0041RD )/C0042V REF (1 /C0041RD )/C0427 1 /C0041/C04662/C0041RD A /C0467 DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 With the aid of an external operational amplifier, the DAC8832 may be configured to provide a bipolar voltage output. A typical circuit of such an operation is shown in Figure The matched bipolar offset resistors R FB and R INV are connected to an external operational amplifier to achieve this bipolar output swing; typically, R FB R INV k Ω Figure 45. Bipolar Output Mode Table shows the transfer function for this output operating mode. The DAC8832 also provides a set of Kelvin connections to the analog ground and external reference inputs. Table Bipolar Code DAC LATCH (32,767/32,768) 1000 0000 0000 0001 REF (1/32,768) 1000 0000 0000 0000 0111 1111 1111 1111 V REF (1/32,768) 0000 0000 0000 0000 V REF (32,768/32,768) V REF Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation: Bipolar Mode Worst-Case Output: Where: V OS External operational amplifier input offset voltage RD R FB and R IN resistor matching error A Operational amplifier open-loop gain Submit Documentation Feedback

www.ti.com OUTPUT AMPLIFIER SELECTION REFERENCE AND GROUND POWER SUPPLY AND REFERENCE BYPASSING DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This provides the V REF output. In a single-supply application, selection of a suitable operational amplifier may be more difficult because the output swing of the amplifier does not usually include the negative rail; in this case, AGND. This output swing can result in some degradation of the specified performance unless the application does not use codes near The selected operational amplifier needs to have low-offset voltage (the DAC LSB is µ V with a 2.5 V reference), eliminating the need for output offset trims. Input bias current should also be low because the bias current multiplied by the DAC output impedance (approximately 6.25 k Ω adds to the zero-code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but in order to minimize gain errors the input impedance of the output amplifier should be as high as possible. The amplifier should also have a dB bandwidth of MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. Since the input impedance is code-dependent, the reference pin should be driven from a low impedance source. The DAC8832 operates with a voltage reference ranging from 1.25 V to V DD References below 1.25 V result in reduced accuracy. The DAC full-scale output voltage is determined by the reference. Table and Table outline the analog output voltage for particular digital codes. For optimum performance, Kelvin sense connections are provided. If the application does not require separate force and sense lines, they should be tied together close to the package to minimize voltage drops between the package leads and the internal die. For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a µ F tantalum capacitor in parallel with a 0.1 µ F ceramic capacitor. Submit Documentation Feedback

www.ti.com DAC8832 SBAS380A FEBRUARY 2006 REVISED APRIL 2006 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original Revision (February 2006) to A Revision Page Deleted Lead Temperature information from Absolute Maximum Ratings Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DAC8832IBRGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IBRGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IBRGYT ACTIVE QFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IBRGYTG4 ACTIVE QFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832ICRGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832ICRGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832ICRGYT ACTIVE QFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832ICRGYTG4 ACTIVE QFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IRGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IRGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IRGYT ACTIVE QFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC8832IRGYTG4 ACTIVE QFN RGY 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

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