87CH46N

TMP87C446N TOSHIBA | Alldatasheet

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Technical content

CMOS 8-Bit Microcontroller TMP87C446N, TMP87C846N, TMP87CH46N 87C446/846/H46 are high speed and high performance 8-bit single chip microcomputers. These MCU contain CPU core, ROM, RAM, input/output ports, an A/D converter, six multi-function timer/counters, a serial interface, a high speed serial output, and two clock generators on a chip. [PartNo Rom RAM Package TOTP version | TMP87C446N 4Kx8-bit TMP87CB46N 8KxB-bit 512x8-bit P-SDIP42-600-1.78 TMP87PH46N TMP87CH46N 16K xB-bit Features P-SDIP42-600-1.78 8-bit single chip microcomputer TLCS-870 Series @ instruction execution time: 0.5 us (at 8 MHz), 122 ys (at 32.768 kHz) $412 basic instructions © Multiplication and Division (8 bits x 8 bits , 16 bits + 8 bits) © Bit manipulations (Set/Clear/Complement/Move/Test/Exclusive or) i z i © 16-bit data operations SS © 1-byte jump/subroutine-call (Short relative jump / Vector call) TMP87C446N $14 interrupt sources (External: 6, Internal: 8) TMP87C846N TMP87CH46N ® Allsources have independent latches each, TMP87PH46N and nested interrupt control is available. © 4edge-selectable external interrupts with noise reject @ High-speed task switching by register bank changeover

5 Input/Output ports (35 pins)

@ High current output: 8pins (typ. 20 mA) 030619EBP1 Sire information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license i granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook" etc. @The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or. bodily injury ("Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. Fo products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. @For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. 87C446-1 2003-09-17

@Two 16-bit Timer/Counters @ Timer, Eventcounter, Programmable pulse generator output, Pulse width measurement, External trigger timer, Window modes @Two 8-bit Timer/Counters @ Timer, Event counter, Capture (Pulse width/duty measurement), PWM output, Programmable divider output modes @Time Base Timer (Interrupt frequency: — 1Hzto 16 kHz) @Divider output function (frequency: 1kHz to 8 kHz) @ Watchdog Timer 8-bit Serial Interface © With 8 bytes transmit/receive data buffer @ Internal/external serial clock, and 4/8-bit mode @8-bit High Speed Serial Output (rate: max. 1 bit/ xs) @8-bit successive approximate type A/D converter with sample and hold © 8 analog inputs ®@ Conversion time: 23 us /92 us at 8 MHz programmable selectable @Dual clock operation @Five Power saving operating modes © STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance. @ SLOW mode: Low power consumption operation using low-frequency clock (32.768 kHz). @ IDLE1 mode: CPU stops, and Peripherals operate using high-frequency clock. Release by interrupts. @ IDLE2 mode: CPU stops, and Peripherals operate using high and low frequency clock. Release by interrupts. @ SLEEP mode: CPU stops, and Peripherals operate using low-frequency clock. Release by interrupts. @ Emulation Pod: BM87CH47U0A 87C446-2 2003-09-17

Pin Assignments (Top View) P-SDIP42-600-1.78 (HSO) P77 <> 1 42H<— vop (HSCK) P76 <> 2 41> P22 (XTOUT) (so) P75 <> 3 40> p21 (xTIN) (si)p74 <> G4 391—<> P20 (INTS /STOP) Gem p73 <> 5 38<> pi7 (DOW) P72 <> O6 a7—<> pi6 (INT4) P71 <7 36> P15 (TC2) pos <> 10 33> P12 (INT2/TC1) pos <> 11 320 > P11 (INT1) Poa <> C12 31D<> pro GiTO) pos <> 013 30> P67 (AIN7) poz <> 14 291<—> P66 (AIN6) por <> 15 281 P65 (AINS) Poo <> 16 27> P64 (AINA) Test —> 17 26> P63 (AIN3) RESET <> 18 25H—€> P62 (AIN2) xin —>)19 2a0-<> P61 (Ai) xouT <—{ 20 230 P60 (AINO) (vass) vss — 421 22)\\—*— VAREF Block Diagram Power {we ‘Supply vss: Register Banks Reset RESET“[ >| system Controller Testpin TEST Program Memory standby contol (rom) eee tf f f Ff f = = Resonator { xn} high Timer Timer/Counters |]] Timer/Counters || _ Interfaces Connecting \\ xour- trea | clock Pins Low Generator Watchdog O i) O 0 O O Bot p22 ate P67 (AIN7) P07 Pi7 °77 to to to to +0 to P20 Analog P60 (AINO) POO P10 P70 WO port reference , Voltage _(anatoginputs) vo tons 87C446-3 2003-09-17

Two 8-bit programmable input/output P17, P16 vo ports (tri-state). eee) csunanafenmenPu...| Each bit of these ports can be [Timencounter ima P14 (PPG) individually configured as an input or an | programmable pulse generator output jossurnneneenenneeene] YO(Output) | output under software control. rovstnetstivenstsninninenstneintseestcernesel P13 (DVO) During reset, all bits are configured as | Divider output P12(INT2/TC1) inputs. 7 External interrupt input 2 or When used as a divider output or a PPG | Timer/Counter 1 input P11 (INT1) V/O (Input) output, the latch must be set to "1". External interrupt input 1 P10 (INTO) External interrupt input 0 P22 (XTOUT) V0 (Output) Resonator connecting pins (32.768kHz). pccsntsniatttteefsisusae] 3bitinputoutput port with latch. For inputting external clock, XTIN is used p20 (INTS/STOP) must be set to “1”. Externai interrupt input 5 or STOP mode release signal input ‘ann &-bit programmable input/output port P67 (AIN7) to (tri-state). Each bit of the port can be i P60 (AINO) VO (Output) | individually configured as an input or an_| 4/2 converter analog inputs output under software control P77 (HSO) . ; HSO serial data output tesssssrsssstseeneneesee 8-bit programable input/output port Jousnistiniitisionairiaeriiistinitisaeeeee P76 (HSCK) (tri-state). HSO serial clock output jesceenenennceneee] YQ (Output) Jnnstisiiutiinniusiuniniitieatieiaesee P75 (SO) SIO serial data output P74 (SI) SIO serial data input pronrmnnmnnnnnnnfeonennmnenes| When used aS an input port, a SIO. frnsrrrnnnmmnnnnnsstsnsnnnin P73 (SCK) VO(VO) | inputoutput, an external interrupt input | SIO serial clock input/output ae or a PWM/PDO output, the latch must be | 8-bit PWM output or P72 (PWM / PDO) YO Output) | otto “1”. 8-bit programmable divider output P71 (INT4) External interrupt input 4 sinnnneneeunneneed — YO (Input) oe ne sects External interrupt input 3 or P70 (INT3/TC3) Timer/Counter 3 input Resonator connecting pins for high-frequency clock IN, XOUT Input, Output onator x For inputting external clock, XIN is used and XOUT is opened. RESET Reset signal input or watchdog timer output/address-trap-reset output/system-clock- ra oa” a mer ou Preset ouput VDD, vss +5V, OV(GND) Power Supply - VAREF Analog reference voltage input 87C446-4 2003-09-17

1. CPU CORE FUNCTIONS The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a watchdog timer. This section provides a description of the CPU core, the program memory (ROM), the data memory (RAM), and the reset circuit. 1.1. Memory Address Map The TLCS-870 Series is capable of addressing 64K bytes of memory. Figure 1-1 shows the memory address. maps of the 87C446/846/H46. In the TLCS-870 Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the first 128 bytes of the RAM address space. SFR ( oar | S4bytes | ooa,| S4bytes | o5,,| 4 bytes oy” 0940 ogao Register banks 128 bytes i | 128bytes |: | 128bytes | } (registers x16 banks) o0BF ooBF OOBF ooco 09¢0 o9co RAM 384 bytes i 384 bytes i 384 bytes | note: i ! ROM; Read Only Memory includes : 023F 023F 023F | Program memory poi Poi: RAM; Random Access Memory includes : : Poi Poi: : Data memory + Pare 2k = Stack = rit esd > General-purpose register banks OF 80 oF80 OF80 SFR; Special Function Register includes i i WO ports DBR 128 bytes | 128bytes |; | 128bytes Peripheral control registers i i Peripheral status registers OFFF OFFF OFFF System control registers = Zs Zit = Interrupt control registers roi Tif ? Program Status Word “T | i poi | DBR; Data Buffer Register includes : yiesy | 27936 bytes | 23840 bytes ROM H H 192 bytes | 2 192bytes | > 192 bytes FEBF FEBF FFBE FFCO FFCO FFCO Vector table for vector call | «ty area for EEDE |. B2bytes | epg]. 32bytes | pepe |. 32 bytes | Deseineenrtinieh ooeeat FFEO FFEO Vector table for interrupts! rrr | 32bytes | peep | 32bytes | prep | 32bytes ) vonet (16 vector) instructions 87CH46 87846 870446 Figure 1-1. Memory Address Maps 87C446-5 2003-09-17

1.2 Program Memory (ROM)

The 87C446 has an 4K x8-bit (addresses FOOO}-FFFF}), the 87C846 has a 8K x8-bit (addresses E000y- FFFFy), and the 87CH46 has a 16K x 8-bit (address COO0}-FFFFH) of program memory (mask programmed ROM). Addresses FFOO}4-FFFFH in the program memory can also be used for special purposes. (1) Interrupt/ Reset vector table (addresses FFEO}4-FFFFH) This table consists of a reset vector and 15 interrupt vectors (2 bytes/vector). These vectors store a reset start address and interrupt service routine entry addresses. (2) Vector table for vector call instructions (addresses FFCO4-FFDFH) This table stores call vectors (subroutine entry address, 2 bytes/vector) for the vector call instructions [CALLV n]. There are 16 vectors. The CALLV instruction increases memory efficiency when utilized for frequently used subroutine calls (called from 3 or more locations). (3) Entry area (addresses FFOO-FFFF}) for page call instructions This is the subroutine entry address area for the page call instructions [CALLP n]. Addresses FFOO}- FFBFy are normally used because address FFCO},-FFFFy are used for the vector tables. Programs and fixed data are stored in the program memory. The instruction to be executed next is read from the address indicated by the current contents of the program counter (PC). There are relative jump and absolute jump instructions. The concepts of page or bank boundaries are not used in the program memory concerning any jump instruction. Address ROM Example: The relationship between the jd jump instructions and the PC. £000) (F883) ® 5-bit PC-relative jump [RS cc, $+2+d] : Example : Therelationship ents E8C4H: JRS T, $+2+08H Fro and Call group When JF = 1, the jump is made to E8CEy, ; instructions/InterrupU/ which is 08} added to the contents of the E Reset PC. (The PC contains the address of the Ene a instruction being executed +2; | FFIB Joos CALLP 7BH ; PC <-FF7By therefore, in this case, the PC contents FFBF are E8C4y +2 = E8C6y.) FFCO 56 CALLV OH ; PC<—CB856q FFC1 | callvector(H) | C8 ®@ 8-bit PC-relative jump UR cc, $+2+d] FFC2 E8C4H: JR Z, $+2+80H When ZF = 1, the jump is made to E846y, i which is FF80}q (- 128) added to the | FFOF current contents of the PC. FFEO 68 INTS + PC D368q FFE1 |interrupt vector (H)| D3 ® 16-bit absolute jump [JP al FFE2 E8C4H : JP 0C235H An unconditional jump is made to FFFD address C235y. The absolute jump | FFFE 3E RESET + PC CO3EH instruction can jump anywhere within | FFFF |_resetvector(H) | CO the entire 64K-bytes space. Figure 1-2. Program Memory Map In the TLCS-870 Series, the same instruction used to access the data memory (e.g. [LD A, (HL)] ) is also used to read out fixed data (ROM data) stored in the program memory. The register-offset PC-relative addressing (PC +A) instructions can also be used, and the code conversion, table look-up and n-way multiple jump processing can easily be programmed. 87C446-6 2003-09-17

Example 1 : Loads the ROM contents at the address specified by the HL register pair contents into the accumulator (87CH46 : HL= C000,): i) A, (HL) ; AE-ROM (HL) Example 2 : Converts BCD to 7-segment code (common anode LED). When A = 05x, 92H is output to port PO after executing the following program: ADD A, TABLE-$-4 } PO<-ROM (TABLE +A) LD (P0), (PC+A) gin, JRS T, SNEXT ‘fe TABLE: DB OCOH, OF9H, OAH, OBOH, 99H, 92H, 82H, OD8H, 80H, 98H ef (: SNEXT. Sav oh Notes: — “$” isa header address of ADD instruction. dq DBs a byte data difinition instruction. Example 3 : N-way multiple jump in accordance with the contents of accumulator (05 AS 3): SHLC A ; if A=004 then PCHC234, g Pp (PC+A) if A=01y then PCHC378y if A=02) then PC-DA37y if A=03, then PCE1B0y DA Dw 0C234H, 0C378H, ODA37H, OE1B0H 1.3. Program Counter (PC) The program counter (PC) is a 16-bit register which indicates the program memory address where the instruction to be executed next is stored. After reset, the user defined reset vector stored in the vector table (addresses FFFFy and FFFEy) is loaded into the PC ; therefore, program execution is possible from any desired address. For example, when COy and 3Ey are stored at addresses FFFFY and FFFEH, respectively, the execution starts from address CO3Ey after reset. The TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, the PC always indicates 2 addresses in advance. For example, while a 1-byte instruction stored at address C123} is being executed, the PC contains C125}. se \\sB 1514131211109 876543210 — PoComents KX att Xe? X_a+3 ) (a) Configuration {b)_ Timing chart of PC contents and Instruction Execution Figure 1-3. Program Counter 87C446-7 2003-09-17

1.4 Data Memory (RAM)

The 87C446/846/H46 have a 512K x 8-bit (address 0040}-023F}) of data memory (static RAM). Figure 1-5 shows the data memory map. Addresses 0000};-O0FF} are used as a direct addressing area to enhance instructions which utilize this addressing mode; therefore, addresses 0040};-00FF} in the data memory can also be used for user flags or user counters. General-purpose register banks (8 registers x 16 banks) are also assigned to the 128 bytes of addresses 0040}-O0BFH. Access as data memory is still possible even when being used for registers. For example, when the contents of the data memory at address 0040} is read out, the contents of the accumulator in the bank 0 are also read out. The stack can be located anywhere within the data memory except the register bank area. The stack depth is limited only by the free data memory size. For more details on the stack, see section “1.7 Stack and Stack Pointer”. With the TLCS-870 series, programs in data memory cannot be executed. If the program counter indicates a specific data memory address (addresses 0040H - 023FH), an address - trap - reset is generated due to bus error. (Output from the RESET pin goes low.) Example1 : If bit 2 at data memory address 00COy is “1”, 00H is written to data memory at address 00E3}; otherwise, FFy is written to the data memory at address 00E3y. TEST (00COH).2 i if (00C04) 2=0 then jump JRS T,SZERO cLR (00E3H) ; (00E3y) —00y JRS T,SNEXT SZERO: LD (O0E3H), OFFH j (00E3y) — FFy SNEXT : Example2 : Increments the contents of data memory at address OOF5y, and clears to 004 when 104 is exceeded. INC (O0FSH) ; (OOF5,) —(OOF5,) +1 AND (OOFSH), OFH 3 (OOF5y) — (00F5,) AOFy The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Note: The general-purpuse registers are mapped in the RAM ; therefore, do not clear RAM at the current bank addresses. Example: Clears RAM to “004” except the bank 0 LD HL, 0048H ; Sets start address to HL register pair Lo AH ; Sets initial data (00}) to A register Lo BC, O1F7H ; Sets number of byte to BC register pair SRAMCLR: LD (HL+), A DEC BC JRS F, SRAMCLR 87C446-8 2003-09-17

Address 0 1 2 3 4 5 6789 ABCODEF 0040,, RegisterbankO |. Registerbank1 oso” se narbone * fe i ebaa 0060 | Registerbanka | —-RegisterbankS woo" . “pager bans a _ oe ebonkd a ooao |. Registerbank 12. |.—-Registerbank 13. o0co poi Popo i poi sooo pope : a bed a poe coro aan 7 me sone en nk ee og [re ep eens on20 ao pepe 7 7 = a sdesedee ‘i ob Oe ee oe a popped Fa cesedese ow PE ais a ee ~ oe Figure 1-4. Data Memory Map 87C446-9 2003-09-17

1.5 General-purpose Register Banks

General-purpose registers are mapped into addresses 0040}-O00BFy in the data memory as shown in Figure 1-4. There are 16 register banks, and each bank contains eight 8-bit registers W, A, B, C, D, E, H, and L. Figure 1-5 shows the general-purpose register bank configuration. ll bank 15 (00B8 to 00BF};) bank 14 (00B0 to 00B7,) Samole : Jank o - bank 13 (00A8 to 00AF}) H wia bank 12 (00A0 to 00A7y) {Pode 00d essenseesebeseenrees bank 4 (0060 to 0067,,) DoE Dig bank 3 (0058 to 005F},) (0045y) ; (0044n) essesseesebeseensens bank 2 (0050 to 0057,,) He Hoiok bank 1 (0048 to 004F,,) (00471) : (0046) - bank 0 (0040 to 0047,,) (a) Configuration (b) Address assignments of registers Figure 1-5. General-purpose Register Banks In addition to access in 8-bit units, the registers can also be accessed in 16-bit units as the register pairs WA, BC, DE, and HL. Besides its function as a general-purpose register, the register also has the following functions: (1) A,WA The A register functions as an 8-bit accumulator and WA the register pair functions as a 16-bit accumulator (W is high byte and A is low byte). Registers other than A can also be used as accumulators for 8-bit operations. Examples: @® ADD A,B ; Adds B contents to A contents and stores the result into A. @ SUB WA, 1234H } Subtracts 1234) from WA contents and stores the result into WA. i SUB E,A ; Subtracts A contents from E contents, and stores the result into E. (2) HL, DE The HL and DE specify a memory address. The HL register pair functions as data pointer (HL) /index register (HL +d) /base register (HL + C), and the DE register pair function as a data pointer (DE). The HL also has an auto-post- increment and auto-pre-decrement functions. This function simplifies multiple digit data processing, software LIFO (last-in first-out) processing, etc. Example 1: ® LD A, (HU) ; Loads the memory contents at the address specified by HL into A. 2@ LD A, (HL+52H) ; Loads the memory contents at the address specified by the value obtained by adding 52), to HL contents into A. i) LD A, (HL+C) ; Loads the memory contents at the address specified by the value obtained by adding the register C contents to HL contents into A. ® LDA, (HL+) ; Loads the memory contents at the address specified by HL into A. Then increments HL. ) LD A, (-HL) ; Decrements HL. Then loads the memory contents at the address specified by new HL into A. The TLCS-870 Series can transfer data directly memory to memory, and operate directly between memory data and memory data. This facilitates the programming of block processing. 87C446-10 2003-09-17

Example 2: Block transfer LD B,m ; m=n-1(n: Number of bytes to transfer) Lo HL, DSTA } Sets destination address to HL LD DE, SRCA ; Sets source address to DE SLOOP: LD (HL), (DE) ; (HL) (DE) INC HL ; HLEHL+1 INC DE ; DE@DE+1 DEC B ; BeB-1 JRS F, SLOOP ; ifB20thenloop (3) B,C, BC Registers B and C can be used as 8-bit buffers or counters, and the BC register pair can be used as a 16-bit buffer or counter. The C register functions as an offset register for register-offset index addressing (refer to example 1 @ above) and as a divisor register for the division instruction [DIV gg, cj. Example 1 : Repeat processing Lo Bn ; Setsnas the number of repetitions to B SREPEAT: : Processing (n + 1 times processing) DEC B JRS F, SREPEAT Example 2 : Unsigned integer division (16-bit + 8-bit) DIV WA, C ; Divides the WA contents by the C contents, places the quotient in A and the remainder in W. The general-purpose register banks are selected by the 4-bit register bank selector (RBS). During reset, the RBS is initialized to “0”. The bank selected by the RBS is called the current bank. Together with the flag, the RBS is assigned to address 003Fy in the SFR as the program status word (PSW). There are 3 instructions [LD RBS, n], [PUSH PSW], [POP PSW] to access the PSW. The PSW can be also operated by the memory access instruction. Example 1 : Incrementing the RBS INC (003FH) ; RBS<-RBS +1 Example2 : Reading the RBS LD A, (003FH) } A@PSW (A3.9 — RBS, A7.aeFlags) Highly efficient programming and high-speed task switching are possible by using bank changeover to save registers during interrupt and to transfer parameters during subroutine processing. During interrupt, the PSW is automatically saved onto the stack. The bank used before the interrupt was accepted is restored automatically by executing an interrupt return instruction [RETI]/[RETN] ; therefore, there is no need for the RBS save/restore software processing. The TLCS-870 Series supports a maximum of 15 interrupt sources. One bank is assigned to the main program, and one bank can be assigned to each source. Also, to increase the efficiency of data memory usage, assign the same bank to interrupt sources which are not nested. Example: Saving /restoring registers during interrupt task using bank changeover. PINTI: LD RBS, n ; RBS —n (Bank changeover) RETI ; Maskable interrupt return (Bank restoring) 87C446-11 2003-09-17

1.6 Program Status Word (PSW)

The program status word (PSW) consists of a register bank selector (RBS) and four flags, and the PSW is assigned to address 003Fy in the SFR. The RBS can be read and written using the memory access instruction (e. g. [LD A, (003FH)], [LD (003FH), A], however the flags can only be read. When writing to the PSW, the change specified by the instruction is made without writing data to the flags. For example, when the instruction [LD (003FH), 05H] is executed, “5” is written to the RBS and the JF is set to “1”, but the other flags are not affected. [PUSH PSW] and [POP PSW] are the PSW access instructions.

1.6.1 Register Bank Selector (RBS)

The register bank selector (RBS) is a 4-bit register used to 76 5 4 3 2 1°90 select general-purpose register banks. For example, when RBS = 2, bank 2 is currently selected. During reset, the RBS — is initialized to “0”. Figure 1-6. PSW (Flags, RBS) Configuration

1.6.2 Flags

The flags are configured with the upper 4 bits : a zero flag, a carry flag, a half carry flag and a jump status flag. The flags are set or cleared under conditions specified by the instruction. These flags except the half carry flag are used as jump condition “cc” for conditional jump instructions [JR cc, $ +2 +d]/[JRS cc, $+2+d]. After reset, the jump status flag is initialized to “1”, other flags are not affected. (1) Zero flag (ZF) The ZF is set to “1” if the operation result or the transfer data is 004 (for 8-bit operations and data transfers)/0000} (for 16-bit operations); otherwise the ZF is cleared to “0”. During the bit manipulation instructions [SET, CLR, and CPL], the ZF is set to “1” if the contents of the specified bit is “0”; otherwise the ZF is cleared to “0”. This flag is set to “1” when the upper 8 bits of the product are 004 during the multiplication instruction [MUL], and when 00} for the remainder during the division instruction [DIV]; otherwise it is cleared to “0”. (2) Carry flag (CF) The CF is set to “1” when a carry out of the MSB (most significant bit) of the result occurred during addition or when a borrow into the MSB of the result occurred during subtraction; otherwise the CF is cleared to “0”. During division, this flag is set to “1” when the divisor is 00} (divided by zero error), or when the quotient is 1004 or higher (overflow error); otherwise it is cleared. The CF is also affected during the shift/rotate instructions [SHLC, SHRC, ROLC, and RORC]. The data shifted out from a register is set to the CF. This flag is also a 1-bit register (a boolean accumulator) for the bit manipulation instructions. Set/clear/complement are possible with the CF manipulation instructions. Example : Bit manipulation XOR CF, (009A). 0 LD (0001H) . 2, CF Example2 : Arithmetic right shift LD CF, A.7 ; AcAl2 RORC A (3) Half carry flag (HF) The HF is set to “1” when a carry occurred between bits 3 and 4 of the operation result during an 8- bit addition, or when a borrow occurred from bit 4 into bit 3 of the result during an 8-bit subtraction; otherwise the HF is cleared to “0”. This flag is useful in the decimal adjustment for BCD operations (adjustments using the [DAA r], or [DAS r] instructions). 87C446-12 2003-09-17

Example: BCD operation (The A becomes 47} after executing the following program when A = 19, B = 28) ADD AB ; A@4ty, HFT DAA A 7 A@4ly + 064 = 47, (decimal-adjust) (4) Jump status flag (JF) Zero or carry information is set to the JF after operation (e.g. INC, ADD, CMP, TEST). The JF provides the jump condition for conditional jump instructions [JRS T/F, $+2+d], [JR T/F, $+2+d] (T or Fis a condition code). Jump is performed if the JF is “1” for a true condition (T), or the JF is “0” for a false condition (F). The JF is set to “1” after executing the load/exchange/swap/nibble rotate/jump instruction, so that [URS T, $+2+d] and [JRT, $ + 2 +d] can be regarded as an unconditional jump instruction. Example : Jump status flag and conditional jump instruction INC A JRS T, SLABLE1 ; Jump when a carry is caused by the immediately 3 preceding operation instruction. LD A, (HL) JRS T, SLABLE2 ; JF is set to “1” by the immediately preceding instruction, making it an unconditional jump instruction. Example : The accumulator and flags become as shown below after executing the following instructions when the WA register pair, the HL register pair, the data memory at address 00C5y, the carry flag and the half carry flag contents being “219Ay", “00C5q", "D7", “1” and “0”, respectively. Instruction = = Instruction ADDC A, (HL) 72 1 : 0 pd 1 INC A 9B 0 0 1 0 sUBB A, (HL) 2 1ioitio ROLC A 35 1: 0:51:50 cMP A, (HL) 9A oof tio RORC A fo) 0:0 0:0 AND A, (HL) 92 oo: 1:0 ADD WA, OF508H 16A2 1i 0:1: 0 LD A, (HL) D7 1ioitio MUL W, A 13DA | 0:5 0:1:0 ADD A, 66H 00 riaiada SET AS. BA 1i 1:14:50 1.7. Stack and Stack Pointer

1.7.1 Stack

The stack provides the area in which the return address or status, etc. are saved before a jump is performed to the processing routine during the execution of a subroutine call instruction or the acceptance of an interrupt. On a subroutine call instruction [CALL a] / [CALLP n] / [CALLV n], the contents of the PC (the return address) is saved; on an interrupt acceptance, the contents of the PC and the PSW are saved (the PSW is pushed first, followed by PCy and PC,). Therefore, a subroutine call occupies two bytes on the stack; an interrupt occupies three bytes. When returning from the processing routine, executing a subroutine return instruction [RET] restores the contents to the PC from the stack; executing an interrupt return instruction [RETI] / [RETN] restores the contents to the PC and the PSW (the PC_ is popped first, followed by PCy and PSW). The stack can be located anywhere within the data memory space except the register bank area, therefore the stack depth is limited only by the free data memory size. 87C446-13 2003-09-17

1.7.2 Stack Pointer (SP)

The stack pointer (SP) is a 16-bit register containing the address of the next free locations on the stack. an wnwss76s4324 ia The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted; and Stack Pointer (SP) the SP is pre-incremented when a return or a pop instruction is executed. Figure 1-8 shows the stacking order. Figure 1-7. Stack Pointer The SP is not initialized hardware-wise but requires initialization by an initialize routine (sets the highest stack address). [LD SP, mn], [LD SP, gg] and [LD gg, SP] are the SP access instructions (mn ; 16-bit immediate data, gg ; register pair). Example 1 :To initialize the SP Lo SP, 023FH j SPe-023Fy Example 2 : To read the SP LD HL, SP ; HLe-sP At acceptance of interrupt At execution of or At execution of a CALLCALLV/CALLP at execution of At execution of a RETURETN instruction a SWI instruction a RET instruction instruction 023¢ osc] 023¢ osc] | 023D 023d} PC, 023D 0230] PC, 0236} PC. tush 0238} PC, ~<tEM? 23] PCL te, 023E] PCy —Ptp” Bash wu fa sects 023F . PCH 7 023F - Psw 023F . PCy 023F | PSW — 0040, stack depth se betore [oF] ¢ Y Y Y Y (023F) SPafter [0230 023¢ 023F 023F (a)_ Stacking order (b) Stack depth Figure 1-8. Stack

1.8 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a stand-by controller. Timing generator control register io generator 0036, BS P| High-frequency Timing o Tf: : Stand-by controller jk clock oscillator generator XOUT “To : ii Nae XTIN = i System clocks i i] oof: Low-frequency fs 0038, 00394 XTOUT ; A Clock generator control System control registers Figure 1-9. System Clock Controller 87C446-14 2003-09-17

1.8.1 Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the system clock controller to low-power operation based on the low-frequency clock. The high-frequency (fc) and low-frequency (fs) clocks can be easily obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins, respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to the XIN/XTIN pin with the XOUT/XTOUT pin not connected. The 87C446/846/H46 are not provided an RC oscillation. pommesanesa"""" High-frequency clock ““"""""= === === 3 remem =-===== Low-frequency clock “~""="= === === 7 i XOUT XIN xour {| xmTiN XTOUT XTIN xtour | Ooi Oo} H (open) i | (open) » 0 Pot ao | (a) crystaliceramic (b) Externaloscillator | (© Crystal (d) External oscillator i rl resonator fot | Figure 1-10. Examples of Resonator Connection Note: Accurate Adjustment of the Oscillation Frequency: Although no hardware to externally and directly monitor the basic clock pulse is not provided, the oscillation frequency can be adjusted by making the program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand. Example: To output the high-frequency oscillation frequency adjusting monitor pulse to P13 DVO) pin. SFCCHK: LD (P1CR), 000010008 |; Configures port P13 as an output SET (P1).3 ; P13 outputlatch —1 output waveform LD (TBTCR), 111000008 ; Enables divider output J IRS T,$ ; Loops endless <— #01024 ——!

1.8.2 Timing Generator

The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware. The timing generator provides the following functions : ® Generation of main system clock ® Generation of divider output (DVO) pulses ® Generation of source clocks for time base timer ® Generation of source clocks for watchdog timer ®© Generation of internal source clocks for timer/counters TC1 -TC5 © Generation of internal clocks for serial interfaces SIO and high speed serial output HSO @ Generation of warm-up clocks for releasing STOP mode ® Generation of a clock for releasing reset output (1) Configuration of Timing Generator The timing generator consists of a 21-stage divider with a divided-by-4 prescaler, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode and DV7CK (bit 4 in TBTCR) shown in Figure 1-11 as follows. 87C446-15 2003-09-17

tfc or 1/fs [s} H ‘ Main System Clock | | i i H H i state [so Pst sz ss so st sess i Hl 0.5ys at fc=8MHz ) 122s at_ f5=32.768kHz Figure 1-13. Machine Cycle

1.8.3 Stand-by Controller

The stand-by controller starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. There are two operating modes: single-clock and dual-clock. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1-14 shows the operating mode transition diagram and Figure 1-15 shows the system control registers. Either the single-clock or the dual-clock mode can be selected by an option during reset. (1) Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. In the single-clock mode, the machine cycle time is 4/fc [s] (0.5 us at fc=8 MHz). @® NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. In the case where the single-clock mode has been selected as an option, the 87C446/846/H46 are placed in this mode after reset. ® IDLE1 mode In this mode, the internal oscillation circuit remains active, and the CPU and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high- frequency clock). IDLE1 mode is started by setting IDLE bit in the system control register 2 (SYSCR2), and IDLE1 mode is released to NORMAL1 mode by an interrupt request from on- chip peripherals or external interrupt inputs. When IMF (interrupt master enable flag) is “1” (interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When IMF is “0” (interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction. @ STOP1 mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. The output status of all output ports can be set to either output hold or high-impedance under software control. STOP1 mode is started by setting STOP bit in the system control register 1 (SYSCR1), and STOP1 mode is released by an input (either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warming-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction. 87C446-17 2003-09-17

(2) Dual-clock mode Both high-frequency and low-frequency oscillation circuits are used in this mode. Pins P21 (XTIN) and P22 (XTOUT) cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] (0.5 us at fc = 8 MHz) in NORMAL2 and IDLE2 modes, and 4/fs [s] (122 ys at fs = 32.768 kHz) in SLOW and SLEEP modes. Note that the 87PH46/H47 is placed in the single-clock mode during reset. To use the dual-clock mode, the low- frequency oscillator should be turned on by executing [SET (SYSCR2).XTEN] instruction. @® NORMAL2 mode In this mode, the CPU core operates using the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. In case that the dual- clock mode has been selected by an option, the 87C446/846/H46 are placed in this mode after reset. @ SLOW mode This mode can be used to reduce power-consumption by turning off oscillation of the high- frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Switching back and forth between NORMAL2 and SLOW modes is performed by the system control register 2. @ IDLE2 mode In this mode, the internal oscillation circuits remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. @® SLEEP mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high- frequency clock are halted; however, on-chip peripherals remain active (operate using the low-frequency clock). Starting and releasing of SLEEP mode is the same as for IDLE1 mode, except that operation returns to SLOW mode. © STOP2 mode Asin STOP1 mode, all system operations are halted in this mode. 87C446-18 2003-09-17

IDLE1 <otwere— Normalt |—_ ‘STOPT mode mode mode interrupt ‘STOP pin input (a) Single-clock mode reset release software IDLEZ CF NORMAL mode mode oftware interrupt ms "ard STOP pin > | stor2 impute mode 7 ae SLEEP on stow | 4° -- mode mode 2777 software interrupt (b) Dual-clock mode Note: NORMAL1 and NORMAL2 modes are generically called NORMAL; STOP1 and STOP2 are called STOP; and IDLE1, IDLE2 and SLEEP are called IDLE. Operating mode CPU core mene pening cycle High-frequency | Low-frequency Peripherals time } turning on G | NORMAL1 4 te Aff 3 oscillation | turning off operate operate cls] = |ipves oscillation © 7 halt "a ‘turning off turning on iy | NORMAL2 oscillation High-frequency operate 4/fc [s] rd . High and/or Loy ; oscillation 3 [sow § quency [a] i Low-frequency 4/fs [s] SLEEP turning off oscillation hal turning off alt STOP2 oscillation halt Figure 1-14. Operating Mode Transition Diagram 87C446-19 2003-09-17

(ooss,) [stor Traum [rer ouren] wyr ] 2") nitiat value: 0000 00+» ) 0 : CPU core and peripherals remain active STOP | STOP mode start 1: CPU core and peripherals are halted (start STOP mode) reum | Release method 0: Edge-sensitive release for STOP mode 1: Level-sensitive release Operating mode 0: Return to NORMAL mode RETM | after STOP mode 1: Return to SLOW mode Rw ouren | Pertoutput control 0: High-impedance during STOP mode 1: Remain unchanged : 19 3 wut | Warming-up time at or. oe or NR " releasing STOP mode 1*. Reserved Note 1: Always set RETM to “0” when transiting from NORMAL1 mode to STOP1 mode and NORMAL2 mode to STOP2 mode. Always set RETM to “1” when transiting form SLOW mode to STOP2 mode. Note2: When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the RETM contents. Note3: fe ; high-frequency clock [Hz] fs; low-frequency clock [Hz] *; don't care Note4: Bits 1 and Qin SYSCR1 are read in as undefined data when a read instruction is executed. Note5: When the STOP mode is started by specifying OUTEN = “0”, the internal input of port is fixed to “0” and the interrupt of the folling edge may be set. System Control Register 2 P65 xen {High-frequency oscillator | 0 : Turn off oscillation control 1: Turn on oscillation xten |Low-frequency oscillator] 0 : Tum offoscillation control 1: Turn on oscillation M tem clock select rw jain system clock selec High sysck | (write)/main system clock : : High-frequency clock t : Low-frequency clock monitor (read) 0 : CPU and watchdog timer remain active Inte | IDLE tart Note 1: A reset is applied (RESET pin output goes low) if both XEN and XTEN are cleared to “0”. Note2: Do not clear XEN to “0” when SYSCK =0, and do not clear XTEN to "0” when SYSCK = 1. Note3: *;don'tcare Note4: Bits 3-0 in SYSCR2 are always read in as “1” when a read instruction is executed. Note5: An optional initial value can be selected for XTEN. Always specify when ordering ES (engineering sample). Note 6: The instruction for specifying Masking Option (Operating Mode) in ES Order Sheet is described in ADDITIONAL INFORMATION “Notice for Masking Option of TLCS-870 and TLCS-870/X series” section 8. XTEN_| operating mode after reset 0 | Single-clock mode (NORMAL1) 1 | Dual-clock mode (NORMAL2) Figure 1-15. System Control Registers 87C446-20 2003-09-17

1.8.4 Operating Mode Control

(1) STOP mode (STOP1, STOP2) STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP pin input. The STOP pin is also used both as a port P20 and an INTS (external interrupt input 5) pin. STOP mode is started by setting STOP (bit 7 in SYSCR1) to “1”. During STOP mode, the following status is maintained. @® Oscillations are turned off, and all internal operations are halted. @ The data memory, registers (except for DBR) and port output latches are all held in the status in effect before STOP mode was entered. The port output can be select either output hold or high-impedance by setting OUTEN ( bit 4 in SYSCR1). @ The divider of the timing generator is cleared to “0". @ The program counter holds the address of the instruction following the instruction which started the STOP mode. STOP mode includes a level-sensitive release mode and an edge-sensitive release mode, either of which can be selected with RELM (bit 6 in SYSCR1). a. Level-sensitive release mode (RELM = 1 In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. When the STOP pin input is high, executing an instruction which starts the STOP mode will not place in STOP mode but instead will immediately start the release sequence (warm-up). Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following method can be used for confirmation: @ Using an external interrupt input INT5 (INTS is a falling edge-sensitive input). Example: Starting STOP mode with an INT5 interrupt. PINTS: TEST —(P2).0 ; Toreject noise, the STOP mode does not start if JRS —F, SINTS port P20is at high LD (SYSCR1), 01000000B ; Sets up the level-sensitive release mode. SET (SYSCR1).7 ; Starts STOP mode LOW — (IL), 1110011101010111B —;_IL12, 11, 7, 5, 3-0 (clears interrupt latches) SINTS : RETI y STOP pin \\ fh iH \\ t xouT pin | CTT bperation ~_ operation oN Warmup —>H— Operation Confirm by program that the STOP mode is released by the hardware. STOP pin input is low and Always released if the STOP start STOP mode. pin input is high. Figure 1-16. Level-sensitive Release Mode switched until a rising edge of the STOP pin input is detected. 87C446-21 2003-09-17

b. Edge-sensitive release mode (RELM = 0) In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high. Example: Starting STOP mode operation in the edge-sensitive release mode LD (SYSCR1), 000000008; OUTEN€0 (specifies high-inpedance) DI ; IMF«-0 (disables interrupt service) SET — (SYSCR1).STOP ; STOP (activates stop mode) LOW (IL),1110011101010111B ; 1L12,11,7,5,3€-0 (clears interrupt latches) El i IMF«—1 (enables interrupt service) H Ly NORMAL j STOP i t H H stop operation operation mre Warm-up MSE mAL operation operation STOP mode started Ls / by the program STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 1-17. Edge-sensitive Release Mode STOP mode is released by the following sequence: ® When returning to NORMALZ2, both the high-frequency and low-frequency clock oscillators are turned on ; when returning to SLOW mode, only the low-frequency clock oscillator is turned on. When returning to NORMAL 1, only the high-frequency clock oscillator is turned on. @ Awarming-up period is inserted to allow oscillation time to stabilize. During warm-up, all internal operations remain halted. Two different warming-up times can be selected with WUT ( bits 2 and 3 in SYSCR1) as determined by the resonator characteristics. @ When the warming-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction (e.g. [SET (SYSCR1). 7]). The start is made after the divider of the timing generator is cleared to “0”. Table 1-1. Warming-up Time example 3x2"/fe [sl 375 [ms] 196.6 [ms] 3x2/ fs [s] 750. [ms] 21 fe 125 65.5 28/48 250 Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore, the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warming-up time must be considered an approximate value. STOP mode can also be released by setting the RESET pin low, which immediately performs the normal reset operation. In this case, even if the setting is to return to the SLOW mode, it starts from the NORMAL2 mode. (in case of 87PH46, starts from NORMAL1 mode) 87C446-22 2003-09-17

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Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower rate than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non- inverting high-level input voltage (hysteresis input). (2) IDLE mode (IDLE1, IDLE2, SLEEP) IDLE mode is controlled by the system control register 2 and maskable interrupts. The following status is 7 maintained during IDLE mode. @® Operation of the CPU and watchdog timer is byinstuction halted. On-chip peripherals continue to operate. @ The data memory, CPU registers and port output latches are all held in the status in 7 Yes effect before IDLE mode was entered. Reset @ The program counter holds the address of No (high) the instruction following the instruction which started IDLE mode. Ne Example: Starting IDLE mode. { Normal ) Yes SET (SYSCR2).4 5 IDLER release mode lo IDLE mode includes a normal release mode and an <a> interrupt release mode. Selection is made with the Yes (Interrupt release mode) interrupt master enable flag (IMF). Releasing the IDLE mode returns from IDLE1 to NORMAL1, from IDLE2 to NORMAL2, and from SLEEP to SLOW mode. Execution of the a. Normal release mode (IMF = “0") IDLE mode is released by any interrupt source ‘the IDLE mode start enabled by the individual interrupt enable flag instruction (EF) or an external interrupt 0 (INTO pin) request. Execution resumes with the instruction following 4 the IDLE mode start instruction (e.g. [SET Figure 1-19. IDLE Mode (SYSCR2).4]). The interrupt latch (IL) of the interrupt source for releasing the IDLE mode must be cleared to “0” by load instruction. b. Interrupt release mode (IMF = “1”) IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (EF) or an external interrupt 0 (INTO pin) request. After the interrupt is processed, the execution resumes from the instruction following the instruction which started IDLE mode. IDLE mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the 87C446/846/H46 are placed in NORMAL mode after reset release. Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is started, the watchdog timer interrupt will be processed but IDLE mode will not be started. 87C446-24 2003-09-17

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(3) SLOW mode SLOW mode is controlled by the system control register 2 and the timer/counter 2. a. Switching from NORMAL2 mode to SLOW mode First, set SYSCK (bit 5 in SYSCR2) to switch the main system clock to the low-frequency clock. Next, clear XEN (bit 7 in SYSCR2) to turn off high-frequency oscillation. When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. The timer/counter 2 (TC2) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. Note : The high frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high frequency clock when switching from SLOW mode to STOP mode. Example1 : Switching from NORMAL2 mode to SLOW mode. SET (SYSCR2) .5 ; SYSCKe1 (Switches the main system clock to the low-frequency clock) CLR (SYSCR2) .7 ; XEN@O (turns off high-frequency oscillation) Example2: Switching to SLOW mode after low-frequency clock oscillation has stabilized. fi) (TC2cR), 14H ; SetsTC2 mode (timer mode, source clock : fs) Low (TREG2), 8000H ; Sets warming-up time (according to Xtal characteristics) Lo (TC2CR), 34H j Starts TC2 PINTTC2: Lo (TC2CR), 10H ; Stops TC2 SET (SYSCR2). 5 ; SYSCKe1 CLR (SYSCR2).7 ; XENAO RETI VINTTC2: DW PINTTC2 ; INTTC2 vector table b. Switching from SLOW mode to NORMAL2 mode First, set XEN (bit 7 in SYSCR2) to turn on the high-frequency oscillation. When time for stabilization (warm-up) has been taken by the timer/counter 2 (TC2), clear SYSCK (bit 5 in SYSCR2) to switch the main system clock to the high-frequency clock. Note1: After the SYSCK is cleared to “0”, the CPU core operate using low frequency clock when the main system clock is switching from low frequency clock to high frequency clock. Note2: SLOW mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the 87C446/846/H46 are placed in NORMAL2 mode. (The PH46 is placed in NORMAL! mode) 87C446-26 2003-09-17

Example: Switching from SLOW mode to NORMAL2 mode (fc = 8 MHz, warming-up time is about 7.9 ms). SET (SYSCR2) .7 ; XENC1 (turns on high-frequency oscillation) fa) (TC2CR), 10H ; SetsTC2 mode (timer mode, source clock: fc) fa) (TREG2+1), OF8H — ; Sets the warming-up time {according to frequency and resonator characteristics) SET (EIR). EF14 ; Enable INTTC2 El LD (TC2CR), 30H } Starts TC2 PINTTC2: LD (TC2CR), 10H ; Stops TC2 CLR (SYSCR2).5 ; SYSCK0 (Switches the main system clock to the high-frequency clcok) RETI VINTTC2: = DW PINTTC2 ; INTTC2 vector table 87C446-27 2003-09-17

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1.9 Interrupt Controller

The 87C446/846/H46 each have a total of 14 interrupt sources: 6 externals and 8 internals. Nested interrupt control with priorities is also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. Each interrupt vector is independent. The interrupt latch is set to “1” when an interrupt request is generated and requests the CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled and disabled by the program using the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priority order as determined by the hardware. Figure 1-22 shows the interrupt controller. Table 1-2. Interrupt Sources . Interrupt |Vector Table| Interrupt Source Enable Condition Latch ‘Address | Priority Pay [nono C*dine | | an | rawr [wna Cinetawinrineripd [weet [ks | ws || rawr [wed eoireainwrn) [wrest [ms | wees | ec ee [ect [its oratory fase [as | re, | tow | 87C446-29 2003-09-17

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(1) Interrupt Latches (IL 15~2) Interrupt latches are provided for each source, except for a software interrupt. The latch is set to “1” when an interrupt request is generated, and requests the CPU to accept the interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt latches are initialized to “0” during reset. The interrupt latches are assigned to addresses 003Cy and 003Dy in the SFR. Each latch can be cleared to “0” individually by an instruction; however, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used (Do not clear IL2 for a watchdog timer interrupt to “O”). Thus, interrupt requests can be cancelled and initialized by the program. Note that interrupt latches cannot be set to “1” by any instruction. The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt requests by software is possible. Example 1 : Clears interrupt latches Low (IL), 1110100000111111B —; ILy2, ILyg~ILge-O Example 2 : Reads interrupt latches Lo WA, (IL) j Welly, ACT Example 3: Tests an interrupt latch TEST (1.7 ; if IL7=1 then jump JR F,SSET (2) Interrupt Enable Register (EIR) The interrupt enable registers (EIR) enable and disable the acceptance of interrupts except for the pseudo non-maskable interrupts (software and watchdog timer interrupts). Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR; however, the pseudo non-maskable interrupts cannot be nested more than once at the same time. For example, the watchdog timer interrupt is not accepted during the software interrupt service. The EIR consists of an interrupt master enable flag (IMF) and individual interrupt enable flags (EF). These registers are assigned to addresses 003Ay and 003By in the SFR, and can be read and written by an instruction (including read-modify-write instructions such as bit manipulation instructions). © Interrupt Master enable Flag (IMF) The interrupt master enable flag (IMF) enables and disables the acceptance of all interrupts, except for pseudo non-maskable interrupts. Clearing this flag to “0” disables the acceptance of all maskable interrupts. Setting to “1” enables the acceptance of interrupts. When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the acceptance of maskable interrupts. After execution of the interrupt service program, this flag is set to “1” by the maskable interrupt return instruction [RETI] to again enable the acceptance of interrupts. If an interrupt request has already been occurred, interrupt service starts immediately after execution of the [RETI] instruction. Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (IMF = 1). Note that IMF remains “0” when cleared in the interrupt service program. The IMF is assigned to bit 0 at address 003A in the SFR, and can be read and written by an instruction. IMF is normally set and cleared by the [EI] and [DI] instructions, and the IMF is initialized to “0” during reset. Note: Donotset IMF to “1”during non-maskable interrupt service programs. ® Individual interrupt Enable Flags (EF15 to EF4) These flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0” disables acceptance. 87C446-31 2003-09-17

Example 1 : Sets EF for individual interrupt enable, and sets IMF to “1”. Low (EIR), 1110100010100001B; EFis~EF13, EF11, EF7, EFs, IMFe-1 Example 2 : Sets an individual interrupt enable flag to “1”. SET (EIRH).4 3 EF 21 i 4 3 #2 #W 0 9 8 7 6 5S 4 3 2 1 0. " ee een TT, (003D a) TE, (003) eR — (initial Value ;... 09900000. 000000«) (0030 oe.) le FTN aeoee™myeOeeecvw EIR} (0038) EIR, (003An) (initial Value: 00000000 0000+#*0) Note? : Do not use any read-modify-write instruction such as bit manipulation for clearing IL. Note2 : Do not clear the IL2 by an instruction. Note? : Do not set IMF to “1”during non-maskable interrupt service programs. Figure 1-23. Interrupt Latch (IL) and Interrupt Enable Register (EIR)

1.9.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 machine cycles (4 us at f¢=8 MHz in NORMAL mode) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo non-maskable interrupts). (1) Interrupt acceptance processing @® The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. @ The interrupt latch (IL) for the interrupt source accepted is cleared to “0”. @ The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack. The stack pointer (SP) is three decrements. @ The entry address of the interrupt service program is read from the vector table address, and the entry address is loaded to the program counter. © The instruction stored at the entry address of the interrupt service program is executed. interrupt service task 1 machine cycle fe______terrupt service task gy ee Interrupt. | H H ! signal i i i H T i Hi . tt i ' H ime T X ! H 1 1 Note2 + ' i i i ro XEXE XE XS OF*XO XEON OFX) be a DS ED (SED, " Notel: a, return address, b ; entry address, c ; address when the RET! instruction is stored Note2: The maximum response time from when an IL is set until an interrupt acceptance processing starts is 38/fc or 38/fs [5]. Figure 1-24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program. 87C446-32 2003-09-17

Vector table address Entry address FFF24 | 034 —_) D203, | OF y FFF3y | D2y D204, | 06, A maskable interrupt is not accepted until the IMF is set to “1” even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the IMF is set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. However, an acceptance of external interrupt 0 cannot be disabled by the EF; therefore, if disablement is necessary, either the external interrupt function of the INTO pin must be disabled with INTOEN in the external interrupt control register (EINTCR) or interrupt processing must be avoided by the program. (When INTOEN =0, the interrupt latch IL3 is not set, therefore, the falling edge of the INTO pin input cannot be detected.) Example 1 : Disables an external interrupt 0 using INTOEN: ia) (EINTCR), 000000008 ; INTOEN<-0 Example 2 : Disables the processing of external interrupt 0 under the software control (using bit 0 at address OOFO} as the interrupt processing disable switch): PINTO: TEST (00FOH) .0 ; Returns without interrupt processing if (00FOy)o = 1 JRS T, SINTO Ai ree SINTO : z interrupt processing, RETI VINTO : ow PINTO (2) General-Purpose register save / restore processing During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers: ® General-purpose register save/restore by register bank changeove: General-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, bank 0 is used for the main task and banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. The switched bank is automatically restored by executing an interrupt return instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save the RBS. 87C446-33 2003-09-17

Example: Register Bank Changeover PINTxx : LD RBS) } Switches to bank n(1 sat MHz) ilnterrupt processing, ; RETI j_Restores bank and Returns main task interrupt main task . acceptance of tar i W \\' Switch to bank by \\V saving N LD RBS, n] or registers [INC (GRBS) } \\ instruction | | essen Restore bank 4 m interrupt return automatically by VW t [RETI]/[RETN] registers interrupt return (a)_Saving/Restoring by register bank changeover (b) Saving/Restoring using push/pop or data transfer instructions Figure 1-25. Saving/Restoring General-purpose Registers @® General-purpose register save/restore using push and pop instructions: To save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using push/pop instructions. Example: Register save using push and pop instructions PINTxx : PUSH WA ; Save WA register pair Interrupt processing : POP WA ; Restore WA register pair RETI ; Return eeseseenenseeeses eoseseeeeeeeseses esseceeeeeeeeesese sessisssesetsssee] Address (example) sp 023Ay A 0238 Pe ooo bee psec Oe cP ane ee ene. ee eosnesenen| O23D PCy PCy PCy 023E ooh POM POM SPY cca O25F At acceptance Atexecution At execution At execution of an ofaninterrupt TY ofapush > ofapop >) interrupt return instruction instruction instruction @ General-purpose registers save/restore using data transfer instruction: Data transfer instructions can be used to save only a specific general-purpose register during processing of a single interrupt. Example: Saving/restoring a register using data transfer instructions PINTxx : LD ccs (GSAVA), A ; Save Aregister ‘interrupt processing , LD A, (GSAVA) ; Restore A register RETI ; Return 87C446-34 2003-09-17

The interrupt return instructions [RETI] / [RETN] perform the following operations. [RETI] Maskable interrupt return [RETN] Non-maskable interrupt return @® The contents of the program counter and the | @® The contents of the program counter and program status word program status word are restored from the stack. are restored from the stack. @ The stack pointer is incremented 3 times. @ The stack pointer is incremented 3 times. @ The interrupt master enable flag is set to “1”. @ The interrupt master enable flag is set to “1” only when a non- maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at “0” when so clear by an interrupt service program. Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note :When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task.

1.9.2 External Interrupts

The 87C446/846/H46 each have six external interrupt inputs (INTO, INT1, INT2, INT3, INT4, and INTS). Four of these are equipped with digital noise rejection circuits (pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1, INT2, INT3 and INT4. The INTO/P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise rejection control and INTO/P10 pin function selection are performed by the external interrupt control register (EINTCR). When INTOEN =0, the IL3 will not be set even if the falling edge of INTO pin input is detected. Table 1-3. External Interrupts [soe [mm [ESE | eatiention [eter | oataomnna | Pulses less than 15/fc [s] or 63/fc [s] are cancelled as noise. Pulses equal INT INTT to or more than 48/fc [s] or 192/fc [s] fallingedge | are regarded as signals. or as noise. Pulses equal to or more than 24/fc [s] are regarded as Teo tea Peles tins Tcl 87C446-35 2003-09-17

Note1: — The noise rejection function is turned off in the SLOW and SLEEP modes. Also, the noise reject times are not constant for pulses input while transiting between operating modes (NORMAL2@SLOW) Note2: — The noise rejection function is also affected for timer/counter input (TC1 and TC3 pins). INote3: The pulse width (both "H” and "L” level) for input to the INTO and INT5 pins must be over 1 machine cycle. INTO/INTS input ‘tint, tintH > teyc : : P Note: teyc = 4/fc (at NORMAL 1/2 and IDLE 1/2 i a modes) 4/fs (at SLOW and SLEEP modes) Note4: — Ifa noiseless signal is input to the external interrupt pin in the NORMAL 1/2 or IDLE 1/2 mode, the maximum time from the edge of input signal until the IL is set is as follows : ® INT1 pin 49/fc [s] (INTINC=1), 193/fc [s] (INTINC=0) @ INT2,INT3, INT4 pins 25/fe [s] Note5: | When high-impedance is specified for port output in stop mode, port input is forcibly fixed to low level internally. Thus, interrupt latches of external interrupt inputs except INTS (P20/STOP) which are also used as ports may be set to 1”. To specify high-impedance for port output in stop mode, first disable interrupt service (IMF =0), activate stop mode. After releasing stop mode, clear interrupt latches using load instruction, then, enable interrupt service. Example : Activating stop mode LD (SYSCR1) 010000008 ; OUTEN€-0 (specifies high-impedance) DI ; IMF<-0 (disables interrupt service) SET (SYSCR1).STOP ; STOP<+ (activates stop mode) LOW (IL),1110011101010111B —; 1L12,11,7,5,3€-0 (clears interrupt latches) El ; IMF<-1 (enables interrupt service) inter 2 © 5 4 3 2 71 0 (00371) (Initial value: 00*0 000) etl 0 : Pulses of less than 63/fc [s] are eliminated as noise ANTS pi ; 0 : P10 input/output port ww INT4 ES INT3 ES 0: Rising edge INT1 ES Note1: fc ; High-frequency clock [Hz] * ; don’t care Note2: — Edge detection during switching edge selection is invalid. Note3: Do not change EINTCR when IMF = 1. After changing EINTCR, interrupt latches of external interrupt inputs must be cleared to “0” using load instruction. Note4: — Inorder to change of external interrupt input by rewriting the contents of INT2ES, INT3ES and INTAES during NORMAL 1/2 mode, clear interrupt latches of external interrupt inputs (INT2, INT3 and INTA) after 8 machine cycles from the time of rewriting. During SLOW mode, 3 machine cycles are required. Note5: — Inorder to change an edge of timer counter input by rewriting the contents of INT2ES, INT3ES and INTAES during NORMAL1/2 mode, rewrite the contents after timer counter is stopped (TC*s = 0), that is, interrupt disable state. Then, clear interrupt latches of external interrupt inputs (INT2, INT3 and INT4) after 8 machine cycles from the time of rewriting to change to interrupt enable state. Finally, start timer counter. During SLOW mode, 3 machine cycles are required. Example: When changing TC1 pin inputs edge in external trigger timer mode from rising edge to falling edge. (example: TMP87CHOON) LD (TC1CR),01001000B ; TC1S 00 (stops TC1) DI ; IMF <0 (disables interrupt service) LD (EINTCR),00000100B ;_ INT2ES <1 (changes edge selection) t NOP 8machine =~ cycles = NOP i LD (ILL),011111118 j 1L7€0(clears interrupt latch) El ; IMF <1 (enables interrupt service) LD (TC1CR),01111000B j; TC1S€-11 (starts TC1) Note6: If changing the contents of INT1ES during NORMAL1/2 mode, interrupt latch of external interrupt input INT1 must be cleared after 14 machine cycles (when INTINC = 1) or 50 machine cycles (when INTINC =0) from the time of changing. During SLOW mode, 3 machine cycles are required. Figure 1-26. External Interrupt Control Register 87C446-36 2003-09-17

1.9.3 Software Interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable interrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the [NOP] instruction. Thus, the [SWI] instruction behaves like the [NOP] instruction. Note: Software interrupt generates during non-maskable interrupt processing to use SWI instruction for software break in a development tool. Use the [SWI] instruction only for detection of the address error or for debugging. @® Address Error Detection FFy is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address. Code FF is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFy to unused areas of the program memory. Address-trap- reset is generated for instruction fetch from a part of RAM area (addresses 0040}-023Fy) or SFR area (0000}4-003F}). Note: The fetch data from addresses, BF80}, to BFFF} for 87C446/846/H46 is not “FFy”. @® Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 87C446-37 2003-09-17

1.10 Watchdog Timer (WDT)

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset output or a non- maskable interrupt request. However, selection is possible only once after reset. At first the reset output is selected. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.

1.10.1 Watchdog Timer Configuration

MPX reset release signal from T.G. f¢/2” or f5/2'° ——>|A Binary Counters fc/ 2" or f5/2? ——>|B clock overflow reset fc/2" or f5/2""——>|C_ Y D WDT output output 2 (\\ [oS interrupt request INTWDT internal reset —e enable Q S_R fe writing writing clear wotout worT H disable code |code woe] P was] Watchdog Timer Control Registers Figure 1-27. Watchdog Timer Configuration

1.10.2 Watchdog Timer Control

Figure 1-28 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows. ® Setting the detection time, selecting output, and clearing the binary counter. @ Repeatedly clearing the binary counter within the setting detection time. If the CPU malfunction occurs for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTOUT =1 a reset is generated, which drives the RESET pin low to reset the internal hardware and the external circuits. When WDTOUT =0, a watchdog timer interrupt (INTWDT) is generated. The watchdog timer temporarily stops counting in the STOP mode including warm-up or IDLE mode, and automatically restarts (continues counting) when the STOP/IDLE mode is released. 87C446-38 2003-09-17

Example: Sets the watchdog timer detection time to 221/fc [s] and resets the CPU malfunction. fn) (WDTCR1), 000011018; WDTT<10, WDTOUT1 ia) (WOTCR2), 4EH ; Clears the binary counters Within 3/4 of WOT i (always clear immediately after changing WDTT) detection time i Lo (WOTCR2), 4EH ; Clears the binary counters Within 3/4 of WOT : detection time i LD (WDTCR2), 4EH ; Clears the binary counters Watchdog Timer Control Register 1 7.6 5 4 3 2 1 0 woTert OA, iti (0034,) : (Initial value: **** 1001) woten | Watchdog timer 0 : Disable (itis necessary to write the disable code to WDTCR2) enable/disable 1: Enable 00:2%/fc or 27/fs — [s] Watchdog timer 01: 2%/fe or 2" / fs. write WDTT | detection time 10:2"/fe or 2° /fs only 11:2") fe or 2" /fs worour | Watchdog timer 0: Interrupt request. output select 1: Reset output Note 1 : | WDTOUT cannot be set to ”1” by program after clearing WDTOUT to "0". Note2: fc ; High-frequency clock [Hz] fs ; Low-frequency clock [Hz] * ; don’t care Note3 : WDTCRT isa write-only register and must not be used with any of read-modify-write instructions. Note4 : Disable the watchdog timer or clear the counter just before switching to STOP mode. When the counter is cleared just before switching to STOP mode, clear the counter again subsequently to releasing STOP mode. Watchdog Timer Control Register 2 worer2 7 6 5S 4 3 #2 #1 O (00354) (inital value: s¥s+ +3+4) . 4E, —: Watchdog timer binary counter clear (clear code) it Watchdog timer control : imer Bi u write WDTCR2 | code write register B1y — : Watchdog timer disable (disable code) only others : Invalid Note1 : The disable code is invalid unless written when WDTEN =0. Note2: *,;don'tcare Note3 : Since WDTCR2 is a write-only register, read-modify-write instructions (e.g. ; bit manipulating instructions such as SET or CLR and arithmetic instructions such as AND or OR) cannot be used for read/write to this register. Note4 : Toclearbinary counter doesn’ initialize the source clock, therefore, it is recommended to clear binary counter within 3/4 of the detection period. Figure 1-28. Watchdog Timer Control Registers Table 1-4. Watchdog Timer Detection Time NORMAL1 NORMAL2 sLOW Atfc=8MHz | At fs=32.768 kHz 271 fc 2 fc, 2/5 2° fs 1.048 s 1s 21 fc 2 /fc, 2° / fs —_— 262.1 ms 250 ms 2"°/ fe 2'°/ fc, 2" fs — 65.5 ms 62.5ms 87C446-39 2003-09-17

(2) Watchdog Timer Enable The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1) to “1”. WDTEN is initialized to "1" during reset, so the watchdog timer operates immediately after reset is released. Example : Enables watchdog timer Lo (woTcRr1), 000010008 ; WDTEN1 (3) Watchdog Timer Disable The watchdog timer is disabled by writing the disable code (B1}) to WDTCR2 after clearing WDTEN (bit 3 in WDTCR1) to “0”. The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTEN is cleared to “0”. The watchdog timer is halted temporarily in STOP mode (including warm-up) and IDLE mode, and restarts automatically after STOP or IDLE mode is released. During disabling the watchdog timer, the binary counters are cleared to “0”. Example : Disables watchdog timer Low (WOTCR1), 0B101H ; WDTEN€-0, WOTCR2<disable code

1.10.3 Watchdog Timer Interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the EIR. Ifa watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDTOUT. Example : Watchdog timer interrupt setting up. LD SP, 023Fy ; Sets the stack pointer in) (WDTCR1) , 000010008 ; WDTOUT€-0

1.10.4 Watchdog Timer Reset

If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin (sink open drain output) low to reset the internal hardware and the external circuits. The reset output time is 220/fc [s] (131 ms at fc =8 MHz). The high-frequency clock oscillator also turns on when a watchdog timer reset is generated in SLOW mode. Note: The high-frequency clock oscillator also turns on when a watchdog timer reset is generated in SLOW mode. Thus, the reset output time is 2?°/fc. The reset output time include a certain amount of error if there is any function of the oscillation frequency when the high-frequency clock oscillator turns on. Thus, the reset, output time must be considered approximate value. . 2'/fc [s] 2ife H <2 es Clock l l (wort = 118) Binary counter 1X2 X3X_9 XX 2X Xo Overflow i INTWOT interrupt : WOT reset output nn a rn | 2 (“L" output) writes 4, to WDTCR2 Figure 1-29. Watchdog Timer Interrupt / Reset 87C446-40 2003-09-17

1.11 Reset Circuit

The 87C446/846/H46 each have four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 1-5 shows on-chip hardware initialization by reset action. The internal source reset circuit (watchdog timer reset, address trap reset, and system clock reset) is not initialized when power is turned on. Thus, output from the RESET pin may go low (220/fc [s.] (131 ms at 8 MHz) when power is turned on. Table 1-5. Initializing Internal Status by Reset Action Register bank selector (RBS) t) circuitry Interrupt individual enable flags (EF) t) fl Refer to each of Interrupt latches crs) C) Control registers control register

1.11.1 External Reset Input

When the RESET pin is held at low for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the a operating voltage range and oscillation stable, a reset is veo i vob applied and the internal state is initialized. ' typ. 220k2. When the RESET pin input goes high, the reset operation is RESET released and the program execution starts at the vector * ! address stored at addresses FFFE} - FFFFy. ~ L The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor. A simple power-on-reset can be Figure 1-30. Simple Power-on- applied by connecting an external capacitor and a diode. Reset Circuitry

1.11.2 Address-Trap-Reset

An address-trap-reset is one of fail-safe function that detects CPU malfunction caused by noise or the like, and returns the CPU to the normal state. If the CPU attempts to fetch an instruction from addresses 0000} to 023Fy (a part of RAM or SFRs), an internal reset (called address-trap-reset) will be generated. Then, the RESET pin output will go low. The reset time is 220/fc [s] (131 ms at 8 MHz). reset Execution KP a) {reset release _Ynstructon ataddresr | I) Address-trap is occurred ey es ee RESET output (“L" output) (Hi-Z)! t i H Hi t es Sa S| i Pe [3] ie 1 Met to Note1: 05a=023Fy Note2: During reset release, reset vector “r” is read out, and an instruction at address r is fetched and decoded. Figure 1-31. Address-Trap-Reset 87C446-41 2003-09-17

1.11.3 Watchdog Timer Reset

Refer to Section “1.10 Watchdog Timer”.

1.11.4 System-Clock-Reset

Clearing both XEN and XTEN (bits 7 and 6 in SYSCR2) to “0” stops both high-frequency and low- frequency oscillation, and causes the MCU to deadlock. This can be prevented by automatically generating a reset signal whenever XEN = XTEN =0 is detected to continue the oscillation. Then, the RESET pin output goes low from high-impedance. The reset time is 220/fc [s] (131 ms at 8 MHz). 87C446-42 2003-09-17

1. ON-CHIP PERIPHERALS FUNCTIONS

2.1 Special Function Registers (SFR) and Data Buffer Registers (DBR)

The TLCS-870 Series uses the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function registers (SFR) and data buffer registers (DBR). The SFR are mapped to addresses 0000} to 003Fy, and the DBR to addresses OF80} to OFFFy. Figure 2-1 shows the 87C446/846/H46 SFRs and DBRs. Address Read Write ‘Address Read Write 00 cece eeenennnneee PO POM ccccceesmnuntssssesanene] — 0020H/SiOSR(S10 status) [SIOCRT ne i OD Jorccsssssneessnsseeennssseenns ee POM cc sssneessnsnneeesnnnsneessny 22 Yarcsccsssssneesnssnsseernnsenesst@SOIMVCD, sc ccsusssneeemnsnnneesnssaneees O38 Yaeececcsesssssseeseeeeeeeereen nf OSOMOO cssnsnssnseeeeesen , DB Yo ccsvvsseseserserseseseceeeecnnnen nf OSONED,.cccccceceeennnssnnesnnneeeeee

04 Yn cesssssseeseeceeeneneee of OSEMED eso sossnanee 24 |HSOsR(HSO status) HsocR (iso control) |

06 PG Port 26 reserved

OF Yeeeeesecccccencnennentnee en PORE ccceeeeceenecnnanenanen DT | ccesssssssesnseesseseseceeePIGRZ (PT UO COMIN. ccesessnsessanssseeeeee 08 reserved 28 reserved 09 Pann cssneennsnsseenesssnen ss SOMEG os socsssnsangenssnneneeesnn 29 Yo ccsseessssneeenannneeernnsened @SOMED,. ccscessnsnneetinsnneeennseee 0A = |POCR (Po 1/0 control). 2A reserved OB foscccsessseeesnsnseesmeseseeesnsnseeefPEGRIPLMO contol) PB Ya ccsssessssneseessseeersnsered @SOMED,sooseessnsnenetnnnneenennneee OC Yaneececcsesssssee TeeceeeerereesanseneefPOGR (PE MO COMO) ae CY ceccsesseseseserseseseseeerseenes fOSONOG, ccecccceccseenesessessaneneesesed OD Jarccsssssseeernnn eecressaeee ansee ee RN PT MO Come os 2D Joavesccsssssseesnssnseeernnseeesef@SOIVCD,.sccssssssneeennssnneenmasseeees QE Yan secssenssnnenee ADCCRIAD converter OMe seen DE Yo occcccsseeeteeteneeneseceeereeenenfOSONOD, ec cccsennnnnnnesnnnenseeesee OF [ADCOR (A/D conv. result) = 2F reserved 10 foo cccceeeeecceaTeeessessnteseeesneeef REGTAL register BO Poccccceecccceneeesessnteeeeee A OSOIMOO oe ccccceeeeseceneeeseeeeeee 1 = frrecia,, Timer reatster 14) 31 reserved 12 Yaa ccccssseeeeeeeeneen TREGIBL. timer register 18) <-+sseseeeesssssssee BQ Ye cceccccesennnnenennnnnnnseeeeeE@SOIMED. i ccccceeeeeececesnanananenn

13 TRESia,, Timer roaster 18) 33 reserved

V4 Yas ccccsseeeeenen Tenssssssnsnesneeeseef GIER (TCL comtrol BA acco ccscceeeeenee snssnssnvenneneeeeed WOTERI,, ntr TB Yoon casesseeseesvensenseunetnsevef SLR TCR control a 35 fa... Toessserseeneess Ire reo) V6 Yc ccesstmnnTiersnrmnernsen nef REZ. Crimer register BE Yc ccseseeeneene BTR... (TBT/TS/DVO COMtTON)sccseren 17 fs Finega"” Cimerreaieer Vg [oe EINTeR (External nteruptcontal) VB faa ccscsseseseeeersee, PREG3A Timer register 3A) sossnanee 38 sosananesasn4vS¥SERT sotsesseseneonsnananess 19. | FREGIB imerregieter 39) YT gg fn gysena Coster contra 1A = HrC3CR (73 control) 3A EIR, bo : 1c reserved 3C i, 1E = [TCSCR (TCS control). 3E reserved 1F reserved 3F [PSW (Program status word) RBS (Register bank selector) (a) Special Function Registers Address Read Write es cn Note1 : Do not access reserved areas by the — nh ee program. orb — Note2: - : Cannot be accessed. fa vse Note3 : When defining address 003Fy with os ae orrerenennne assembler symbols, use GPSW and GRBS. 13 sio encom Note4 : Write-only registers and interrupt fa [UT transmit and receive orenenennns latches cannot use the read-modify- fs data buffer enn write instructions (bit manipulation a ae soscerneensennee instructions such as SET, CLR, etc. and a anenarnsaen logical operation instructions such as orre [___- [Ho wensmitdatabutfer | AND, OR, etc.) F9 reserved a FA ccensesntnneeserner ef SSQINOG.. cassenetenetnettneeneene FB reserved a FD reserved a FF reserved (b) Data Buffer Registers igure 2-1. R & DBR 87C446-43 2003-09-17

2.2. V/O Ports The 87C446/846/H46 have 5 parallel input/output ports (35pins) each as follows: | —~_| Primary Function Secondary Functions Port P1 8-bit I/O port external interrupt input, timer/counter input/output, and divider output “PortP2 | 3-biti/O port "| low-frequency resonator connections, external interrupt input, Port P6 8-bit I/O port analog input “PortP7 | 8-bit/Oport _| serial interface, external interrupt, and timer/counter input/output _ Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should either be held externally until read or reading should be performed several times before processing. Figure 2-2 shows input/output timing examples. External data is read from an |/O port in the $1 state of the read cycle during execution of the read instruction. This timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. Output data output changes in the $2 state of the write cycle during execution of the instruction which writes to an I/O port. fetchcycle fetchcycle read cycle fetchcycle fetchcycle write cycle Instruction ___SO 0 0 --- Instruction---30 0 0 = cycle-~ “o> cycle-~ -- pid pulse (a) Input Timing (b) Output Timing Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 2-2. Input/Output Timing (Example) When reading an I/O port except programmable I/O ports, whether the pin input data or the output latch contents are read depends on the instructions, as shown below: (1) Instructions that read the output latch contents @ XCH r, (sre) ® LD (pp) . b, CF ® CLRISET/CPL (src).b © ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), 1n @ CLRISET/CPL (pp).g ® (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) @ww (src).b, CF (2) Instructions that read the pin input data ® Instructions other than the above (1) ® (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) 87C446-44 2003-09-17

2.2.1 Port PO (P07 - POO)

Port PO is an 8-bit general-purpose input/output port which can be configured as either an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port PO input/output control register (POCR). Port PO is configured as an input if its corresponding POCR bit is cleared to “0”, and as an output if its corresponding POCR bit is set to “1”. During reset, POCR is initialized to “0”, which configures port PO as input. The PO output latches are also initialized to “0”. Data is written into the output latch regardless of the POCR contents. Therefore initial output data should be written into the output latch before setting POCR. Note 1: Ports set to the input mode read the pin states. When input pin and output in exist in port PO together, the contents of the output latch of parts set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2: The POCR is a write-only register. It can not be operated by the read-modify instruction (Bit manipulation instruction of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.) STOP o ouren —d_) data output 4 <} output latch Note 1: i=7to0 Note 2: STOP is bit7 of SYSCR1. OUTEN is bit4 of SYSCR1. 7 6 5 4 3 2 1 +O 7.6 5 4 3 2 1 ~O pocr | YOcontrol for port PO 0: input mode write (Set for each bit individually) | _1: output mode only Figure 2-3. Port PO and POCR Example: Setting the upper 4 bits of port PO as an input port and the lower 4 bits as an output port (Initial output data are 1010p). Lo (PO), 000010108 ; Sets initial data to PO output latches LD (POCR),00001111B ; Sets the port PO input/output mode 87C446-45 2003-09-17

2.2.2 Port P1 (P17 - P10)

Port P1 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P1 input/output control register (P1CR). Port P1 is configured as an input if its corresponding P1CR bit is cleared to “0”, and as an output if its corresponding P1CR bit is set to “1”. During reset, the P1CR is initialized to “0”, which configures port P1 as an input. The P1 output latches are also initialized to “0”. Data is written into the output latch regardless of P1CR contents. Therfore initial output data should be written into the output latch before setting P1CR. Port P1 is also used as an external interrupt input, a timer/counter input, and a divider output. When used as secondary function pin, the input pins should be set to the input mode, and the output pins should be set to the output mode and beforehand the output latch should be set to “1”. It is recommended that pins P11 and P12 should be used as external interrupt inputs, timer/counter input, or input ports. The interrupt latch is set at the rising or falling edge of the output when used as output ports. Pin P10 (INTO) can be configured as either an I/O port or an external interrupt input with INTOEN (bit 6 in EINTCR). During reset, pin P10 (INTO) is configured as an input port P10. Note 1: Ports set to the input mode read the pin states. When input pin and output in exist in port P1 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2: The PICR is a write-only register. It can not be operated by the read-modify instruction (Bit manipulation instruction of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.) sToP 3D OUTEN —d e PACRi > | data input nH <Q data output [>a] ali Cy ii output latch control output control input Note : i=7to0 Z — T 4 + > 2 z 1 — P1 P17: P16: P15 : Pid: P13: P12: P11 : P10 (0001,,) H Prez | ppg | vo | 'N? !inr1 INTO | (Initial value: 0000 0000) 6 4 0 picr | YOcontrol for port P1 0: Input mode write (Set for each bit individually) | _ 1: Output mode only Figure 2-4. Port P1 and P1CR Example : Sets P17, P16 and P14 as output ports, P13 and P11 as input ports, and the others as function pins. Internal output data is “1” for the P17 and P14 pins, and “0” for the P16 pin. Lo (EINTCR), 010000008; INTOENe~1 in) (P1), 101111118 PI71, P14—1, P16H0 fn) (P1CR), 110100008 87C446-46 2003-09-17

2.2.3 Port P2 (P22 - P20)

Port P2 is a 3-bit input/output port. It is also used as an external interrupt | _S€T/CLR/CPL others CMP/MCMP/TEST/ others input, and low-frequency crystal |>2#inPut [J <}+~<] connection pins When used as an opens input port, or a secondary function | pata output fo | > [_] P20 (ints STOP) pin, the output latch should be set to | Control input Ke "1". During reset , the output latches | Data input - <KI are initialized to “1". at] | | Ose. enable A low-frequency crystal (32.768 kHz) D ita output P21 (XTIN) is connected to pins P21 (XTIN) and ata outpe [o_o] pane [] U P22 (XTOUT) in the dual-clock mode. | pata input <kK] J In the single-clock mode, pins P21 and << TL -/ 0 P22 can be used as normal 9 input/output ports. Data output [> 9] > is LJ P22 tour It is recommended that pin P20 { ) should be used as an external] crop [> interrupt input, a STOP mode release | OUTEN o Note 1: * ;don’tare signal input, or an input port. If used | XTEN Note 2: SENS bits of as an output port, the interrupt latch <] ° is set on the falling edge of the fs a output pulse. When a read instruction is executed en rr a 1 0 for port P2, bits 7 to 3 read in as “1”. p2 H H i P22: P21 :_P20. (00024) : i i i xtour! xTIN | Stop (initial value: #*** *111) Figure 2-5. Port P2

2.2.4 Port P6 (P67 to P60)

Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P6 input/output control register (P6CR). Port P6 is also used as an analog input for the A/D converter. When used as an analog input, AINDS (bit 4 in the ADCCR) must be cleared to “0” and its corressponding P6CR bit must be set to “0”. In this case, unuse pin as analog input is configured as only input port. During reset, AINDS is initialized to “0” and all bits of P6CR are initialized to “0”, which configures port P6 as analog input. The P6 output latches are initialized to “0”. Data is written into the output latch regardless of the P6CR contents. Therefore initial output data should be written into the output latch before setting P6CR. 87C446-47 2003-09-17

Analog input —D STOP AINDS —o g san 1 { ) [_) PGCRI o Data input C.J <| H | | Data output fea] [> {| P6i Note :i=7to0 Ps 7 6 5 4 3 2 1 0 P67 : P66 : P65 ; P64 : P63 : P62: P61 : PEO oe PécR 7 6 5S 4 3 2 1 +0 VO control for port P6 0 : Inputmode write P6CR | (set for each bit individually) | 1 : Output mode only Note1 : P6CRis a write-only register and must not be used with any of the read-modify-write instruction. Note2 : Unused analog input pins cannot be configured as output mode when AINDS = 0. Figure 2-6. Port P6

2.2.5 Port P7 (P77 to P70)

Port P7 is an 8-bit general-purpose input/output port which can be configured as either input or output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P7 input/output control register (P7CR1/P7CR2). For example, port P7 is configured as an input if its corresponding P7CR bit is cleared to “0”, and as an output if its corresponding bit is set to “1”. During reset, P7CR is initialized to “0”, which configures port P7 as input. The output latches are initialized to “0”. Data is written into the output latch regardless of the P7CR contents. Therefore initial output latch before setting P7CR. Note: P7CR is a write-only register and must not be used with any of the read-modify-write instructions. 87C446-48 2003-09-17

re = ae PT7CRIi Data input = <] Data output. oe: TT] 7 P7 7 6 5 4 3 2 1 0 (00074) | P77 :_P76 : P75 : P74 : P73 : P72: P71 : P70 HSO :HSCK: SO : SI: SCK : PDO : INT4 : INT3 , H :PWM: TC3 (initial value 0000 0000) P7CR1 7 6 5 4 3 2 1 0 p7cri_ | YO control for P7 0: Input mode write (Set for each bit individually) | 1: Output mode only prr2 7 6 5 4 3 2 #1 O VO control for P7 0: Sink open drain Figure 2-7. Port 7 and P7CR

2.3 Time Base Timer (TBT)

The time-base timer is used to generate the base time for key scan and dynamic display processing. For this purpose, it generates a time-base timer interrupt (INTTBT) at predetermined intervals. This interrupt is generated beginning with the first rising edge of the source clock (the timing generator’s divider output selected by TBTCK) after the time-base timer is enabled. Note that since the divider cannot be cleared by a program, the first interrupt only may occur earlier than the set interrupt period. (See Figure 2-8. (b).) When selecting the interrupt frequency, make sure the time-base timer is disabled. (Do not change the selected interrupt frequency when disabling the active timer either.) However, you can select the interrupt frequency simultaneously when enabling the timer. 87C446-49 2003-09-17

2.4 Divider Output (DVO)

A 50% duty pulse can be output using the divider output circuit, which is useful for piezo-electric buzzer drive. Divider output is from pin P13 (DVO). The P13 output latch should be set to “1” and then the P13 should be configured as an output mode. Divider output circuit is controlled by the control register (TBTCR) shown in Figure 2-11. 7 6 5 4 3 2 1 ~O oon (initial value: 0%#0 Owes) . . 0: Disable 00 : fc/2'? or fs/25[Hz] RW Divider output (DVO) 01: fc/2'2 or fs/24 Dvock frequency selection 10 : fc/2" or fs/23 11: fc/2"? or f5/2? Note: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], * ; don’t care Figure 2-10. Divider Output Control Register Example: 1kHz pulse output (at fc = 8 MHz) SET (P1).3 ; P13 output latch 1 LD (P1cR), 000010008 ; Configures P13 as an output mode LD (TBTCR), 100000008 } DVOEN€1, DVOCKe-00 Table 2-2. Frequency of Divider Output voce] ummm, [acon seve Divider Output 00 fe/2" or f3/2° 0.976[kHz]} 1.024 [kHz] 01 fel2” 5/2" 1.953 2.048 10 fel2" 3/2? 3.906 4.096 1 fel2 3/2? 7.812 8.192 output latch output enable data outpur—>[>_ 0] [4 >> 3 ovo) MPxX A fe/2'3 or fs/25 >] a (.) fc/2'2 or fs/24 >8 fc/211 or fs/23 c Y P13 output latch J fe/210 or fs/22 >-[0_s 1 Cc 2 i = Dvock DVOEN PVOEN I ae L Divider output control register (a) Configuration b) Timing Chart Figure 2-11. Divider Output 87C446-51 2003-09-17

2.5 16-bit Timer/Counter 1 (TC1)

2.5.1 Configuration

: i gy | | u 4] i viele ei 3 é¢ 3 aei>?T] Lo He & z — $f : Hl Le 5 zg | > i : ae : r > * ° AN 2 iG co i al am 3] | |< . 5 easel ae 2 3) a V | 8 nk 87C446-52 2003-09-17

2.5.2 Control

The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer registers (TREG1A and TREG1B). Reset does not affect TREG1A and TREG1B. TREGIA 11413 121 1099 BO ULL (0010, 00114) TREG1A;, (00114) TREG 1A, (00104) Write only TREGIB (0012, 0013,) TREG 1B) (00134) JREG1B, (0012}4) Read / Write (Write available in only 77 6 25 4 #3 #2 1 0 PPG output mode ) TCICR mca (initial value : 0000 0000) (0014,) Tret |MCAPIT Tes TCICK TCIM initial value + MPPG1 00: timer/ external trigger timer / event counter mode tcim_ {TC 01: window mode mode select, 10: pulse width measurement mode 11: PPG output mode 00: internal clock 2" or fs/2? [Hz] qeick |TC! 01: internal clock fo/2” source clock select 10: internal clock fo/2? 11: external clock (TC1 pin input) 00: stop & counter clear ters. TC 01: command start Write start control 10: reserved only 11: external trigger start SCAP1 0: - 1: software capture trigger (Note 3) capi | Pulse width measurement 1: double edge capture 1: single edge capture control external trigger timer tri tri METTI | Control 0 : trigger start 1: trigger start & stop PPG output control 0: continuous pulse _1: single pulse TeF1__ | timer F/F1 control for PPG 0: clear 1: set output mode Note 1: fc; High-frequency clock [Hz], fs ; Low-frequency clock [Hz] Note2: Writing to the low-byte of the timer registers (TREG1A,, TREG1B,), the comparison is inhibited until the high-byte (TREG1Ay, TREG1B,,) is written. After writing to the high-byte, the comparison of 1 cycle (during instruction execution) is ignored. Note3: Set the mode, source clock, edge (INT2ES), PPG control and timer F/F control when TC1 stops (TC15 =00). Note 4: Software capture can be used in only timer and event counter modes. Note5: Values to be loaded to timer registers must satisfy the following condition. TREG1A>TREG1B>0 (PPG output mode) ; TREG1A>0 (others) Note 6: Always write "0” to TFF1 except the PPG output mode. Note 7: TCICR isa write-only register, which cannot be accessed by any read-modify-write instruction such as bit operate, etc. Note 8: TREG1B cannot be written after setting to PPG output mode. Figure 2-13. Timer Registers and TC1 Control Register 87C446-53 2003-09-17

2.5.3 Function

Timer/counter 1 has six operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output mode. (1) Timer Mode In this mode, counting up is performed using the internal clock. The contents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to”0”. Counting up resumes after the counteriscleared. The current contents of up-counter can be transfered to TREG1B by setting SCAP1 (bit 6 in TC1CR) to “1” (software capture function). SCAP1 is automatically cleared to “0” after capaturing. Table 2-3. Timer/Counter 1 Source Clock (Internal Clock) fe/2 [Hz] fe/2 [Hz] - 1 ys - 65.5 ms fc/2" fc/2" - 16 ps - 1.0 s Example 1 : Sets the timer mode with source clock fs/23[Hz] and generates an interrupt 1s. later (at fs = 32.768 kHz). LD (Tc1¢R), 000000008 j Sets the TC1 mode and source clock LDW (TREG1A), 1000H ; Sets the timer register (1s +23/fs= 1000,,) SET (EIRL). EF4 ; Enables INTTC1 interrupt El LD (TC1CR), 000100008 ; Starts TC1 Note: The TCICR is write-only register and can not be started by [SET (TC1CR). 4] instruction. Example 2 : Software capture LD (TC1CR), 010100008 ; SCAP1<+1 (Captures) LD WA, (TREG1B) ; Reads captured value Command start Source clock J { J J Up-counter ° Xi X2X2X 4) KKK KKK KEXEXAK | TREGIA a H Match Counter INTTC1 interrupt i detect clear (a) Timer Source clock | “1 rd T 1 1 1 al r1 capture capture SCAP 1 (b) Software Capture Figure 2-14. Timer Mode Timing Chart 87C446-54 2003-09-17

(2) External Trigger Timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the rising or falling edge can be selected with INT2ES. Edge selection is the same as for the external interrupt input INT2 pin. Source clock is used an internal clock selected with TC1CK. The contents of TREG1A is compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to”0” and halted. The counter is restarted by the selected edge of the TC1 pin input. The TC1 pin input has the same noise rejection as the INT2 pin; therefore, pulses of 7/fc [s] or less are rejected as noise. A pulse width of 24/fc [s] or more is required for edge detection in NORMAL1/2 or IDLE1/2 mode. The noise rejection circuit is turned off in SLOW and SLEEP modes. But, a pulse width of 4/fs [s] or more is required. Example 1: Detects rising edge (in TC1 pin input) and generates an interrupt 100 ys later. (at fc = 8 MHz) Lo (EINTCR), 000000008 j INT2ES€-0 (rising edge) Low (TREG1A), 0064H j 100 ys + 2%/fc=64y SeT (EIRL.) EF4 ; Enables INTTC1 El Lo (TC1CR), 001110008 ; Starts TC1 with an external trigger, METT = 0 Example 2: Generates an interrupt, inputting “L” level pulse (pulse width : 4 [ms] or more) to the TC1 pin. (at fc = 8 MHz) Lo (EINTCR), 000001008 ; INT2ES€-1 (“L" Level) Low (TREG1A), OOFAH 3 Ams = 2/fc=FAy SET (EIRL). EFA ; Enables INTTC1 El LD (TC1cR), 011101008 ; Starts TC1 with an external trigger, METT = 1 count start count restart TC1 pininput f trigger K trigger (INT2ES = 0) Internal clock J J i J J Up-counter o X1X2X2X mo XX 9 XX 2X 3X4 TREGIA | inter match clear (a) Trigger Start (METT = 0) count count count start clear start TC1 pin input [rrcser Y trigger K trigger Yeising edge select i i 1 (INT2ES = 0) Internal clock l ' I ' l ' I l t ' t Up-counter 7 OOOMEE— OPEG00G TREGIA eT INTTC1 match_| [clear (b) Trigger Start &Stop(MeTT1=1) Note: msn Figure 2-15. External Trigger Timer Mode Timing Chart 87C446-55 2003-09-17

(5) Pulse width measurement mode Counting is started by the external trigger (set to external trigger start by TC1S). The trigger can be selected either the rising or falling edge of the TC1 pin input. The source clock is used an internal clock. On the next falling (rising) edge, the counter contents are transferred to TREG1B and an INTTC1 interrupt is generated. The counter is cleared when the single edge capture mode is set. When double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred to TREG1B. If a falling (rising) edge capture value is required, it is necessary to read out TREG1B contents until a rising (falling) edge is detected. Falling or rising edge is selected with INT2ES, and single edge or double edge is selected with MCAP1 (bit 6 in TC1CR). count count start start TC1 pin input Kriaser Y K Internal clock Nn ane l IE upcouner ID © ©) C00 0 | CD € € i capture TREGIB n INTTCA I [Applications] High or low pulse width measurement (a) Single Edge Capture count count start start TC1 pin input K Y K meric = FL FE PLLA J U1 Yercounter aD CD CDE), Cd, 09 CP. co, 0, CE INTTC1 J [Applications] @ Period / Frequency measurement @ Duty measurement (b) Double Edge Capture Figure 2-18. Pulse Width Measurement Mode Timing Chart 87C446-57 2003-09-17

Example: Duty measurement (Resolution fc/2” [Hz]) CLR (INTTC1C).0 ;_ INTTC1 service switch initial setting LD (EINTCR), 00000000B ; Sets the rise edge at the INT2 edge LD (TC1CR), 000001108 ; Sets the TC1 mode and source clock SET (EIRL).4 ; Enables INTTC1 EI LD (TC1CR), 001101108 ; Starts TC1 with an external trigger PINTTC1: CPL (INTTC1C).0 ; Complements INTTC1 service switch JRS_—F,SINTTC1 LD (HPULSE), (TREG1BL) ; Reads TREG1B LD (HPULSE + 1), (TREG1BH) RETI SINTTC1: LD (WIDTH), (TREG1BL) ; Reads TREG1B (Period) LD — (WIDTH + 1), (TREG1BH) RET1 VINTTC1: DW PINTTC1 (6) Programmable Pulse Generate (PPG) output mode Counting is started by an edge of the TC1 pin input (either the rising or falling edge can be selected) or by a command. The source clock is used an internal clock. First, the contents of TREG1B are compared with the contents of the up-counter. If a match is found, timer F/F1 output is toggled. Next, timer F/F1 is again toggled and the counter is cleared by matching with TREG1A. An INTTC1 interrupt is generated at this time. Timer F/F output is connected to the P14 (PPG) pin. In the case of PPG output, set the P14 output latch to “1” and configure as an output with P1CRq. Timer F/F1 is cleared to “0” during reset. The timer F/F1 value can also be set by program and either a positive or negative logic pulse output is available. Also, writing to the TREG1B is not possible unless the timer / counter 1 is set to the PPG output mode with TC1M. 87C446-58 2003-09-17

Internal clock J J J | J command start Up-counter 8 KKK DEK TAK 2 recta CE Se | matey NNN Resta CC DS PPG output ff Note:m>n INTTC1 | (a) Pulse count start TC1 pininput i trigger external trigger start Internal clock i l | l J J l Up-coune OOOGONIG TRE Cr | match) Resta Ce PPG output i Note :m>n INTTC1 J [Applications] One shot pulse output (b) Single Figure 2-19. PPG Output Mode Timing Chart Example: Pulse output (“H” level <— 800 ys, “L” level — 200 us) (at fc = 8 MHz) SET (P1).4 ; P14 output latch —1 Lo (P1cR), 00010008 ; Sets the P14 output mode LD (TC1cR), 100000118 ; Sets the PPG output mode TFF=1 Low (TREG1A), 03E8H ; Sets the period (1 ms + 1 1s =03E8}) Low (TREG1B), 00C8H ; Sets the “L" level pulse width (200 ys + 1 »s = 00C8}) Lo (TC1CR), 100100118 ; Command start 87C446-59 2003-09-17

Data output {oo} TFFI pset output enable te se reset ° TCICR write strobe [ [] P14 PPG) pin match with TREG1B match with TREGIA | D7-pressle B INTTC1 interrupt ral Timer F/F 1 Al sI-T) TC1S clear signal MPPG1 Figure 2-20. PPG Output 2.6 16-bit Timer/Counter 2 (TC2)

2.6.1 Configuration

te2s >> Te2pin DH>[H MPX U window {223 or f5/215: lA [ ) iB £c/28)>—>|€ event counter source 123: bY A, | clock fe E fs] Tc2M 5 romparates Feet] _) INTC reack Teas [ma enable Timer/Counter 2 control register 16-bit timer register 2 TREG2H —-TREG2L write strobe write strobe Figure 2-21. Timer/Counter 2 (TC2) 87C446-60 2003-09-17

2.6.2 Control

The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TREG2). Reset does not affect TREG2. is 4 #8 2 #1 +0 9 8 7 6 5 4 3 2 71 O a 4) write only colin 6 5 4 3 2 1.0 (0015) a reas ace, (wnital value: +400 0020) mode select 1: Window mode 000 : Internal clock fc/2> or fs/2" [Hz] oor: fe/2 or f3/2° ow: fe/ 2 Tc2ck | Timer/counter 2 on ’ fel? write source clock select 100 ’ fe (Note 5) only 101 + fs 110 : Reserved 111 : External clock (TC2 pin input) start control 1: Start Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; don't care Note2: When writing to the low-byte of timer register 2 (TREG2,), the comparison is inhibited until the high-byte (TREG2,,) is written. After writing to the high-byte, any match during 1 machine cycle (instruction execution cycle) is ignored. Note3: Set the mode and source clock when timer/counter stops (TC2S = 0). Note4: Values to be loaded to the timer register must satisfy the following condition. TREG2 > 0 (TREG2}5.11>0 when warm-up). Note5: “fc” canbe selected as the source clock only in the timer mode during the SLOW mode. Note 6: Always write “0” to bit 0 in TC2CR. Note 7: TC2CR and TREG2 are write-only registers and must not be used with any of the read- modify-write instructions. Figure 2-22. Timer Register 2 and TC2 Control Register

2.6.3 Function

The timer/counter 2 has three operating modes: timer, event counter and window modes. Also timer/counter 2 is used for warm-up when switching from SLOW mode to NORMAL2 mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of TREG2 are compared with the contents of up-counter. If a match is found, a timer/ counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. Also, when fc is selected as the source clock during SLOW mode, the lower 11 bits of TREG2 are ignored and an INTTC2 interrupt is generated by matching the upper 5 bits. Thus, in this case, only the TREG2y setting is necessary. 87C446-61 2003-09-17

Table 2-4. Source Clock (Internal Clock) for Timer/Counter 2 Resolution Maximum time setting SLOW mode | SLEEP mode fc/2*[Hz] | fs/2°[Hz] fs/2°[Hz]| — fs/2"° [Hz] 1.05 s Tos 19.1 hour 18.2 hour fe/2" 5/2 f5/2° 5/2 1.02 ms 1 ms 1.1. min 1 min fel? fe? - - 1 os - 65.5 ms - - - fc (Note) - 125 ns - 7.9 ms - fs fs = = 30.5 2s Example: Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 8 MHz). LD (TC2CR), 000011008 ; Sets the TC2 mode and source clock Low (TREG2), 61A8H ; Sets TREG2 (25ms + 23/fc = 61A8}) SET (EIRH). EF14 ; Enables INTTC2 El LD (TC2CR), 001011008 ; Starts TC2 (2) Event Counter Mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TREG2 are compared with the contents of the up-counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The maximum frequency applied to the TC2 pin is fc/24 [Hz] in NORMAL1/2 or IDLE1/2 mode, and fs/24 [Hz] in SLOW or SLEEP mode. Example: Sets the event counter mode and generates an INTT2 interrupt 640 counts later. LD (TC2CR), 000111008 ; Sets the TC2 mode Low (TREG2), 0640H j Sets TREG2 SET (EIRH). EF14 ; Enables INTTC2 El LD (TC2CR), 001111008 ; Starts TC2 (3) Window Mode In this mode, counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC2 pin input (window pulse) and an internal clock. The internal clock is selected with TC2CK. The contents of TREG2 are compared with the contents of up-counter. If a match is found, an INTTC2 interrupt is generated, and the up-counter is cleared to “0”. It is necessary that the maximum applied frequency (TC2 input) be such that the counter value can be analyzed by the program. That is, the frequency must be considerably slower than the selected internal clock. TC2 pin input H 1 1 Internal clock | l: l ‘] i l J | i ' Up-counter 0 CEX2K XoXo? AKO KZ XS) ReG2 a counter cleé INTTC2 interrupt match nen eer Figure 2-23. Window Mode Timing Chart 87C446-62 2003-09-17

2.7 8-Bit Timer/Counter 3 (TC3)

2.7.1 Configuration

Eds —— 7 control wrte3 tr) interrupt} ras > >o INT3ES lear re3pin O A [dole D fer2or f24 lay source clock overflow fo2" or fs22 8 fe? cs 2 i) [( match Tack capture P Teas scar 8-bit Timer Register 3A, 38 Timer/Counter 3 Control Register Figure 2-24. Timer/Counter 3

2.7.2 Control

TREGSA 7 6 5 4 3 2 #1 +O (0019}) Read only 7.6 5 4 3 2 1 0 Te3cr wdc ae why ; Timer/counter 3 0: Timer/event counter TC3M " ‘operation mode set 1: Capture 00 : Internal clock fe/2" or fs/2* [Hz] te3ck | Timer/counter 3 01 : Internal clock fe/2" or 5/2? source clock select 10 : Internal clock fe/2" Write 11: External clock (TC3 pin input) only Timer/counter 3 0: Stop & clear TS | start select oO: = Note 1: fc; High-frequency clock [Hz] fs ; Low-frequency clock [Hz] _* ; don’t care Note2: Set the mode, the source clock and the edge selection (INT3ES) when the TC3 stops (TC3S = 0). Note 3: Values to be loaded into timer register 3A must satisfy the following condition. TREG3A > 0(in the timer/event counter mode) Note4: TC3CR isa write-only register and must not be used with any of read-modify-write instructions. Figure 2-25. Timer Register 3A/3B and TC3 Control Register The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TREG3A and TREG3B). Reset does not affect these timer registers. 87C446-63 2003-09-17

2.7.3 Function

The timer/counter 3 has three operating modes : timer, event counter, and capture mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of TREG3A are compared with the contents of up-counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up-counter is cleared. Counting up resumes after the up-counter is cleared. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to “1". SCAP is automatically cleared after capturing. Table 2-5. Source Clock (Internal Clock) for Timer Counter 3 fe/2” or fs/2* [Hz] fs/2" [Hz] 512 ys 488.28 ys 131.1. ms 125° ms fc/2" or f5/2? - 128 4s 122.07 ps 32.8 ms 31.25 ms (2) Event Counter Mode In this mode, the TC3 pin input pulses are used for counting up. Either the rising or falling edge can be selected with INT3ES (bit 3 in EINTCR). The contents of TREG3A are compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is generated and the counter is cleared. The maximum applied frequency is fc/2* [Hz] in the NORMAL1/2 or IDLE1/2 mode, and fs/24 [Hz] in SLOW or SLEEP mode. Two or more machine cycles are required for both the “H” and “L” levels of the pulse width. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to “1”. SCAP is automatically cleared after capturing. Example: Generates an interrupt every 0.5 s, inputing 50 Hz pulses to the TC3 pin. LD (TC3CR), 00001100B ; Sets TC3 mode and source clock SET — (EIRH). EF8 ; Enables INTTC3 El LD (TC3CR), 000111008; Start TC3 (3) Capture Mode The pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals, etc. The counter is free running by the internal clock. On the rising (falling) edge of the TC3 pin input, the current contents of counter is loaded into TREG3A, then the up-counter is cleared and an INTTC3 interrupt is generated. On the falling (rising) edge of the TC3 pin input, the current contents of the counter is loaded into the TREG3B. In this case, counting continues. At the next rising (falling) edge of the TC3 pin input, the current contents of counter are loaded into TREG3A, then the counter is cleared again and an interrupt is generated. If the counter overflows before the edge is detected, FF} is set to the TREG3A and an overflow interrupt (INTTC3) is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the TREG3A value is FFy. Also, after an interrupt (capture to TREG3A, or overflow detection) is generated, capture and overflow detection are halted until TREG3A has been read out; however, the counter continues. After TREG3A has been read out, capture and overflow detection are resumed, usually, TREG3B is read out first. 87C446-64 2003-09-17

Internal clock | J J Up-counter KKK KKK Ke KKK KX 2X 2 XK EKA X 2X 2) TC3 pin input \\ | P| : 1 TREG3A > >7?0 er Hf t a H TREG38 eS {capture 1 capture overflow INTTC3 interrupt Reading TREG3A l Figure 2-26. Timing Chart for Capture Mode (INT3ES = 0) 87C446-65 2003-09-17

2.8 8-bit Timer/Counter 5 (TC5)

2.8.1 Configuration

MPX TCSS [> fo27 A Vv) 25 >—>|8 Timer F/FS fZ2 c_ | Source clear BWI POD ere yo a a fd2 > |E P | DY) tosate t>o—o Solr. fe > clear Tesck 3 Tess | Tc5M me Timer/Counter 5 control register _—_—8-bit Timer register 5 Note: MPX; Multiplexer 7? 7? CMP ; Comparator INTTCS == TCSM_ TCS Interrupt Figure 2-27. Timer/Counter 5 (TC5)

2.8.2 Control

The TCS is controlled by a timer/counter 5 control register (TC5CR) and an 8-bit timer register 5 (TREGS). 7 6 5 4 3 2 1 ~O gown [2 7 i (001DH) Write only 7.6 5S 4 3 2 1 0 tory [ress] esc, te5m_] tial ** 00 : Timer mode TcsM |TC5 Operating mode select | 01: Reserved berating 10 : Progrmmable divider output (PDO) mode 11 : Pulse width modulation (PWM) output mode 000 : Reserved 001 : Internal clock fc/2? [Hz] write 010 : Internal clock fe/25 only 011 : Internal clock fe/23 TCSCK | TC5 Source clock select 100: internal clock fe/22 101 : Internal clock f/2 110 : Internal clock fc 111: Reserved 0: Stop & clear Note 1: fc ; High-frequency clock [Hz], fs ; Low-frequency clock [Hz], » ; don’t care Note 2: The set value of timer register must satisfy the following conditions. (a) When in PWM output mode, 5<TREGS<251 (b) When in any other mode than PWM output mode, 0< TREGS Note 3: Source clock fc/22, fe/2, and fc cannot be used except in PWM output mode. Note 4: Set the mode and source clock when timer/counter stops (TC5S =0).. Figure 2-28. Timer/Counter 5 Timer Register, Control Register 87C446-66 2003-09-17

2.8.3 Function

TC 5 has 3 operating modes : timer, programmable divider output, and PWM output mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of the timer register 5 (TREG5) is compared with the contents of the up-counter. Matching with TREGS5 generates a timer/counter 5 interrupt (INTTC5) and clears the counter. Counting up resumes after the counter is cleared. Table 2-6. Source Clock (Internal clock) for TC5 fo2’ [Hz] 16 ps 4 ms fel2® 4 us 1 ms fel2? 1 us 255 us (2) Programmable divider output (PDO) mode The internal clock is used for counting up. The contents of the TREGS are compared with the contents of the up-counter. The timer F/F5 output is toggled and the counter is cleared each time a match is found. The timer F/F5 output is inverted and output to the PDO (P72) pin. This mode can be used for 50% duty pulse output. INTTCS interrupt is generated each time the PDO output is toggled. Example : 1024Hz pulse output (at fc = 4.194304 MHz) LD (TCSCR), 000010108; __ Sets to TC5 modes and source clock LD (TREGS), 10H ; Sets TREGS SET — (EIRH). EF15 ; Enables INTTCS EI LD (TCSCR), 001010108; _ Starts the measurement Internal clock | J | U LJ U L Counter DOG XXX 2K KKK MK 2X KKK OK 2X KOK! Timerregisters XB Timer F/F 5 ' i ' i PDOO pin INTTCS interrupt | | Figure 2-29. PDO Mode Timing Chart 87C446-67 2003-09-17

(3) Pulse width modulation (PWM) output mode PWM output with a resolution of 8-bits is possible. The internal clock is used for counting up. The contents of the TREGS is compared with the contents of the up-counter. If a match is found, the timer F/F5 output is toggled. The counter continues counting and, when an overflow occurs, the timer F/F5 output is again toggled and the counter is cleared. The timer F/F5 output is inverted and output to the PWM (P72) pin. An INTTCS interrupt is generated when an overflow occurs. TREGS is configured a 2- stage shift register and, during output, will not switch until one output cycle is completed even if TREGS is overwritten; therefore, output can be altered continuously. Also, the first timer, TREGS is shifted by setting TC5S (bit 5 in TC5CR) to “1” after data are loaded to TREGS. Note 1: Do not overwrite TREG4 only when an INTTC4 interrupt is generated. Usually, TREG4 is overwritten in the routine of INTTC4 interrupt service. Note 2: PWM output mode can be used only in the NORMALI, 2, and IDLE1, 2 mode. Internal clock l J | J l Up-counter XX ROKK KER OK IK KKK KEK KK Kr) AH A Timerregisters Kon BS Xf Xm Timer F/F 5 t 1 t i t PWMO pin INTTCS interrupt I 1 cycle ———1 Figure 2-30. PWM Output Mode Timing Chart Table 2-7. PWM Output Mode SLOW, SLEEP mode resolution Repeat cycle fo2? [Hz] 500 ns 127.5 ps fol2 250 ns 63.8 ps fe 125ns 31.9 ps 87C446-68 2003-09-17

2.9 Serial Interface (SIO)

The 87C446/846/H46 each have two clocked-synchronous 8-bit serial interfaces (SIO). Each serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. The serial interfaces are connected to external devices via pins P75 (SO), P74 (SI), P73 (SCK) for SIO. The serial interface pins are also used as port P7. When used as serial interface pins, the output latches of these pins should be set to “1”. In the transmit mode, pins P74 can be used as normal I/O ports, and in the receive mode, the pins P75 can be used as normal I/O ports.

2.9.1 Configuration

The SIO have the same configuration, except for the addresses/bit positions of the control/ status registers and buffer registers. SIO control/status registers SIOCR1/SIOSR SIOCR2 ee Transmit and receive rr data buffer (8 bytes in DBR) “ Buffer control Shift register if 765 4 3.210 S01 pins [" i a data output 8-bit transfer 4-bit transfer SI1 pins Serial data input INTSIO interrupt request Serial clock KT pins OSerial clock VO Figure 2-31. Serial Interfaces

2.9.2 Control

The serial interfaces are controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status registers (SIOSR). The transmit and receive data buffer is controlled by the BUF (bits 2-0 in SIOCR2). The data buffer is assigned to addresses OFFO} - OFF7} for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in the receive mode or transmit/receive mode) interrupt (INTSIO) is generated. When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be selected with WAIT (bits 4 and 3 in SIOCR2). 87C446-69 2003-09-17

7 6 5 4 3 2 1 ~O socrt [sios | ie | siom (initial value: 0000 0000) i 0: Stop [sos | Indicate transfer starvstop 0 : Continue transfer SIOINH | Continue/abort transfer 1: Abort transfer (automatically cleared after abort) 000 : 8-bit transmit mode 010 : 4-bit transmit mode write SIOM__ | Transfer mode select 100 : 8-bit transmit / receive mode only 101 : &-bit receive mode 110 : 4-bit receive mode 000 : Internal clock f¢/2" or fs/25 [Hz] 001 : Internal clock fe/2° ‘Output on SCK | Serial clock select 010 : Internal clock fe/ 2° SCK pin 011 : Internal clock f¢/2° 111 : External clock (input from SCK pin) Note 1: fc; High-frequency clock [Hz], fs ; Low-frequency clock [Hz] Note2: Set SIOS to "0” and SIOINH to "1” when setting the transfer mode or serial clock. Note 3: SIOICRISIO2CR1 are write-only registers and must not be used with any of read-modify-write instructions. SIO Status Registers siosr 7 6 5 4 3 2 1.0 Serial transfer operating 0: Transfer terminated After S10S is cleared to "0", SIOFis SIOF 4 : cleared to “0” at the termination status monitor 1: Transfer in process of transfer orsetting of SIOINH./ | read ser _| Shift operating status 0 : Shift operation terminated only monitor 1: Shift operation in process SIO Control Registers 2 SHORZ a Sine Siang A 3 210 (oot) 2 wart uF | (Initial value: *#*0 0000) 00: Ty =Tp 01:7; =2T Wait | wait control 10: Ty =4Tp 11:7; =8Tp Buffer address used sio 000: 1 word transfer OFFO4 Write 001: 2 words transfer OFFO - OFF1y only Bur |Numberoftransfer words | 010: 3 wordstransfer OFFO - OFF2y 011: 4 wordstransfer OFFO - OFF3y 100 : 5 words transfer OFFO - OFF4,, 101: 6 words transfer OFFO - OFF5y 110: 7 wordstransfer OFFO - OFF6, 111: 8 words transfer OFFO - OFF74 87C446-70 2003-09-17

@® External Clock An external clock connected to the SCK pin is used as the serial clock. In this case, the P73 ‘SCK1) output latch must be set to “1”. To ensure shifting, a pulse width of at least 4 machine cycles is required. Thus, the maximum transfer speed is 244K-bit/s. (at fc = 8 MHz). ‘SCK pin input l tsckL tsckH teckL, tse > 4 teye Note : teyc = 4/fc (In NORAML1/2, IDLE1/2 modes) 4lfs (In SLOW, SLEEP modes) b. Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. @® Leading Edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/output). @ Trailing Edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). CK pin 1 1 LI 1 Opin Shiftregister (a) Leading Edge Sipin Jote: * ; don’t care (b) Trailing Edge Figure 2-34. Shift Edge (2) Number of Bits to Transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving. The data is transferred in sequence starting at the least significant bit (LSB). (3) Number of Words to Transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred is loaded to BUF in SIOBCR. An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of words is to be changed during transfer, the serial interface must be stopped before making the change. 87C446-72 2003-09-17

SO pin \\2X= X= X% INTSIO interrupt (a) 1 Word Transmit SCK pin J J SO pin \\20 X21 X 22 X23 X bo Xb: X be X bs Xo Xs Xa Xs INTSIO interrupt (b) 3 Words Transmit SCK pin J J Stpin X20 X21 X 22 X 23 X bo X bi X be X bs Xo XK Xa Xs / INTSIO interrupt (0)_3 Words Receive Figure 2-35. Number of Bits to Transfer (Example : 4-bit serial transfer)

2.9.3 Transfer Mode

SIOM (bits 5 - 3 in SIOCR1) is used to select the transmit, receive, or transmit/receive mode. (1) 4-bit and 8-bit Transmit Modes In these modes, the SIOCR1 is set to the transmit mode and then the data to be transmitted first are written to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOS to “1". The data are then output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit (LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (buffer empty) interrupt is generated to request the next transmitted data. When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer register by the time the number of data words specified with the BUF has been transmitted. Writing even one word of data cancels the automatic-wait; therefore, when transmitting two or more words, always write the next word before transmission of the previous word is completed. Note : Waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. When the transmit is started, after the SIOF goes "1” output from the SO pin holds final bit of the last data until falling edge of the SCK. The transmission is ended by clearing SIOS to “0” or setting SIOINH to “1” in buffer empty interrupt service program to end transmitting. That the transmission has ended can be determined from the status of SIOF (bit 7 in SIOSR) because SIOF is cleared to “0” when a transfer is completed. 87C446-73 2003-09-17

(2) 4-bit and 8-bit Receive Modes After setting the control registers to the receive mode, set SIOS to “1” to enable receiving. The data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the number of words specified with the BUF has been received, an INTSIO (buffer full) interrupt is generated to request that these data be read out. The data are then read from the data buffer registers by the interrupt service program. When the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read. A wait will not be initiated if even one data word has been read. Note : Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer register. If the previous data have not been read, the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read. The receiving is ended by clearing SIOS to “0” or setting SIOINH to “1” in buffer full interrupt service program. When SIOINH is set, the receiving is immediately ended and SIOF is cleared to “0”. When SIOS is cleared, the current data are transferred to the buffer in 4-bit or 8-bit blocks. The receiving mode ends when the transfer is completed. SIOF is cleared to “0” when receiving is ended and thus can be sensed by program to confirm that receiving has ended. Note: The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOS to “0”, read the last data and then switch the transfer mode. If it is necessary to change the number of words in external clock operation, SIOS should be cleared to “0” then BUF must be rewritten after confirming that SIOF has been cleared to “0”. If it is necessary to change the number of words in internal clock operation, during automatic-wait which occurs after completion of data receiving, BUF must be rewritten before the received data is read out. SS vearsi0s ——— I siOs nn SIOF SEK pin (output) | | Sipin LM 9X 1X 22X 2X 24X asX 2X a7]X boX biX b2X baX baX bs XK bX 67] INTSIO interrupt Read out Read out Figure 2-37. Receive Mode (Example: 8-bit, 1 word, internal clock) 87C446-75 2003-09-17

(3) 8-bit Transmit/Receive Mode After setting the control registers to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (DBR). After that, enable transceiving by setting SIOS to “1". When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving, the data are input to the SI pin at the trailing edges of the serial clock. 8-bit data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when the number of data words specified with the BUF has been transferred. The interrupt service program reads the received data from the data buffer register and then writes the data to be transmitted. The data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted after reading the received data. When the internal clock is used, a wait is initiated until the received data are read and the next data are written. Await will not be initiated if even one data word has been written. Note: Waits are also canceled by writing to a DBR not being used as the transmit/received data buffer register; therefore, do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written. When the transmit is started, after the SIOF goes "1” output from the SO pin holds final bit of the last data until falling edge of the SCR. The transmit/receive operation is ended by clearing SIOS to “0” or setting SIOINH to “1” in buffer full interrupt service program. When SIOS is cleared, the current data are transferred to the data buffer register in 8-bit blocks. The transmit mode ends when the transfer is completed. SIOF is cleared to “0” when receiving is ended and thus can be sensed by program to confirm that receiving has ended. Note: The buffer contents are lost when the transfer mode is switches. If it should become necessary to switch the transfer mode, end receiving by clearing SIOS to “0”, read the last data and then switch the transfer mode. When SIOINH is set, the transmit/receive operation is immediately ended and SIOF is cleared to “0”. If it is necessary to change the number of words in external clock operation, SIOS should be cleared to “0”, then BUF must be rewritten after confirming that SIOF has been cleared to “0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/receive operation, BUF must be rewritten before reading and writing of the receive/transmit data. 87C446-76 2003-09-17

2.10 8-bit High-speed Serial Output (HSO) The 87C446/846/H46 each have a clock-synchronous 8-bit serial output (HSO). The HSO has a 1-byte transmit data buffer register (HSODR). The HSODR is assigned to address OFF8} in the DBR area. The HSO is connected to the external devices via pins P76 (HSCK) and P77 (HSO). These pins are also used as the port P7. When used as pins HSCK/HSO, the P76/P77 output latches should be set to “1”.

2.10.1 Configuration

26 IB y Control HSOPR OT ‘serial data output

25 Ic circuit

123 D O) HSCK pin

afsck INH {ser Figure 2-40. High-speed Serial Output

2.10.2 Control

The HSO is controlled by a HSO control register (HSOCR). The transfer status can be determined by reading a HSO status register (HSOSR). HSO Control Register 7 6 5 4 3 2 1 0 HSOCR ee Goepeeetcsnpee Boney (0024,) ch ee (initial value: *0«* *+00) ee 00: Internal clock fe/2 [Hz] write 01: Internal clock f¢/2° only SCK | Serial clock select 10: Internal clock fe/2* 11: Internal clock fe/2? Note: fc; High-frequency clock [Hz], * ; don’t care HSO Status Register HSOSR 7 6 5 4 382 (oozay nt" [ser | ae ere sie ee nee ser _ | Shift operating status 0: Shift operation terminated (enable write to buffer) | read monitor 1: Shift operation in process _ (disable write to buffer) _| only Figure 2-41. HSO Control Register and Status Register

2.10.3 Transmit Operations

SCK (bits 1 and 0 in HSOCR) is used to select the transfer rate. Transmission is started by writing one byte of data to the HSODR. The transmit data are output sequentially to the HSO pin in synchronized with the falling edges of the serial clock, starting with the least significant bit (LSB). Writing to the buffer is disabled by the hardware during data transfers. The shift register is empty after one byte of data has been transferred, so writing to the buffer is again enabled at that point. SEF (bit 6 in HSOSR) is set to “1” during transfers (write to buffer disabled) and is cleared to “0” when a transfer is completed (write to buffer enabled); therefore, whether or not a transfer has been completed can be confirmed with a program that reads SEF. The HSCK pin is raised to “high” at the start and end of transfers. 87C446-78 2003-09-17

Note: To continue a transfer without sensing SEF, write the next data to be transferred after 9 cycles (11 cycles when fc/23 [Hz] is selected only) at the transfer rate selected with SCK after writing to the buffer. write write HSODR or rs) HSCK pin output Sonn Hs0 pin output ) oy Cy SEF Figure 2-42. High-speed Serial Output Timing Chart 87C446-79 2003-09-17

2.11 8-bit A/D Converter (ADC) The 87C446/846/H46 each have an 8-channel multiplexed-input 8-bit successive approximate type A/D converter with sample and hold. 2.11.1__Configuration Ladder resistors i Re R R R2 | VAREF + we nnne enna nnn nnnnnn enna nn + 1 vass Analog input Sample & Hold Reference Multiplexer ne i i Voltage i i Aino O Ay i 3 i aint O B i i 8 ain O c i aa ans O D i i ‘Analog i i Comparator aina O E Leet ere ee erence aAins O F clock ain7 O HEN Shift clock ENS , * “ST P6 input/output control register A/D Converter control register AID Conversion result register Figure 2-43. A/D Converter

2.11.2 Control

The A/D converter is controlled by an A/D converter control register (ADCCR) and a port P6 input/output control register (P6CR). AID Conversion Result Register apcor 7 6 5S 4 3 2 1 +O 87C446-80 2003-09-17

AID Converter Control Register 7 6 5 4 3 2 1 t) pec [Foor [Abs [Ack JANOS], SAN] italvalue: 00+0 0000) (000Ey) 0000 : AINO 0001 : AINI 0010 : AIN2 0011 : AIN3 Analog input selection 0100 : AING 0101 : AINS 0110 : AING 111 : AIN7 1*** : reserved 0: Enable 0:23 ys (at fc=8MHz) 0: - cocr | End of A/D conversion flag 0 : Under conversion or Before conversion 1: End of conversion Note 1: * ; don’t care Note 2: Select analog input when A/D converter stops. Note 3: The ADS is automatically cleared to “0” after starting conversion. Note4: The EOCF is cleared to “0” when reading the ADCDR. Note5: The EOCF is read-only. Figure 2-44. A/D Converter Control Register and A/D Conversion Result Register

2.11.3 Operation

Apply analog reference voltage to pins VAREF and VASS. (1) Start of A/D conversion First, set the corressponding P6CR bit to “1” for analog input. Clear the AINDS (bit 4 in ADCCR) to “0” and select one of eight analog input AIN7-AINO with the SAIN (bits 3-0 in ADCCR). A/D conversion is started by setting the ADS (bit 6 in ADCCR) to “1”. Conversion is accomplished in 46 machine cycles (184/fc [s] at ACK = 0). The EOCF (bit 7 in ADCCR) is set to “1” at end of conversion. Note 1: The pin that is not used as an analog input can be used as regular input/output pins. During conversion, do not perform output instruction to maintain a precision for all of the pins. Note2: To keep the same level of an analog input during 4 Machine Cycle Time is necessary for charging the electron to the sample hold circuit which has a resistor (typ.5k Q) and a capacitor (typ. 12pF) (2) Reading of A/D conversion result After the end of conversion, read the conversion result from the ADCDR. The EOCF is automatically cleared to “0” when reading the ADCDR. 87C446-81 2003-09-17

(3) A/D conversion in STOP mode When the MCU places in the STOP mode during the A/D conversion, the conversion is terminated and the ADCDR contents become indefinite. However, if the STOP mode is started after the end of conversion (EOCF = 1), the ADCDR contents are held. ADS ADCDR KX invatid XK result XinvalicXinvatig YX result «conversion time >! "< conversion time->: ib 184/fe[s] : 184/fc [s] (at ACK =0) (at ACK = 0) EOCF i —o- o> A 2 oo _ rh 4 4 4 rs ros s et e t t aa aoa a dr dor r t t t Figure 2-45. A/D Conversion Timing Chart Example: ; AIN SELECT LD (ADCCR) , 000001008. ; selectsAIN4 (at ACK=0) ; AID CONVERT START SET (ADCCR). 6 ; ADS=1 SLOOP =: TEST (ADCCR). 7 ; EOCF=1? JRS T, SLOOP ; RESULT DATA READ LD (9EH), (ADCDR) FFy — FEW 7 Conversion FD a“ result Ze 03, — 02H —< On — = {$$$ - o 4 2 3 253° 254 «255256 x VAREE vass_ Analog input voltage Figure2-46. Analog Input Voltage vs A/D Conversion Result (typ.) 87C446-82 2003-09-17

Note: The instruction for specifying Masking Option (Operating Mode) in ES Order Sheet is described in ADDITIONAL INFORMATION “Notice for Masking Option of TLCS-870 and TLCS-870X series” section 8. (1) Control pins The input/output circuitries of the 87C446/846/H46 control pins are shown below, any one of the circuitries can be chosen by a code (NM1 or NM2) as a mask option. Osc. enable Resonator connecting pins (high-frequency) XIN Input vob ih wal Ry =1.2M0 (typ) XOUT Output ‘Oo Ro =1.5k2 (typ.) XIN XxOUT Osc. enable Resonator connecting pins (low-frequency) XTIN (P21) Input Refer vob W VOD | Rk =6MQ (typ) XTOUT (P22) | Output port P2 t Ro Ro =220k2 — (typ.) XTIN XTOUT VDD oVvpD | Sink open drain output Rin Hysteresis input — R RESET VO | Address-trap-reset Pull-up resistor Watniogtimereser= =| >—— Riv=220kQ (typ.) System-clock-reset Retkd (yp) output R Hysteresis input STOP/INTS Input (P20) p20 input R=1kQ (typ.) STOP/INTS VDD R D, Pull-down resistor TEST Input input Riv=70kQ = (typ.) Rin R=1kQ typ.) Note1: — The 87PH46 does not have a pull-down resistor (Ry) and diode (D)) for TEST pin. Be sure to fix the TEST pin to low. Note2: — The input/output circuitries of the 87PH46 is the code NM1 type. 87C446-83 2003-09-17

(2) Input/Output Ports The input/output circuitries of the 87C446/846/H46 input/output ports are shown below. INPUT/ OUTPUT CIRCUITRY and CODE (A) VDD output Tri-state VO PO initial “Hi-Z” | High current output only PO vo P6 disable R input R=1k0 (typ.) VDD output Tri-state VO initial "Hi-2” | Hysteresis input vo disable R input R=1k0 (typ) Sink open drain output initial “Hi-2" V0® Pinitial “Hi-Z” P2 VO | output —>o- itput —>o-] R eusps R R=1kQ. input input vod P7CR2 Tri-state VO output initial “Hi-2” P7 vo disable me R R=1k0 (typ.) input 87C446-84 2003-09-17

Electrical Characteristics

Absolute Maximum Ratings (Vss=0V) Input Voltage Pov fo 03 t0Vo0 +03 Output Current (Per 1 pin) mA PortsP1,P2,P6,P7 Output Current (Total) mA Power Dissipation [Topr = 70°C] | po | e7cassraae/Ha6 [| 600 ~S | mw | Soldering Temperature(time) | tid [600109 Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Recommended Operating Conditions | (Vss=0V, Topr= - 30 to 70°C) symbot | ins | concvins min ax unit | NORMAL1, 2 mode fe=8MHz IDLE1, 2 mode NORMAL1, 2 mode fc=4.2MHz Supply Voltage Voo IDLE1, 2 mode 07 55 v fs= SLOW mode 32.768kHz | SLEEP mode Except hyneredisinpat Vpp24.5V Except hysteresis input Vo x0.30 iL pt hyst pI Vp=45¥ 1 [Mus [ooo esy | Woo x0.10 Vpp = 4.5 to 5.5V fe | XIN, XOUT 22 | 20 | MHz Clock Frequency Vop =2.7to 5.5V [ 42 | XTIN, XTOUT ee ee ee Note: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. 87C446-85 2003-09-17

D.C. Characteristics (Vss=0V, Topr= - 30 to 70°C) |__rerameter yma] rns | cottons | in | tym | mn | uit Hysteresis Voltage Vop= 5.0V [ - [os [ - Jv | Input Current Vpp=5.5V #2 | ua im In2_} OP por. Pore | Vy =5.5V/0V . | lina | RESET, STOP RESET [100 | 220 | 450 | ke | Output Leakage | tLo1_| Sink open drain ports Vpp = 5.5 V, Vour=5.5V [- [| - [2 ] nm Current Voo=5.5V, Vour=5swov | - | - | #2 | Output High Voltage Vop=45Vlou=-0.7mA | at | - | = | v | Output Low Voltage Except XOUT and PO Vop=4.5V, lov=1.6mA | - | - [oa] v | JOutputtowcurrent_[ los [Po Vo = 4.5V, Vou = 1.0 [| - [| 20 | - | ma | Supply Current in Vpp=5.5V 4 NORMAL 1, 2 modes fe=8 MHz Supply Current in fs = 32.768 kHz IDLE 1, 2modes Vin = 5.3 V/0.2V Supply Current i Vpp=3.0V upply Current in DD os | as NORMAL 1, 2 modes fe= 4.19 MHz nq m Supply Current in fs = 32.768 kHz 1s | 20 IDLE 1, 2 modes Vin=2.8V/0.2V ° ” Supply Current in Vpp=3.0V ‘A SLOW mode p> “ - fs = 32.768 kHz Supply Current in Vin =2.8V/0.2V SLEEP mode Supply Current in Vpp=5.5V 10 HA STOP mode Viv =5.3V/0.2V Note 1: Typical values show those at Topr=25°C. Note 2: Input Current Iwyi,linz; The current through resistor is not included, when the input resistor (pull-upor pull-down) is contained. Note 3: Ino; Except for Iner A/D Conversion Characteristics (Vsg = OV, Vpp = 4.5 to 5.5 V, Topr= - 30 to 70°C) | var | Analg Reference Volage ane | =| vo | A ee | Nonlinearity Error |_| Yoo=5.0v P= | = fos | Vas tvs9 200 [| +1 | Zero Point Error || VARS V59) =0.000 or P= f= fs ee Full Scale Error Vpop=2.7V a eae p= | = | Note : Quantizing Error is not contained in total Errors. 87C446-86 2003-09-17

A.C. Characteristics (Vss=0V, Vpp =4.5to 5.5 V, Topr= - 30 to 70°C) In NORMAL 1,2 mode - - In IDLE 1, 2mode Machine Cycle Time ty ys In SLOW mode 117.6 133.3 In SLEEP mode High Level Clock Pulse Width For external clock operation Low Level Clock Pulse Width (XIN input), f¢= 8 MHz High Level Clock Pulse Width For external clock operation 147 s Low Level Clock Pulse Width (XTIN input), fs= 32.768 kHz : “ Recommended Oscillating Conditions | (Vss=0V, Vop=4.5to 5.5V, Topr= - 30 to 70°C) Recommended Condition Parameter Frequency Recommended Oscillator KYOCERA _KBR8.0M. MURATA —_CSA8.00MTz CSACS8.00MT Ceramic Resonator CSTCS8.00MT 30 pF 30 pF KYOCERA _KBR4.0MS. High-frequency 4MHz MURATA ——_CSAC4.00MGC CSA4.00MG Crystal Oscillator 20 pF 20 pF | amie [rovocom 2048 40000 XTIN XTOUT XIN XOQUT a u Po c Cz (1) High-frequency Oscillation (2) Low-frequency Oscillation Note 1: An electrical shield by metal shield plate on the surface of the IC package should be recommendable in order to prevent the device from the high electric fiedstress applied from CRT (Cathode Ray Tube) for continuous reliable operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL http://www.murata.co.jp/searchlindex.htm! 87C446-87 2003-09-17

P-SDIP42-600-1.78 Unit: mm Lo 42 22 TV DOO ooo nn °o I a ») 3 > 38 rT Trea g 38.5MAX 38.040.2 g 2 CTT To tho j= ro} Bb oO oS 87C446-88 2003-09-17