87C809

TMP87C409B TOSHIBA | Alldatasheet

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@8-bit single chip microcomputer TLCS-870 Series P-SDIP28-400-1.78 @ instruction execution time: 0.5 ys (at 8 MHz) 412 basic instruction @ Multiplication and Division (8 bits x 8 bits, 16 bits = 8 bits) @ Bit manipulations (Set/Clear/Complement/Load/Store/Test/Exclusive or) a - TMP87C409BN @ 16-bit data operations — TMP87C809BN © 1-byte jump/subroutine-call (Short relative jump/Vector call) @ 11 interrupt sources (External: 4, Internal: 7) P-SOP28-450-1.27 @ All sources have independent latches each, and nested interrupt control is available. © 2 edge-selectable external interrupts with noise reject. @ High-speed task switching by register bank changeover @ 3 Input/Output ports (22 pins) e High current output: 6 pins (Typ. 20 mA) TMP87C4098M 16-Bit Timer/Counter TMP87C809BM © Timer, Event counter modes (000707661 @ For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. @ [OSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA Products could cause loss of human life, bodily injury or damage to property In developing your designs, please ensure that [OSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA, products specifications, Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. @The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, ersonal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc). These TOSHIBA products are neither intended nor warranted for usage in equipment’ that requires extraordinarily high quality andior ‘reliability or a, malfunction or failure of which may cause loss of human life or. bodily injury (Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's ‘own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual Property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. Zeal Purchase of TOSHIBA I? C components conveys a license under the Philips ? C Patent Rights touse these. —_ [| Gls) components in an I? C system, provided that the system conforms to the I? C Standard Specification as defined by [BUS] Philips. 3-09-1 2002-01-08

@ Two 8-Bit Timer/Counters @ Timer, Event counter, Capture (Pulse width/duty measurement), PWM output, Programmable divider output modes. @ Time Base Timer (Interrupt frequency: 1 Hz to 16 kHz) @ Divider output function (frequency: 1 kHz to 8 kHz) @ Watch dog Timer @ Serial bus Interface (SBI-ver. B) © 12C bus, 8-bit SIO modes. @ 10-bit successive approximate type AD converter ® 8 analog inputs @ Two Oscillation Stop Detector outputs (High-impedance output) ‘@ Two Power saving operating modes @ STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance. @ IDLE mode: CPU stops, and Peripherals operate using high-frequency clock. Release by interrupts. @ Emulation Pod: BM87C809N0A. 3-09-2 2002-01-08

Pin Assignments (Top View) P-SDIP28-400-1.78 / P-SOP28-450-1.27 xour <—(]1 28 F1=<— von (vareF) xin —> (2 27 1) =<— RESET (AINo) P60 <> C4 25 [<> p16 (AIN1) P61 <> (5 24 <> pis (ain2) p62 <> C16 23 <> p14 (Aina) P64 <> 8 21 f) <> P12 (TC1) {AINS) P6S <> (9 20 Fi ~<> P11 (INT1) (aine) P66 <>C] 10 19 [1 <> P10 (INTO) (AIN7/VAREF) P67, <> (411 18 [<> p43 (STOP/INTS) (TC3/INT3/CLZ0) P50 <>} 12 17 F< P42 (sDA/so) (TC4/PWMIPDO/CLZ1) P51 <>] 13 16 [<> P41 (SCLSI) (vass) vss —>C] 14 15 F1~<> pao (CK) Block Diagram Power { voo ‘Supply \\ vss V f rsw | [iar Data Memory Cie Tes] Se Register Banks Reset pin RESET Prose Menor Resonator Seailation Timer Timer/Counters || | Timer/Counters, Interface ref aI] Oeste” | = = Decoder i © ee ae 2 | a O O O O o-bit AD if i i i P67 (AIN7) VAREE PI7%0P10 #140 PSO a3 to PA0 to (VO0/P67) P60 (AINO) Analog {analog input) reference voltage 3-09-3 2002-01-08

PI7toP14 vo &-bit programmable input/output ports P13 (DVO) VO (Output) _| Each bit of the port can be individually —_| Divider output cveeteatanetufcueunnnonee nese] Configured as an input or an output under fsrseesenetsnsenseeenseteneneeneesessee P12(TC1) software control. Timer/Counter 1 input osssessrsssessssassesensesesee When used as an external input or a timer evssseevssesvsseeenseeseneeesaneeennseernnsesnnareense P11 (INT1) VO (Input) counter input, the input mode is External interrupt input 1 P10 (INTO) output, the latch must be set to “1*. External interrupt input 0 43 (STOP/INTS) VO (Inpuvinput) | 4-bit input/output port with latch (high inerupesinpat everternal esrivrenernneneee nerrsrenennernen] CUFTENE OUEPUL). INCSCTUpE S IM PUE . scessssenereser mone , 2 P42 (SDAVSO) YO (vO/Output) | When used as an input port, an I2C serial gata outaut ee outeut or SiO ferenttstnsentetsnfsnissstnsentseeesse jMpUUOUtpUt oF an external interrupt Neen eeaee iamcaiouipat ori P40 (SCK) vO (VO) SIO serial clock input/output 2-bit programmable input/output ports (tri-state, high current output). P51 (TC4/PWM/ =| 1/0 (Input/Output | Each bit of the port can be individually _| Timer/counter 4 input or &-bit PWM PDO/CLZ1) /Output/Output)) | configured as an input or an output under | Output or 8-bit PDO output or oscillation software control. stop detector output 1 When used asa timer counter input or an seeneeueueneimagiie) snstasiesinnenanneee external interrupt input the input mode is. [vwverseeeussnnenanssseeneneesssssnse configured. When used as a PWM/PDO output, the Timer/counter 3 input or external P50 VO (Input/input | latch must beset to “1” and the output —_| interrupt input 3 or oscillation stop (TC3/NT3/CLZO) fOutpuy) mode is configured. detector output 0 When used as a oscillation stop detector ‘output, the output mode is configured. bit programmable input/output ports (tri-state). AD converter analog input or analog P67 (AINZ/VAREF) | VO(Inputinput) |e 2ch bit of the port can be individually reference power supply ossustuseuseuseuetnen) oeieeineaneuseeeneees] Configured as an INPUT OFAN OULPUT UNMET Ys aasnsentnetsesnsnetneenesen software control. P66 (AIN6) to P60 When used as an analog input or an , (Aino) VO(Input) | analog reference power supply, the input_| AP converter analog inputs mode is configured. Resonator connecting pins for high-frequency clock. XIN, XOUT Input, Output | Forinputting external clock, KIN‘ used and ROUT Is opend. RESET | imur—| Reset signal input. Power Supply VSS (VASS) Ov (GND) Analog reference GND 3-09-4 2002-01-08

1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a watchdog timer. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 1.1. Memory Address Map The TMP87C409B/809B are capable of addressing 64 Kbytes of memory. Figure 1-1 shows the memory address maps of the TMP87C409B/809B. In the TMP87C409B/809B the memory is organized 3 address spaces (ROM, RAM and SFR). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the RAM address space. 0000, SFR ( 64 bytes : Register banks Note: ROM; Read Only Memory includes: i | 128 bytes . : 5: a8 byt ) (8 registers x 16 banks) Program memory o0f0 RAM ; Random Access Memory includes: RAM] —: | 128 bytes Data memory i Stack O13F H General- purpose register banks Pod i SFR; — Special Function Register includes: Pb aa NO ports iT ¥ Peripheral hardware control registers fi : Peripheral hardware status registers is = ‘System control registers pod i Interrupt control registers ae : Program Status Word £000 [ 793 DL bytes Fooo LC 3ea0 1 i i bytes rego [ono rego [teen Hy 192 Hy 192 Rom i bytes H bytes FEBE for BEBE foennedy Vector table for Entry area for page vector call instruction ERDF [Sones |) ERDF | Bzbytes |) vere Interrupt vector table rere | 22 bytes ) reer | S2bvtes ) (ieveclors) TMP87C809B TMP87C409B Figure 1-1. Memory address map 3-09-5 2002-01-08

1.2. Program Memory (ROM) The TMP87C409B has a 4 Kbytes (addresses F000 to FFFF}) , the TMP87C809B has a 8 Kbytes (address E000 to FFFF\\y) of program memory (mask programmed ROM). Figure 1-2 shows a program memory map. Addresses FFOO to FFFFY of program memory is also used for a special purpose. (1) Interrupt vector table (addresses FFEO to FFFFy) This table consists of a reset vector and 16 interrupt vectors (2 bytes/vector). These vectors store a reset start address and interrupt service routine entry addresses. (2) Vector table for vector call instructions (addresses FFCO to FFDF;1) This table stores call vectors (subroutine entry address, 2 bytes/vector) for the vector call instructions [CALLV a]. There are 16 vectors. The CALLV instruction increases memory efficiency when utilized for frequently used subroutine calls (called from 3 or more locations). ' (3) Entry area(addresses FFOO to FFFFy) for page call instructions This is the subroutine entry address area for the page call instructions [CALLP a]. Addresses FF00 to FFBFy are normally used because addresses FFCO to FFFF} are used for the vector tables. Programs and fixed data are stored in the [Address program memory. The instruction to be ein ROM contents executed next is read from the address i indicated by the current contents of the if re - i Example: The relationship program counter (PC). There are relative : between ROM jump and absolute jump instructions. The FF00 Contents and Call concepts of page or bank boundaries are not 3 group — i A i instructions/interrupt/ used in the program memory concerning any i Reset jump instruction. : CALLP 78H; PC & FF7By Example: The relationship between the Fre jump instructions and the PC. FFCO | callvector(L) |56 CALLV OH ; PC < F856q © _5-bit PC-relative jump [IRS cc, $+2+d] FFC1 | call vector(H) | F8 F8C4H: JRS T, $+2+08H FFC2 When JF=1, the jump is made to i F8CEy, which is 084 added to the i contents of the PC. (The PC contains | FFOF }- the address of the instruction being | FFEO 68 INTS i PC & F368, executed +2; therefore, in this case, aa interrupt vector (H)| F3 the PC contents are F8C4y + 2 = F8C6q.) H | | it PC-relative j FFFD @ 8-bit Pevelative jump UR ce: Sa2+dl rere. |_resetvector(i)__|3¢ Reser | PC e Fay , ores FFFF | resetvector(H) | FO When ZF=1, the jump is made to F846}, which is FF80q (-128) added to Figure 1-2. Program memory map the current contents of the PC. @ 16-bit absolute jump [JP a] F8C4H: JP OF235H An unconditional jump is made to address F235. The absolute jump instruction can jump anywhere within the entire 64-Kbytes space. 3-09-6 2002-01-08

In the TLCS-870 Series, the same instruction used to access the data memory is also used to read out fixed data stored in the program memory. The register offset PC-relative addressing (PC + A) instructions can also be used, and the code conversion, table look-up and n-way multiple jump processing can easily be programmed. Example 1: Loads the ROM contents at the address specified by the HL register pair contents into the accumulator (TMP87C809B: HL 2 E0004) LD A,(HL) ; Aj ROM (HL) Example 2: Converts BCD to 7-segment code (common anode LED). When A=05y, 92 is output to port P1 after executing the following program. ADD A, TABLE-$-4 ; P1<-ROM (TABLE +A) g h. LD (P1), (PC+A) 7 JRS T, SNEXT ; Jump to SNEXT AG, TABLE: DB OCOH, OF9H, OA4H, OBOH, 99H, 92H, 82H, OD8H, 80H, 98H d SNEXT: — Note: “$” is a header address of ADD instruction. DB is a byte data definition instruction. Example 3: N-way multiple jump in accordance with the contents of accumulator (0 S A $3). ial SHLC A ; if A=00} then PC—F234q Jp (PC +A) if A=01y then PC <—F378q — a if A=02y then PC <—FA37y =F if A=03y then PC <—F1BOq DW 0F234H, OF378H, OFA37H, OF1B0H Note: DWis a word data definition instruction. Word =2 bytes. 1.3. Program Counter (PC) The program counter (PC) is a 16-bit register which indicates the program memory address where the instruction to be executed next is stored. After reset, the reset vector stored in the vector table (addresses FFFF and FFFE}) is loaded into the PC; therefore, program execution is possible from any desired address. For example, when FO and 3Ey are stored at addresses FFFF and FFFEy, respectively, the execution starts from address FO3Ey after reset. The TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, the PC always indicates 2 addresses in advance. For example, while a 1-byte instruction stored at address F123} is being executed, the PC contains F125p. se LsB isumiswinwse76s43210 ‘ProgramCounter Xa a+t X a+2 Xa+3_ ) (a) Configuration (b) Timing chart of PC counters and Instruction Execution Figure 1-3. Program counter 3-09-7 2002-01-08

1.4 DataMemory (RAM)

The TMP87C409B/809B have 256 bytes (addresses 0040 to 013F}) of data memory (static RAM). Figure 1-4 shows the data memory map. Addresses 0000 to OOFFy are used as a direct addressing area to enhance instructions which utilize this addressing mode; therefore, addresses 0040 to OOFF} in the data memory can also be used for user flags or user counters. Example 1: If bit 2 at data memory address 00CO} is “1”, 004 is written to data memory at address 00E3y; otherwise, FF is written to the data memory at address 00E3}. TEST (OOCOH).2 j if (00CO})2 =0 then jump JRS — T,SZERO CLR (00E3H) ; (00E3y) —00,, JRS— T,SNEXT SZERO: LD — (00E3H), OFFH 3} (00E3q) — FF ‘SNEXT: Example 2: Increments the contents of data memory at address OOF5y, and clears to 004 when 10 is exceeded. INC (OOFS5H) AND (00F5H), OFH General-purpose register banks (8 registers x 16 banks) are also assigned to the 128 bytes of addresses 0040 to OOBFH. Access as data memory is still possible even when being used for registers. For example, when the contents of the data memory at address 00404 is read out, the contents of the accumulator in the bank 0 are also read out. The stack can be located anywhere within the data memory except the register bank area. For more details on the stack, see section “1.7 Stack and Stack Pointer”. With the TLCS-870 Series, programs in data memory cannot be executed. If the program counter indicates a data memory address (addresses 0040 to 013F}), an address-trap-reset is generated due to bus error. (Internal reset is occered) The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example: Clears RAM to 0 except the bank 0 LD HL, 0048H j Sets start address to HL register pair LD A,H i Setsinitial data (A) LD BC, O0F7H ; Sets number of byte to BC register pair SRAMCLR: LD (HL+),A DEC BC JRS_—F, SRAMCLR Note: “$” isa header address of ADD instruction. The general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the current bank addresses. Clears RAM to 0 except the bank 0. 3-09-8 2002-01-08

Address 0 1 2 3 4 5 6 7 8 9 ABC ODE F 00404 z__ Register bankO 2 Register bank 1. cee fo gagiar banks Reger bangs soca poe vf casas cong foemigarbaniga™ po giscrang ee penn babe aka aed ooao |; RegisterbankS fs. Regiterbanke sd | pirectaddressing area 0090 . Reaisterbank10 , Registerbank11 ce, pcteopagiaar bankas agentes cose Pe gagiatar pani PT ~eaergang 9000 LS oro Pep EE EEE

0130 PEEP ppp EEE EG

Figure 1-4. Data memory map

1.5 General-purpose Register Banks

General-purpose registers are mapped into addresses 0040 to OOBFy in the data memory. There are 16 register banks, and each bank contains eight 8-bit registers W, A, B, C, D, E, H, and L. Figure 1-5 shows the general-purpose register bank configuration. The unused register banks can be used as a data memory. | Bank 15 (0088 to 00BF}) . | Bank 14 (00B0 to 00B7y) rome Penk? ; Bank 13 (00A8 to OOAFy) H wia Bank 12 (00A0 to 00A74) {og a) (eae jevnsenesefeesreee Bank 4 (0060 to 0067) ore Dig Bank 3 (0058 to 005F;,) {0005H) (0044) eseeseeseebneeneese Bank 2 (0050 to 0057y) i HoGok Bank 1 (0048 to 004Fy) (00474) : (0046,)

7 Bank 0 (0040 to 00474)

{a) Configuration (b) Address assignments of registers Figure 1-5. General-purpose register banks 3-09-9 2002-01-08

In addition to access in 8-bit units, the registers can also be accessed in 16-bit units as the register pairs WA, BC, DE, and HL. Besides its function as a general-purpose register, the register also has the following functions. (1) A, WA The A register functions as an 8-bit accumulator and WA the register pair functions as a 16-bit accumulator (W is high byte and A is low byte). Registers other than A can also be used as accumulators for 8-bit operations. Examples: © ADD A, B ; Adds B contents to A contents and stores the result into A. @SUB WA, 1234H =; Subtracts 1234y from WA contents and stores the result into WA. @ SUB E,A ; Subtracts A contents from B contents, and stores the result into E. (2) HL, DE The HL register functions as a data pointer/index register/base register, and the DE register pair function as a data pointer to specify the memory address. HL also has an auto-post-increment and auto-pre-decrement functions. This function simplifies multiple digit data processing, software LIFO (last-in first-out) processing, etc. Example 1:@ LD A, (HL) ; Loads the memory contents at the address specified by HL into A. @ LD A, (HL+52H) ; Loads the memory contents at the address specified by the value obtained by adding 521 to HL contents into A. @LD A, (HL+C) ; Loads the memory contents at the address specified by the value obtained by adding the register C contents to HL contents into A. @®LD A, (HL+) ; Loads the memory contents at the address specified by HL into A. Then increments HL. © LD A, (-HL) ; Decrement HL. Then loads the memory contents at the address specified by new HL into A. TLCS-870 Series can transfer data directly memory to memory, and operate directly between memory data and memory data. This facilitates the programming of block processing. Example 2: Block transfer LD B,M ; m=n-—1(n: Number of bytes to transfer) LD HL, DSTA ; SEts destination address LD DE, SRCA ; Setssource address SLOOP: LD (HL), (DE) ; (HL) < (DE) INC HL ; HL©HL+1 INC DE ; DE <DE+1 DEC B ; BeB-1 JRS_ F, SLOOP ; if B20 thenloop 3-09-10 2002-01-08

(3) B, C, BC Registers B and C can be used as 8-bit buffers or counter, and the BC register pair can be used as a 16- bit buffer or counter. The C register functions as an offset register for register offset index addressing (refer to example 1 @ above) and as a divisor register for the division instruction. Example 1: Repeat processing LD Bn. } Sets nas the number of repetitions SREPEAT: processing : DEC B JRS Ff, SREPEAT Example 2: Division (16-bit + 8-bit) DIV. WA, C ; Divides the WA contents by the C contents, places the quotient in A and the remainder in W. The general-purpose banks are selected by the 4-bit register bank selector (RRS). During reset, the RRS is initialized to “0”. The bank selected by the RBS is called the current bank. Together with the flag, the RBS is assigned to address 003F} in the SFR as the program status word (PSW). There are 3 instructions [LD RBS, nl, [PUSH PSW1, [POP PSW1] to access the PSW. The PSW can be also operated by the memory access instruction. Example 1: Incrementing the RBS INC (003FH) ; RBS <— RBS +1 Example 2: Reading the RBS LD A, (003FH) i; A&RBS (The flags are simultaneously read in this instruction.) Highly efficient programming and high speed task switching are possible by using bank changeover to save registers during interrupt and to transfer parameters during subroutine processing. During interrupt, the RBS is automatically saved onto the stack. The bank used before the interrupt is automatically restored by executing an interrupt return instruction [RETIJ/RETN] ; therefore, there is no need for the RBS save/restore software processing. The TLCS-870 Series supports a maximum of 15 interrupt sources. One bank is assigned to the main program, and one bank can be assigned to each source. Also, to increase the efficiency of data memory usage, assign the same bank to interrupt sources which are not nested. Example: — Saving/restoring registers during interrupt task using bank changeover. PINT1: LD RBS, n ; RBS < n (Bank changeover) RETI ; Maskable interrupt return (Bank automatic restoring) 3-09-11 2002-01-08

1.6 Program Status Word (PSW)

The program status word (PSW) consists of a register bank selector (RBS) and flags, and the PSW is assigned to address 003F} in the SFR. The RBS can be read and written using the memory access instruction, however the flags can only be tread. When writing to the PSW, the change specified by the instruction is made without writing data to the flags. For example, when the instruction [LD (003FH), 05H] is executed, “5” is written to the RBS and the JF is set to “1", but the other flags are not affected. During interrupt, PSW is saved to the stack with the program counter. The PSW is restored from the stack by executing return instructions [RETI]/[RETN]. [PUSH PSW] and [POP PSW] are the PSW access instructions.

1.6.1 Register bank selector (RBS)

The register bank selector (RBS) is a 4-bit register used to select general-purpose register banks. For example, when RBS = 2, bank 2 is currently selected. During reset, the RBS is initialized to “0”. 7.6 5 4 3 2 1 0 Figure 1-6. PSW (Flags, RBS) configuration

1.6.2 Flags (FLAG)

The flags are configured with the upper 4 bits: a zero flag, a carry flag, a half carry flag and a jump status flag. The flags are set or cleared under conditions specified by the instruction. These flags except the half carry flag are used as jump condition “cc” for conditional jump instructions [JR cc, $ + 2 +d], [JRS cc, $+2+d]. After reset, the jump status flag is initialized to “1”, other flags are not affected. (1) Zero flag (ZF) The ZF is set to “1” if the operation result or the transfer data is 004 (for 8-bit operations and data transfers)/0000y (for 16-bit operations); otherwise the ZF is cleared to “0”. During the bit manipulation instructions, the ZF is cleared to “0” if the contents of the specified bit is “1". This flag is set to “1” when the upper 8 bits of the product are 004 during the multiplication instruction, and when 00y for the remainder during the division instruction; otherwise it is cleared to “o". (2) Carry flag (CF) The CF is set to “1” when a carry occurred during addition or a borrow occurred during subtraction; otherwise the CF is cleared to “0”. During division, this flag is set to “1" when the divisor is 004 (divided by zero error), or when the quotient is 1004 or higher (quotiont-overflow error). The CF is also affected during the shift/rotate instructions. The data shifted out from a register is set to the CF. This flag is also a 1-bit register (a boolean accumulator) for the bit manipulation instructions. Set/clear/invert are possible with the CF manipulation instructions. Example: Bit manipulation (The result of exclusive-OR between bit 5 content of address 07} and bit O content of address 9Ay is written to bit 2 of address 014.) LD CF, (0007H).5 } (00014)2 — (00074)5 4 (009AH)o XOR CF, (O09AH).0 LD (0001H) . 2, CF 3-09-12 2002-01-08

(3) Half carry flag (HF) The HF is set to “1” when a carry occurred to bit 4 of the operation result during an 8-bit addition, or when a borrow occurred from bit 4 of the result during an 8-bit subtraction. This flag is useful in the decimal adjustment for BCD operations (adjustments using the [DAA r], or [DAS r] instructions). Example: BCD operation (The A becomes 47} after executing the following program when A = 19, B = 28H.) ADD A, B ; A©& 41y, HE 1,CF=0 DAA A i A © 414 + 064 = 474 (decimal-adjust) (4) Jump status flag (JF) The JF is usually set to “1”. Zero or carry information is set to the JF after operation. The JF provides the jump condition for conditional jump instructions [JR T/F, $+2=d], [JRS T/F, $+2+d] (T or Fis a condition code). Example: Jump status flag and conditional jump instruction Inc A JRS_T, SLABLE1 ; Jump when a carry is caused by the immediately preceding i operation instruction. LD A,(HL) JRS — T, SLABLE2 ; JFissetto “1” by the immediately preceding instruction, 5 making it an unconditional jump instruction. Example: The accumulator and flags becomes as shown below after executing the following instructions when the WA register pair, the HL register pair, the data memory at address 00C5y, the carry flag and the half carry flag contents being “219A”, “OOC5y", “D7”, “1", and “0”, respectively. Accumulator Accumulator Instruction after r 7 Instruction after 7 7 ADDC A, (HL) nR vioirial Jmc oa 98 oio:tio SUBB A, (HL) C2 1:0: 1:0 ROLC A 35 i ee) cup A, (HU) 9A 0:01! 0 RORC A co of oioio AND A, (HL) 92 o:0:4 : 0 ADD WA, OFS08H | -16A2 1 : of1io iD A (HD) v7 tioitio] mum wa 13DA oloitio ADD A, 66H 00 tiviria SET AS BA titirio 3-09-13 2002-01-08

1.7. Stack, Stack Pointer

1.7.1 Stack

The stack provides the area in which the return address or status, etc. are saved before a jump is performed to the processing routine during the execution of a subroutine call instruction or the acceptance of an interrupt. On a subroutine call instruction [CALL a] / [CALLP a] / [CALLVn], the return address is saved (the upper byte is pushed first, followed by the lower byte). During software interrupt instruction [SW!] execution or interrupt, the program status word is saved, then the return address is saved. When returning from the processing routine, executing a subroutine return instruction [RET] restores the contents to the PC from the stack; executing an interrupt return instruction [RETI] / [RETN] restores the contents to the PC and the PSW. The stack can be located anywhere within the data memory.

1.7.2 Stack pointer (SP)

The stack pointer (SP) is a 16-bit register to point out the first M start address on the stack. The SP is post-decrement when a | “S* s8 A a 151413 121110 9876543210 subroutine call or a push instruction is executed, or when an interrupt is accepted; and the SPC is pre-incremented when a Stack Pointer (SP) return or a pop instruction is executed. The stack deepens to Figure 1-7. Stack pointer the direction of the lower address. Figure 1-8 shows the change of the stack access and the SP. The SP is not initialized hardware-wise but requires initialization by an initialize routine (sets the highest stack address). [LD SP, mn], [LD SP, gg] and [LD gg, SP] are the SP access instructions (mn; 16-bit immediate data, gg; register pair). Example 1: To initialize the SP LD SP, 013FH 7 SP<-013FH Example 2: TO read the SP LD HL, SP > HL<sP At acceptance of interrupt At execution of or At execution of aCALUCALLV/CALLP at execution of At execution of a RETURETN instruction a SWI instruction a RET instruction instruction ose Pn ose fn ose [I ore | 013D 0130] = PC, 013D 013d] PC, O13E | PCL <P O13E] PCH ~<PEON, 013E] PCL —>, O1BE] PCH oa serene] BUSH eseesenthocn paertee] at esseetnthecey O13F | PCy pn O13F | SW me O13F | PCH pe OTF POW 0040, i Stack : depth SP bet [or3F] [030] : execution Coe] [0130] GES | Y 1 1 Y 013F Satter, (0130 | 013C [_o13F_ | [ovat] (a) Stacking order (b) Stack depth Figure 1-8. Stack 3-09-14 2002-01-08

1.8 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a stand-by controller. Timing generator control register if generator } gy 0036, XIN ite a F | High-frequency |! Timing of: i Stand-by controller E |] clock oscillator | : generator rk lock oscillat : to xouT “>: ; System clocks | gq3g,, 00395 Clock generator control System control registers Figure 1-9. System clock controller

1.8.1 Clock generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. The high-frequency (fc) clocks can be easily obtained by connecting a resonator between the XIN/KOUT pins. Clock input from an external oscillator is also possible. xin XOUT XIN xe ! i i (open) | i oO i i H H H i i H ‘ t (a) Crystal/Ceramic (b) External oscillator | Figure 1-10. Example of resonator connection Note: Accurate Adjustment of the Oscillation Frequency: Although no hardware to externally and directly monitor the basic clock pulse is provided, the oscillation frequency can be adjusted by making the program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand

1.8.2 Timing generator

The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware. The timing generator provides the following functions: @_ Generation of main system clock @ Generation of divider output (DVO) pulses @_ Generation of source clocks for time base timer @ Generation of source clocks for watchdog timer © Generation of internal source clocks for timer/counters © Generation of internal serial clock of serial interface @ Generation of warm-up clocks for releasing STOP mode (1) Configuration of Timing Generator The timing generator consists of a 21-stage divider with a divided-by-2 prescaler. During reset and at releasing STOP mode, the divider is cleared to “0”, however; the prescaler is not cleared. Note: Even if the main system clock is changed by the clock gear, the output from the divider is not changed. The peripheral circuit using high-speed divider output (1st output) can not be used when the main system clock slows down. fe . Machine cycle counters Prescaler Divider Divider fo/28 High-frequency ,_ fe fo4), 7 12] 17]18|19]20} clock | | Hef ) Stand-by Timer / of controller If Counters tty | _F>) wotendog — timer p base timer a ro ) ice output circuit Figure 1-11. Configuration of timing generator (2) Machine Cycle Instruction execution and built-in hardware operation are synchronized with the system clock. The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different types of instructions for the TLCS-870 Series: ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (SO to $3), and each state consists of one main system clock. ie [s] i t t i Figure 1-12. Machine cycle 3-09-16 2002-01-08

1.8.3 Stand-by controller

The stand-by controller starts and stops the oscillation circuits. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1-13 shows the operating mode transition diagram and Figure 1-14 shows the system control registers. Either the single-clock or the dual-clock mode can be selected by an option during reset. (1) Operation mode @ NORMAL mode In this mode, both the CPU core and on-chip peripherals operate. The TMP87C409B/809B are placed in this mode after reset. @ IDLE mode In this mode, the CPU and the watchdog timer are halted; however, on-chip peripherals remain active. IDLE mode is started by the system control register 2, and IDLE mode is released to ' NORMAL mode by an interrupt request from on-chip peripherals or external interrupt inputs. When IMF (interrupt master enable flag) is “1” (interrupt enable), the execution will resume upon acceptance of the interrupt. and the operation will return to normal after the interrupt service is completed. When IMF is “0” (interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction. @ STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. The output status of input output ports can be set to either output hold or high-impedance under software control STOP mode is started by the system control register 1, and STOP mode is released by STOP input pin (either level-sensitive or edge-sensitive can be selected). After the warming-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction. Reset release Instruction Instruction mode Interrupt Release input Single Clock Mode Transition Diagram Operating | Oscillation Peripheral Machine cycle mode circuit circuit time a Turning on [roma | osctaton | Operate | Operate pom | Turning off [ve [= | Figure 1-13. Operating mode transition diagram 3-09-17 2002-01-08

0: CPU core and peripherals remain active STOP mode start 1: €PU core and peripherals are halted 0: STOP pin input rising edge release | rem | Release method for STOP mode 1: STOP pin input “H" level release Port output control during STOP | 0: High-impedance Warming-up time at releasing 22" /fe WUT | mode 10: 3x2"%/fc 11: 2/fe Note 1: Always set bit 5 to “0”. Note 2: Bits 1, 0 in SYSCR1 is read in as undefined value when a read instruction is executed. Note 3: fc; High-frequency clock [Hz] * |; Don't care Note 4: When the STOP mode is started by specifying OUTEN = “O", the in internal input of port is fixed to “0” and the interrupt of the falling edge may be set. System Control Register 2 7 6 5 4 3 2 1 0 0: CPU, WDT operate Note 1: An internal reset is applied if XEN is cleared to “0”. Note 2: Always set bit 6, 5 to “0”. Note 3: WOT; Watchdog timer, * ; Don’tcare Note 4: Bits 3 to 0 in SYSCR2 are read in as “1” when a read instruction is executed. Figure 1-14. System control registers 1,2

1.8.4 Operating mode control

(1) STOP mode (STOP) STOP mode is controlled by the system control register 1 and the STOP pin input. The STOP pin is also used both as a port P43 and an INTS (external interrupt input 5) pin. The STOP mode is started by setting STOP (bit 7 in SYSCR1) to “1”. During STOP mode, the following status is maintained. @ High-frequency oscillations are turned off, and all internal operations are halted. @ The data memory (except for DBR), registers, PSW, and port output latches are all held in the status in effect before STOP mode was entered. The port output can select either output hold or high-impedance by setting OUTEN (bit 4 in SYSCR1). @ The divider of the timing generator is cleared to “0”. @® The program counter holds the address of the instruction after the following instruction which started the STOP mode. [for example, SET (SYSCR1)] STOP mode includes a level sensitive release mode and an edge-sensitive release mode, either of which can be selected with RELM (bit 6 in SYSCR1). Note: In STOP Mode changes in external interrupt signals may cause interrupt latches to be set to 1 and interrupt routines to be started immediately after exiting STOP Mode. Therefore be sure to enter STOP Mode only after disabling interrupts. Also, when enabling interrupts after exiting STOP Mode, be sure to first clear interrupt latches for interrupts not to be used. 3-09-18 2002-01-08

a. _Level-sensitive release mode (RELM = 1) In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. When the STOP pin input is high, executing an instruction which starts the STOP mode will not place in STOP mode but instead will immediately start the release sequence (WARM-up). Thus, to confirm that the STOP pin input is low. The following method can be used for confirmation: Using an external interrupt input INTS (INTS is a falling edge-sensitive input). Example: Starting STOP mode with an INTS interrupt. PINTS: TEST (P4).3 i To reject noise, the STOP mode does not start if JRS_ F, SINTS port P43 is at high. LD (SYSCR1),01000000B ; Sets up the level-sensitive release mode. SET (SYSCR1).7 ; Starts STOP mode LDW (IL), 1000011101010111B ; 1L11,5,3<—0 (clears interrupt latches) SINTS: —RETI STOP pin \\ 7 Vin \\ H t xoursin [III Cini : H NORMAL . STOP mode <- Warm-up -><—— NORMAL operation operation Confirm by program that \\ STOP mode is rel heh and start STOP mode. pininputis high. Figure 1-15. Level-sensitive release mode Note 1: After warm-up start, even if STOP pin input is low again, STOP mode does not restart. Note 2: When changing to the level-sensitive release mode from the edge-sensitive release mode, the release mode is not switched until a rising edge of the STOP pin input is detected. 3-09-19 2002-01-08

b. Edge-sensitive release mode (RELM = “0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is repeatedly executed at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high. Example: Starting STOP mode operation in the edge-sensitive release mode LD (SYSCR1), 000000008 ; OUTEN <0 (specifies high-impedance) Dl ; IMF<-0 SET (SYSCR1). STOP ; STOP <1 (activates STOP mode) LDW (IL), 1000011101010111B ; 1L11,5,3 <0 (clears interrupt latches) El >; IMFe1 y soe iL, ‘a _ \\ i ' H H Speation STOP mode —>}<- Warm-up ate So STOP made —— STOP mode started bythe program. STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 1-16. Edge-sensitive release Mode STOP mode is released by the following sequence: @® The oscillator is turned on. @ Awarming-up period is inserted to allow oscillation time to stabilize. During warm-up, all internal operations remain halted. Four different warming-up times can be selected with WUT (bits 3 and 2 in SYSCR1) as determined by the resonator characteristics. @ When the warming-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction. The start is made after the divider of the timing generator is cleared to “0”. Table 1-1. Warming-up time example [wut at te=4.19430amiiz [atie=amiz | 00 375 ms 196.6 ms o1 125 ms 65.5 ms 10 2.93 ms 1.54 ms "1 976.6 1s 512s Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore, the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warming-up time must be considered an approximate value. STOP mode can also be released by setting the RESET pin low, which immediately performs the normal reset operation. 3-09-20 2002-01-08

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Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower rate than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (hysteresis input). (2) IDLE mode (IDEL1) IDLE mode is controlled by the system control register 2 Y ‘ (SYSCR2) and maskable interrupts. The following NEanranen - by instruction status is maintained during IDLE mode. es @® Operation of the CPU and watchdog timer is halted. On-chip peripherals continue to operate. Y @ The data memory, CPU registers, PSW, and port <et > Yes. Reset output latches are all held in the status in effect before IDLE mode was entered. No @ The program counter holds the address of the instruction after the following instruction which <em> started IDLE mode. (Normal ) release mode Yes Example: Starting IDLE mode. No SET (SYSCR2).4 IDLE mode includes a normal release mode and an te Linterrupr release mode) interrupt release mode. Selection is made with the interrupt master enable flag (IMF). Releasing the IDLE mode returns to NORMAL. instruction which follows the IDLE mode start a. Normal release mode (IMF ="0") instruction IDLE mode is released by any interrupt source enabled by the individual interrupt enable flag Vv (EF) or an external interrupt 0 (INTO) request. Figure 1-18. IDLE mode Execution resumes with the instruction following the IDLE mode start instruction. The interrupt latches (IL) of the interrupt source used for release is required to be cleared to "0" by load instruction. b. Interrupt release mode (IMF = “1") IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (EF) or an external interrupt 0 (INTO) request. After the interrupt is processed, the execution resumes from the instruction following the instruction which started IDLE mode. IDLE mode can also be released by setting the RESET pin low, which immediately performs the reset operation. Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is 3-09-22 2002-01-08

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1.9 Interrupt Controller

The TMP87C409B/809B each have a total of 11 interrupt sources: 4 externals and 7 internals. Nested interrupt control with priorities is also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. Each interrupt vector is independent. The interrupt latch is set to “1” when an interrupt request is generated and requests the CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled and disabled by the program using the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priority order as determined by the hardware. Figure 1-20 shows the interrupt controller. Table 1-2. Interrupt sources Inte t_| Vector Tabl Fe | irat [nrwor wetcrngsimerintronn) | MME te rae || INTWDT (Watchdog timer interrupt) Ie FEA, Feswna [aro tera) —fwevreevsa | ay | mame | a | [ine [aTeT Cinwbwainernerand [uwaesr | a | rm | | ee ee Ce [rane [wre teemainnnn ——rnget | ts [ey] ow | 3-09-24 2002-01-08

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(1) Interrupt Latches (IL15 to IL2) Interrupt latches are provided for each source, except for a software interrupt. The latch is set to “1” when an interrupt request is generated, and requests the CPU to accept the interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt latches are initialized to “0” during reset. The interrupt latches are assigned to addresses 003C and 003DH in the SFR. Each latch can be cleared to “0” individually by an instruction; however, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used (Do not clear IL2 for a watchdog timer interrupt to “0"). Thus, interrupt requests can be canceled and initialized by the program. Note that interrupt latches cannot be directly set to “1” by any instruction. The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt requests by software is possible. Example 1: Clears interrupt latches LDW (IL), 1000110000111111B —; Ilg, ILg, IL Example 2: Reads interrupt latches LD WA, (IL) 7 Welly, ACILp Example 3: Tests an interrupt latch TEST (IL).6 ; Ilg=1then jump JR F, SSET (2) Interrupt Enable Register (EIR) The interrupt registers (EIR) enable and disable the acceptance of interrupts except for the pseudo non-maskable interrupts (software and watchdog timer interrupts). Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR; however, the pseudo non-maskable interrupts cannot be nested more than once at the same time. The EIR consists of an interrupt master enable flag (IMF) and individual interrupt enable flags (EF). These registers are assigned to addresses 003A} and 003By in the SFR, and can be read and written by an instruction (including read-modify-write instructions such as bit manipulation instructions). @ Interrupt Master Enable Flag (IMF) The interrupt master enable flag (IMF) enables and disables the acceptance of all interrupts. Clearing this flag to “0” disables the acceptance of all maskable interrupts. Setting to “1” enables the acceptance of interrupts. When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the acceptance of maskable interrupts. After execution of the interrupt service program, this flag is set to “1” by the maskable interrupt return instruction [RETI] to again enable the acceptance of interrupts. If an interrupt request has already occurred, interrupt service starts immediately after execution of the [RETI] instruction. Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (IMF = 1). Note that IMF remains “0” when cleared in the interrupt service program. The IMF is assigned to bit 0 at address 003Ay in the SFR, and can be read and written by an instruction. IMF is normally set and cleared by the [El] and [DI] instructions, and the IMF is initialized to “0” during reset. a SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 3-09-26 2002-01-08

® Individual Interrupt Enable Flags (EF15 to EF4) These flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0” disables acceptance. Example 1: Sets individual interrupt enable flags o ; IMFO LOW (EIRL), 1110100010100000B ; EFi5to 13, EF11, EF7, EFs<—1 Note: Do not set IMF El ; IMFe1 Example 2: Example of description in C unsignedint _ io (3AH) EIRL i /* 3AH: address for EIRL */ _DdI() H EIRL = 10100000B i EI) ; Interrupt Latches IL 1314 13 121 10S GS ILy (003Dy) IL, (003Cy) (Initial value: 00000000 000000) Interrupt Enable Registers EIR 1514 43 12 =O) 0g 8 8 rT EIR} (003By) EIR, (003Ay) (Initial value: 00000000 0000+**0) Note 1: Do not clear IL2 to “0” by an instruction. Note 2: Do not clear IL with read-modify-write instructions such as bit operations. Note 3: Before you set EF, be sure to clear IMF (to disable interrupt). Note4: * ; Don'tcare Note 5: Do not set IMF to 1 simultaneously with EF. Note 6: Donotset IMF to “1” during non-maskable interrupt service program. Figure 1-21. Interrupt Latch (IL) and Interrupt Enable Register (EIR) a eSeSeSSSeSeSSSSSSeeeeeeeeSSES 3-09-27 2002-01-08

1.9.1 Interrupt sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 machine cycles after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts or [RETN](pseudo non-maskable interrupts). Figure 1- 22 shows the timing chart of interrupt acceptance and interrupt return instruction. (1) Interrupt acceptance processing @® The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. @ The interrupt latch (IL) for the interrupt source accepted is cleared 0 “0”. @ The contents of the program counter and the program status word are saved (pushed) onto the stack. (pushed down in order of PSW, PCy, PC,). The contents of Stack Pointer is decreased by 3. @ The entry address of the interrupt service program is read from the vector table address corresponding to the interrupt source, and the entry address is loaded to the program counter. © The instruction stored at the entry address of the interrupt service program is executed. 1 machine cle t Interrupt service task ose ee ee | incervupt_t \\ i i signal H 7 4 H Interrupt__! a i : latch H | r t IME i \\ H H Hi i ‘ ! A‘ i H a SD) CD aD CD CD (TD (Te (TE) CS) TED CD ED CD ca : ED) CS Ee (CED, n Note 1:2; return address —_b; entryaddress___c ; address when the RET! instruction is stored ‘Note 2: The maximum response time from when an IL is set until an interrupt acceptance processing starts is 38/fe [5]. tt equals to setting the IL on the first machine cycle in 10 cycles instruction execution. Figure 1-22. Timing chart of interrupt acceptance and interrupt return instruction Example: Correspondence between vector tale address for INTTBT and the entry address of the interrupt service program. Vector table address Entry address tty [EE rao, PSR FFF3y F2y F204, 06, 3-09-28 2002-01-08

A maskable interrupt is not accepted until the IMF is set to “1” even if a maskable interrupt of higher priority than that of the current interrupt interrupt being serviced. When nested interrupt service is necessary, the IMF is set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. However, an acceptance of external interrupt 0 cannot be disabled by the EF, therefore, if disablement is necessary, either the external interrupt function must be disabled with the external interrupt control register (INTOEN) or interrupt processing must be avoided by the program. (When INTOEN =0, the interrupt latch IL3 is not set, therefore, the falling edge of the INTO pin input cannot be detected.) When INTOEN =0, the interrupt latch IL3 is not set, therefore, the falling edge of the INTO pin input cannot be detected. Example 1: Disables an external interrupt 0 using INTOEN: CLR (EINTCR). INTOEN 7 INTOEN<O Example 2: Disables the processing of external interrupt 0 under the software control (using bit 0 at address OOFOH as the interrupt processing disable switch): PINTO: TEST (OOFOH).O ; Returns without interrupt processing if (OOFOH)o = 1. JRS_T, SINTO RETI SINTO: Interrupt processing. : RETI VINTO: DW _ PINTO (2) General-purpose register save / restore During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save / restore the general-purpose registers: @_ General-purpose register save / restore by register bank changeover: General-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, bank 0 is used for the main task and banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. The switched bank is automatically restored by executing an interrupt return instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save the RBS. Example: Register Bank Changeover PINTxx: LD RBS, nj, Switches to bank n (1 4s at 8 MHz) ? Interrupt processing : RET Restores bank and Returns eee 3-09-29 2002-01-08

@ General-purpose register save / restore using push and pop instructions: To save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using push/pop instructions. Example: Register save using push and pop instructions PINTxx: PUSH WA ; Save WA register pair PUSH. He sseeneng — ¢ Save HL register pair L_Interrupt processing POP. HL ; Restore HL register pair POP WA ; Restore WA register pair RETI ; Return esseseeneeneen seseesseeneees sesneenseneeee sveestsseseeune AGOFESS (example) esoeeneeneenee in Senne | ecessseneeuse eeseeesesee eel OT 38H ovsesseeetnsee eeeneebnneenn seeectnseneene evststnenentaf 0139 eseeceeneseen eoesceath costa sesneeneeseese eveesesntnee] O13 esesessnsnseeeeee ee esseessnseeesnsn essesennesen ee] O13B Sioned ee eee ed sosnsenerensnf OFC oP ce Fa: a fet eee joseeensennaf O13D fee ae ese POH on on PSH essenseneened OT3E At acceptance of Atexecution of a push At execution of apop At execution of an interrupt an interrupt instruction of WA instruction of WA return instruction register register @ General-purpose registers save/restore using data transfer instruction: Data transfer instructions can be used to save only a specific general-purpose register during processing of a single interrupt. Example: Saving / Restoring registers by data memory transfer instructions. PINTxx: LD (GSAVA), A ; Save A register LD A, (GSAVA) ; Restore A register RETI ; Return Main task Main task Acceptance of Interrupt Agceptance Interrupt Bank m_ | interrupt service task ofinterrupt service task IW WN Switch to bank n by \\ | saving Pf [LD RBS, n] instruction \\ registers pcescetnsensts Restore bank | | m Interrupt return automatically by NS \\\\\\ Restoring interrupt return N \\\\esisers Interrupt return (a) Saving / Restoring by register bank changeover (b) Saving / Restoring using push/pop transfer instructions Figure 1-23. Saving / Restoring general-purpose registers 3-09-30 2002-01-08

(3) Interrupt return The interrupt return instructions perform the following operations. [RET!] Maskable interrupt return [RETN] Non-maskable interrupt return © The contents of the program counter and | © The contents of the program counter and the program status word are restored Program status word are restored from from the stack. ‘the stack. @ The stack pointer isincremented 3 times. | @ Thestack pointer is incremented 3 times. @ The interrupt master enable flag is set to | @ The interrupt master enable flag is set to “a “1" only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at “0” when so clear by an interrupt service program. interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service is performed but not the main task.

1.9.2 Software interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable interrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the [NOP] instruction. Note: Software interrupt generates during non-maskable interrupt processing to use SWI instruction for software break in a development tool. Use the [SWI] instruction only for detection of the address error of for debugging. @® Address Error Detection FF} is read if for some cause such as noise the CPU attempts to fetch an instruction from a non- existent memory address. Code FF is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FF to unused areas of the program memory. Address-trap-reset is generated for instruction fetch from RAM area (addresses 0040 to 013F}) or SFR area (0000 to 003F}). Note: The fetch data from addresses, BF80 to BFFFy for TMP87C409B/809B and TMP87P809 is not “FF”, because the outgoing test ROM is contained. @ Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. SSS 3-09-31 2002-01-08

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1.9.3 External interrupts

The TMP87C409B/8098 each have four external interrupt inputs. Two of these are equipped with digital noise rejection circuits(pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1, INT3 pin. The INTO / P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise rejection control and INTO / P10 pin function selection are performed by the external interrupt control register (EINTCR). Both edge detection of INT3 is controlled by the external interrupt 3 control register (INT3CR). Table 1-3. External interrupts souce | | fnconea lEnable conditions [sing | tating [both | Digital noise rejection circuit INTO | INTO IMF =1 — (hysteresis input) INTOEN=1 63/fc[s] are eliminated as noise. Pulses equal to or more than 48/fc [s] or 192/fc {s] are regarded as signals. int | int3 | P50(Tc3/cLz0) jueseruet[seseowrats=1 [=| For falling or rising edge, INT3W=0 pulses less than 7/fe [s} are cancelled as noise. Pulses INT3W=1 Is] are regarded as signals. Les [rors | passstor [wrest [= [| O [= [-tryteressinnwy | Note 1: The noise rejection function is also affected to detect the edge of timer / counter input (ICI, TC3 pin). Note2: The pulse width (both “H” and “L” level) for input to the INTO and INTS pins must be over 1 machine cycle. INTO/INTS input ee ee es ‘unt tintn > teye t t t Note: tcyc = 4/fc [s] at NORMAL, — + IDLE mode : ‘UNTL i ‘NTH Note 3: If a noiseless signal is input to the external interrupt pin in the NORMAL or IDLE. mode, the maximum time from the edge of input signal until the IL is set is as follows: @ _INT1 pin 49/f¢ [5] (at INTINC = 1), 193/fc [5] (at INTINC =0) @ INT3 pin 25/fc Is} Note 4: When INTOEN =0, the interrupt latch IL3 is not set even if the falling edge of INTO pin input is detected. Note5: When high-impedance is specified for port output in STOP mode, port input is forcibly fixed to low level internally. Thus, interrupt latches of external interrupt inputs except P43 (STOP / INTS) which are also used as ports may be set to “1”. To specify high-impedance for port output in STOP mode, first disable inteerupt service (IMF =0), activate stop mode. After releasing stop mode, clear interrupt latches using load instruction, then, enable interrupt service. Example: Activating stop mode LD (SYSCR1), 010000008 i OUTEN <0 (specifies high-impedance) DI 3 IMFe0 SET — (SYSCR1), STOP i STOP <1 (activates STOP mode) LOW (IL), 1000011101010111B —;_IL11, 5, 3<-0 (clears interrupt latches) fl : IMFe1 Note 6: When INT3W = 1, the edge of an interrupt can be detected by reading INT3R and INT3F (bits 6 and 5 in INT3CR). ee 3-09-32 2002-01-08

ce seiect 4 0: Pulses of less than 63/fc [5] are eliminated as noise + Pera sa cng TRU pin contigurati 0: P10 input/output port INTOEN | P10/INTO pin configuration 1: INTO pin (Port P10 should be set to an input mode.) INT3 ES sei, TC1ES | INT3, TC1, INT1 edge select £ eraege INTIS Falling edge Note: fc; High-frequency clock [Hz] *; Don’t care (oo2s,) Lwraw[wrae[mae] EE initial value: 000+ wees) INT3 sng edge detection fag _ | 0: Rsing edge non-detctes aead : ead 7 Fal . Note 1: _INT3R and INT3F are effective only in INT3W = 1. Note 2: _INT3R and INT3F are cleared to “0” when reading the INT3CR. Figure 1-24. External interrupt control register 3-09-33 2002-01-08

1.10 Watchdog Timer (WDT)

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either an internal reset or a non- maskable interrupt request. However, selection is possible only once after reset. After reset, the signal is initialised to the reset output. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. Note: The functions of the watchdog timer may not be fully realized due to disturbance noise, etc. Therefore, careful consideration is required in the designing stage.

1.10.1 Watchdog timer configuration

fom —»[ 5 Binary Counter Internal reset, fz" ——>| & | Clock Overflow WOT output fo2! GJ clear L

3 A > Interrupt request ino

Internal reset (L____ IO Writing Writing wort + | disable code | clear code WOTOUT Controller wou] f 0035, tf Watchdog Timer Control Registers Figure 1-25. Watchdog timer configuration

1.10.2 Watchdog timer control

Figure 1-26 shows the watchdog timer control registers. The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows. © Setting the detection time, selecting output, and clearing the binary counter. @ Repeatedly clearing the binary counter within the setting detection time. Note: The binary counter is cleared asynchronously with the source clock. Therefore, the detection time may be reduced to 3/4 of the set time depending on the timing at which the counter is cleared. If the CPU malfunction occurs for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTOUT = 1, an internal reset is generated. When WDTOUT = 0, a watchdog timer interrupt(INTWDT) is generated. SSSSSSSeSeSSseeeeeeeeSSSSSSSSSSSSSSSSSSSSSSSSSSee 3-09-34 2002-01-08

The watchdog timer temporarily stops counting in the STOP mode including warm-up or IDLE mode, and automatically restarts (continues counting) when the STOP / IDLE mode is released. Example: Sets the watchdog timer detection time to 221/fc[s] and resets the CPU malfunction. LD (WDTCR2), 4EH ; Clears the binary counters LD (WDTCR1), 00001101B =; WDTT<-10, WDTOUT<-1 oe LD (WDTCR2), 4EH ; Clears the binary counters Within 3/4 of): (always clear immediately after changing WDTT) time i LD (WDTCR2), 4EH ; Clears the binary counters Within 3/4 of : WDT detection i time i LD (WDTCR2), 4EH ; Clears the binary counters Watchdog Timer Control Register 1 road cane seo Devinn bre oa tO (00389) stata L VOT TERE] Miiavatue: seer 1000 O: Disable (tis necessary tow the able coe to wOTCR) 00: 2*/fc [5] - - 01: 22/fe Write- WDTT | Watchdog timer detection time | 19° Saige only 1: 2%/fe . 0: Interrupt request Note 1: WDTOUT cannot be set to “1” by program after clearing WDTOUT to “0”. Note2: fc; High-frequency clock[Hz] *; Don’t care Note 3: WDTCRI is a write-only register and must not be used with any of read-modify-write instructions. Note 4: Disable the watchdog timer or clear the counter just before switching to STOP mode. When the counters cleared just before switching to STOP mode, clear the counter again subsequently to releasing STOP mode. Note 5: When WDTOUT = 1, internal reset time is 12/fc [s]. Watchdog Timer Control Register 2 7.6 5 4 3 2 1 Oo . 4Ey: Watchdog timer binary counter clear (clear code) , worcr2 | Watchdog timer control code | a1. watchdog timer disable(disable code) Write- write register Others: Invalid only Note 1: The disable code is invalid unless written when WDTEN =0. Note 2: *; Don‘tcare Note 3: Since WDTCR2 is a write-only register, read-modify-write instructions (e.g., bit manipulating instructions such as SET or CLR and arithmetic instructions such as AND or OR) cannot be used for read/ write to this register. Note 4: To clear binary counter doesn’ initialize the source clock, therefore, it is recommended to clear binary counter within 3/4 of the detection period. Figure 1-26. Watchdog timer control registers (2) Watchdog Timer Enable The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1). WDTEN is initialized to “1” during reset, so the watchdog timer operates immediately after reset is released. SSS 3-09-35 2002-01-08

(3) Watchdog Timer Disable The watchdog timer is disabled by writing the disable code (B1})) to WDTCR2 after clearing WDTEN (bit 3 in WDTCR1) to “0”. The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTEN is cleared to “0”. During disabling the watchdog timer , the binary counters are cleared to “0”. Example: Disables watchdog timer LDW (WDTCR1), 0B101H ; WDTEN¢-0, WDTCR2<disable code Table 1-4. Watchdog timer detection time 00 4.194 or 1.048 10 262.1m i 65.5m

1.10.3 Watchdog timer interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the EIR. Ifa watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDOTOUT. Example: Watchdog timer interrupt setting up. LD SP, 013FH ; Sets the stack pointer LD (WDTCR1), 000010008 +=; ~WDTOUT<O

1.10.4 Watchdog timer reset

If the watchdog timer output becomes active, an internal reset is generated, which reset the internal hardware. The internal reset time is 12/fc [s] (1.5 «s at 8 MHz). When an internal reset is generated, the RESET pin remains “H” level. . 2c ts] : Efe? i Clock l l l | | l | (WoT = 115) Binary counter 1X2 X3X_0 Xt XX FX Overflow : INTWOT interrupt : Internal reset i writes 4 to WOTCR2 Figure 1-27. Watchdog timer interrupt /reset Note: Adequate care must be given when designing systems so as to eliminate disturbing noise. Otherwise the Watchdog Timer may not exhibit its full functionality. eeeeeSeSSSSSSSSSeSSsSSeeeeeeeSSSSSsSSSSSMMMMFFFsFSeee 3-09-36 2002-01-08

1.11 Reset Circuit

TMP87C409B/809B each have four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Figure 1-28 shows Reset Circuit, Table 1-5 shows on-chip hardware initialization by reset action. Table 1-5. On-chip hardware initialization by reset action Program counter (Po | GFFFF,)-(FFFE,) | Prescaler and Divider of Timing | oo | Register bank selector (RBS) 0 . Jump status flag GF) 1 Watchdog timer Frable Interrupt master enable flag (IMF) t) i Refer to VO port Output latches of input/output port | Refer Por Interrupt individual enable flags (EF) 0 utput latches of inputfoutput port | circuitry

1.11.1 External reset input

The RESET pin contains a hysteresis input with an internal pull-up resistor. When the RESET pin is held at “L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes “H” level, the reset operation is released and the program execution starts at the vector address stored at addresses FFFE to FFFFy. pVDD RESET iS ° O >—P > Resetinput Address trap detection System clock detection Figure 1-28. Reset circuit

1.11.2 Address-trap-reset

An address-trap-reset is one of fail-safe function that detects CPU malfunction such as endless looping caused by noise or the like. If the CPU attempts to fetch an instruction from RAM or SFR, an internal reset will be generated. The reset time is 12/fc (1.5 us at 8 MHz). Instruction (Reset release Ninstruction ataddressr execution ! { Address trap is occurred { ' Internal reset J | i Hi re ‘ 12/fe [s] ' Affcto16/fcls] | 16/fels] Note 1: ais an address in on-chip RAM or SFR. Note 2: During reset release, reset vector “r” is read out, and an instruction at address ris fetched and decoded. Figure 1-29. Address trap reset Note: If an undefined command or a SWI command in the address one before the address trap area is executed, then an address trap reset is applied immediately after the reception of the SWI interrupt is completed. 3-09-37 2002-01-08

1.11.3 Watchdog timer reset

Refer to Section “1.10 Watchdog Timer”.

1.11.4 System clock reset

Clearing XEN to “0” stops a system clock, and causes CPU to deadlock. This can be prevented by automatically generating a reset signal whenever XEN =0 is detected to continue the oscillation. Then internal reset is generated. The reset time is 12/fc [s] (1.5 “s at 8 MHz). 3-09-38 2002-01-08

1. | On-Chip Peripherals Functions

2.1 Special Function Register (SFR)

The TLCS-870 Series uses the memory mapped I/O system, and all peripheral contro! and data transfers are performed through the special function registers (SFR). The SFR are mapped to addresses 0000 to 003Fy. Figure 2-1 shows the TMP87C409B/809B SFR. Address Read Write Address Read Write

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2.2. VO Ports The TMP87C409B/809B have 4 ports, 22 pin input/output ports. @ P1port ; 8-bit/Oport (external interrupt input, timer/counter input/output, and divider output) @ P4port ; 4bit/O port (serial bus interface, external interrupt input) @ P5port ; 2-bit/Oport (timer/counter input/output, external interrupt input, oscillation stop detector output) @® P6port ; 8-bit/Oport (analog input, analog reference power supply) Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should either be held externally until read or reading should be performed several times before processing. Figure 2-2 shows input/output timing examples. External data is read from an I/O port in the $1 state of the read cycle during execution of the read instruction. This timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. Output data output changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle _,_ Fetchcycle Read cycle ht SO S1 S2 S3 SO $1 S2 S3 SO S1 S2 $3 execution cycle =o od (a) Input Timing Fetch cycle Fetch cycle , | Writecycle Pa fee IE |e VE SO S1 S2 $3 SO St $2 $3 SO SI S2 $3 Instruction an oo Output latch pulse ~... nO sone Dataoutput — Xt (b) Output timing Note: The positions of the read an write cycles may vary, depending on the instruction. Figure 2-2. Input/Output timing (Example) When reading an I/O port except programmable I/O ports, whether the pin input data or the output latch contents are read depends on the instructions, as shown below: (1) Instructions that read the output latch contents @ XCH fF, (src) © LD (pp).b,CF @® SET/CLR/CPL (src).b © ADD/ADDC/SUB/SUBB / AND /OR/XOR (src), n @ SET/CLR/CPL (pp).g @ (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) @® LD (src).b, CF (2) Instructions that read the pin input data Instructions other than the above (1) and (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (scr), (HL) SSS 3-09-40 2002-01-08

2.2.1 Port P1 (P17 to P10)

Port P1 is an 8-bit input/output port which can be configured as an input or an output in on-bit unit. Input/output mode is specified by the port P1 input/output control register (P1CR). During reset, the PICR is initialized to “0", which configures port P1 as an input. The P1 output latches are also initialized to 0". Port P11 is also used as an external interrupt input, a timer/counter input, and a divider output. When used as secondary function pin, the input pins should be set to the input mode, and the output pins should be set to the output mode and beforehand the output latch should be set to “1”. It is recommended that pins P11 and P12 should be used as external interrupt inputs, timer/counter input, or input ports. The interrupt latch is set at the rising or falling edge of the output when used as output ports. Pin 10 can be configured as either an input/output ports with INTOEN or an external interrupt input. During reset, pin P10 is configured as an input port. STOP ° OUTEN 4) .) Data input Po <¥ Data outpu [> 9] a TT Output late! Pi Control output Control input . Note: i=7to0 Pt PI7 | P16 : PIS ; P14; P13; P12; P11 : PIO (0001) PF EE pwe iter fants: into | (Initial value: 0000 0000) pee (FJ rit vlue: 0000 0000) picr | YOcontrol for port Pt 0: input mode Write- (Set for each bit individually) | 1: Output mode only Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port P1 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2; The PICR is a write-only register. It can not be operated by the read-modify instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.) Figure 2-3. Port 1and P1CR Example: Sets P17, P16 and P14 as output ports, P13 and P11 as input ports, and the others as function pins. Internal output data is “1” for the P17 and P14 pins, and “0” for the P16 pin. LD (EINTCR), 01000000B i INTOEN€-1 LD — (P1CR), 110100008 SSS 3-09-41 2002-01-08

2.2.2 Port P4 (P43 to P40)

Port P4 is a 4-bit input/output port, and is also used as a serial bus interface input/output, an external interrupt input and a STOP mode release signal input. High current output is available so LEDs can be driven directly. When used as an input port or a secondary function pin, the output latch should be set to “1”. The output latches are initialized to “1" during reset. Bits 7 to 4 are read in as “1” when read instruction is executed for the port P4. Control input CMP/MCMP/TEST/others Data input J << SET/CLR/CPLothers Data output {> 9] [> Pe [| Pai Output latch nite Note 1: *; Don't care Control output Note2: i=3t00 STOP 0 odin —d_) 7 6 5 4 3 2 1 ) P4 peeing cosepnse nee geet tee - - - peepee" pas? Pa? =: Pat | PAO (00044); : i i STOP : SDA : SCL : SCK a H i H i INTS | SO; SI: (initial value: | +e» 1111) Figure 2-4. Port P4 SSeS 3-09-42 2002-01-08

2.2.3 Port P5 (P51 to P50)

Port PS is a 2-bit general-purpose input/output port which can be configured as an input or an output in one-bit unit. High current output is available so LEDs can be driven directly. input/output mode is specified by the port P5 input/output control register (P5CR). During reset, the PS5CR is initialized to “0”, which configures port P5 as an input. The P5 output latches are also initialized to “0”. Port P5 is also used as a timer/counter input, an external interrupt input and a oscillation stop detector output. When used as secondary function pin, the input pins should be set to the input mode, and the output pins should be set to the output mode. When used as timer/counter input, the output latch should be set to “1”. STOP —[p OUTEN —4 » PSCRi ater 1d Data output [>| =i CJ psi Output latch Control output Note 1: *; Don’tcare Control input Note2: j=1t00 5 ) 7 6 5 4 3 2 1 0) Sc ee : Wb i i i i P31) P30 | initial value: s#¥# +400) i H i i i i PDO ; cLz0 PSCR sor ceeneneenl 5 La u 9 (00264) 2° Pepe ee Lo 7 (Initial value: ##** +#00) pscr | YO control for port PS 0: Input mode Write- (Set for each bit individually) | 1: Output mode only Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port P5 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2: The PSCR is a write-only register. It can not be operated by the read-modify instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.) Figure 2-5. PortP5 and P5CR

2.2.4 Port P6 (P67 to P60)

Port P6 is an 8-bit general-purpose input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as analog inputs and P67 can be configured as an analog reference power supply pin (VAREF) by setting SREF to “1” (bit 7 in SELREF). Input / output mode is specified by port P6 input/output control register (P6CR) and AINDS (bit 4 in ADCCR). During reset, P6CR is set to “0”, AINDS is set to "1", and port P6 is in input mode. During reset, the output latches of port P6 is initialized to “0”. P6CR is write-only register. When port P6 is not used as analog input, it can be used input / output port. However output instructions must not be performed to maintain the precision at using AD converter. When the input instruction is executed to port P6 during using AD converter, “0” is read into the pin that selects analog input, and “1” or “0” is read into the pin that does not select analog input, depending on the input level of pins. ee 3-09-43 2002-01-08

Analog input ) STOP > che | ~L AINDS —4 o san —L_) D> [) P6CRi ———— re Data input <I sy Data output [>| > ["] Psi ti=0t06)

9 VDD

Analog input ) STOP 0 AINDS —o o san 1) [ ) [_) P6CRi 9 by oO _ yt Data output: fo 2| > O—L] Pe7 (varer) 7 6 5 4 3 2 1 0 SREF Bi {0006,) for | Pee: pes i Poa | Pas 7 Pez 7 Pet? Poo | AINZ, | AING ; AINS : AINA : AIN AN | A i 0 | initial value: 0000 0000) P6CR 7 6 5 4 3 2 1 0 (009 (rt vatue: on00 onc) pecr | VO control for port P6 0: Input mode Write- (Set for each bit individually) | 1: Output mode _ only Note: Used analog input pins must be configured as input mode. PG7/VAREF select register SELREF 7 6 5 4 3 2 1 oO (002) CoRR peepee bpelengtons ital values Onan ooo) rer | 0: Internal VDD Write- 1: External level P67 only Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port P6 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2: The P6CR and SELREF are a write-only registers. They can not be operated by the read-modify instruction (Bit manipulation instructions of SET, CLR, ete. and Arithmetic instructions of AND, OR, etc.) Figure 2-6. Port P6, P6CR and SELREF Example: — The lower 4-bit of Port P6 is set to an output port and the others are set to an input port. LD (P6CR), OFH + P6CRe-00001111 eee 3-09-44 2002-01-08

2.3. Time Base Timer (TBT) The time-base timer is used to generate the base time for key scan and dynamic display processing. For this purpose, it generates a time-base timer interrupt (INTTBT) at predetermined intervals. This interrupt is generated beginning with the first falling edge of the source clock (the timing generator’s divider output selected by TBTCK) after the time-base timer is enabled. Note that since the divider cannot be cleared by a program, the first interrupt only may occur earlier than the set interrupt period. (See Figure 2-7 (b)) When selecting the interrupt frequency, make sure the time-base timer is disabled. (Do not change the selected interrupt frequency when disabling the active timer either.) However, you can select the interrupt frequency simultaneously when enabling the timer.

0223 Source

2?! ° clock /2'6 + fu2"4 v | [Falling fat s edge Source clock | J l J fo2" a | [detector ‘ : t INTTBT i H : faa"? Ps ! fen? LD request, TBTEN ; SE 3 hE A H TaTCK TBTEN INTTBT ! I hl TF ; - TTC! ; Enable T3T Interrupt period Time Base Timer Control Register (2) Configuration _ (b)_ Time Base Timer Interrupt Figure 2-7. Time base timer Example: _ Sets the time base timer frequency to fc/2'® [Hz] and enables an INTTBT interrupt. LD — (TBTCR), 00001010B SET (EIRL).6 7,6 S 4 3 2 1 ~0 (ose, Lowen] evgeo To [rere] rerex, J (nti value: 0+40 o+se) Time base timer 0: Disable enable/disable 1: Enable 000: fe/2?? [Hz] 001: fo/2?" . 010: fe/2'6 Write- Time base timer interrupt | 011: f2"4 only TeTCK frequency select 100: fy2'? 101: fu2"? 110: fa2"" 111: £29 Note 1: fc; clock [Hz], * ; Don't care Note 2: The fourth bit in TBTCR must be to “0”. Note 3: TBTCR are write-only registers, which cannot access any of in read-modify-write instructions such as bit operate, etc. Figure 2-8. Time base timer control register Table 2-1. Time base timer interrupt frequency [Hz] NORMAL, IDLE mode (at fc = 8 MHz) 000 0.95 001 3.81 o10 122.07 om 488.28 100 976.56 101 1953.12 110 3906.25 dit 15625 SSeS 3-09-45 2002-01-08

a SSSSSSSSSSSSSSSeeeeeseseSSSSSSSSSSSS ee

2.4 Divider Output (DVO)

A50% duty pulse can be output using the divider output circuit, which is useful for piezo-electric buzzer drive. Divider output is from pin P13 (DVO). The P13 output latch should be set to “1” and then the P13 should be configured as an output mode. 7 6 5S 4 3 2 1 ~O Goose) Lxoenlovgee To Towem [core] nitiatvatue: +40 oven) 00: faz [Hz] Divider output (BVO pin) 01: fo2' DVOCK | frequency selection 10: fo2"? 11: fa2"0 Note 1: fc; High-frequency clock [Hz], * ; Don’t care Note 2: The divider output frequency should be selected with divider output disabled. (The divider output frequency should not also be changed when divider changed from enabled state to disabled state.) Note 3: TBTCR are write-only registers. which cannot access any of in read-modify-write instructions such as bit operate, etc. Figure 2-9. Divider output control register Example: 1 kHz pulse output (at fc = 8 MHz) SET (P1).3 ; P13 output latch <1 LD (P1CR),00001000B ; Configures P13 as an output mode LD (TBTCR), 10000000B ; DVOENe-1, DVOCK<-00 Table 2-2. Frequency of divider output [kHz] Ce 00 0.512 0.976 01 1.024 1.953 10 2.048 3.906 "1 4.096 7.812 Outputlatch Output mode (P1CRs) Output data {o a] Dai) Selector 4 fo2'3 a fo2"1 Y is a | — fo210 Ds P13 output latch J J Dvock DVOEN DVOEN — io: | Divider output control register BVO pin —— (a) Configuration (b) Timing Chart Figure 2-10. Divider output eS 3-09-46 2002-01-08

2.5 16-bit Timer/Counter 1 (TC1) The TMP87C409B/809B each have a multi-function 16-bit timer/counter (TC1).

2.5.1 Configuration

3 ° Tetpin O rN Let Tp V fo2" A S$ INTTC1

2 Comparator interrupt

Timer/counter 1 control register 16-bit timer register 1 Figure 2-11. Timer/Counter 1

2.5.2 Control

The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and a 16-bit timer register (TREG1). Reset does not affect TREG1. TREG! SE SO CA oe STC TEST [010 7 6 5 4.3 2 1 C) Write-only Te1cr ae et CSC ' ; (0014p) ba sndecnrteerineeree laces guns {initial value: +0 0000) 00: Internal clock fe/2"" . 01: Internal clock f</2” TCICK | Timer/counter 1 source clock select |'19: internal clock fe/2? Write: 11: External clock (TC1 pin input) only . 0: Stop and counter clear Note 1: fc; High-frequency clock [Hz], *; Don’t care Note 2: Always write “0” to bits 0, 1, 5, Gand 7 in TCICR. Note 3: Writing to the low-byte of timer register (TREG1)), the comparison is inhibited until the high-byte (TREG1,,) is written. After writing to the high-byte, the comparison of 1 machine cycle (during instruction execution) is ignored. Note 4: Set the mode, the source clock and the edge (TC1ES) when the TC! stops (TC1S = 0). Note 5: Values to be loaded to the timer register must satisfy the following condition. TREG1>O Note 6: TCICR and TREG1 are write-only registers, which cannot access any of in read-modify-write instructions such as bit operate, etc. Figure 2-12. Timer register 1 and TC1 control register 3-09-47 2002-01-08

2.5.3 Function

Timer/counter 1 has two operating modes: timer mode and event counter mode. (1) Timer Mode In this mode, counting up is performed using the internal clock. The contents of TREG1 are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to"0". Counting up resumes after the counter is cleared. Table 2-3. Timer/counter 1 source clock (Internal clock) fo23[Hz] 1s 65.5 ms fo” 16 4s 1.0 5 fo2" 256 4s 16.7 s Example: Sets the timer mode with source clock fv/2"[Hz] and generates an interrupt 1s. later (at fc = 8 MHz). LD — (TC1CR),00000000B ; Sets the TC1 mode and source clock LDW (TREG1), OF42H j Sets the timer register (1s +2"/fc = F42}) SET (EIRL).EF4 ; Enable INTTC1 El LD (TC1CR),000100008 ; Starts TC1 Command start Source clock { l | i i Up-counter 0 Ci X2 X 3X4) <=), WAX = X2X2KX«Xs XX2X | tre! a H ‘Match Counter INTTC1 interrupt i detect clear Figure 2-13. Timer mode timing chart (2) Event Counter Mode In this mode, events are counted on the edge of the TC1 pin input. Either the rising or falling edge can be selected with TC1ES in EINTCR. The contents of TREG1 are compared with the contents of the up- counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. The maximum applied frequency is fc/2* [Hz] in NORMAL or IDLE mode. Two or more machine cycles are required for both the “H” and “L” levels of the pulse width. Command start ninn_n meoo4esam TC1 pin input H Up-counter 0 X+X_2 X } Ct XXX) 2 Test Co Hl Match Counter INTTC1 interrupt Hi detect clear Figure 2-14. Event counter mode timing chart (TC1ES = 1) SSS 3-09-48 2002-01-08

2.6 8-Bit Timer/Counter 3 (TC3)

2.6.1 Configuration

Edge Capture — ry) interrupt} Teas +] >0 s Clear reapin Dy —p a iD fea Ay Source clock Overflow foam lo 2 i) (re Match Tack capture 7 DS =< Te3s} — = scaP 8-bit Timer Register 3A, 38 i Timer/Counter 3 Control Register Figure 2-15. Timer/Counter 3

2.6.2 Control

TREG3A 7.6 5 4 3 2 1 ~«0 (00184) ReadWrite (0019) Read-only ee a oe a rr) team _ | Timer/counter 3 0: Timer/event counter operation mode set 1: Capture - 00: Internal clock f/2"? [Hz] teack | Timer/counter 3 01: Internal clock fo/2"? source clock select 10: Internal clock f/2” Write- 11:_ External clock (TC3 pin input) only Timer/counter 3 0: Stop & clear Oo = Note 1: fc; High-frequency clock [Hz] * ; Don't care Note 2: Set the mode, the source clock and the edge selection (INT3ES) when the TC3 stops (TC3S = 0). Note 3: Values to be loaded into timer register 3A must satisfy the following condition. TREG3A > 0(in the timer/event counter mode) Note 4: Software capture can be used in only timer and event counter modes. Note 5: TC3CRis a write-only register and must not be used with any of read-modify-write instructions. Figure 2-16. Timer register 3A/3B and TC3 control register See 3-09-49 2002-01-08

The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TREG3A and TREG3B). Reset does not affect these timer registers.

2.6.3 Function

The timer/counter 3 has three operating modes: timer, event counter, and capture mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of TREG3A are compared with the contents of up-counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up-counter is cleared. Counting up resumes after the up-counter is cleared. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to “1". SCAP is automatically cleared after capturing. Table 2-4. Source Clock (Internal Clock) for Timer Counter 3 [poms oiemeie | tevewm | treme —_| fo2” [Hz] 512 ys fo2" 128 ys fer2? 16 4s (2) Event Counter Mode In this mode, the TC3 pin input pulses are used for counting up. Either the rising or falling edge can be selected with INT3ES (bit 3 in EINTCR). Both edges can not be used. The contents of TREG3A are compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is generated and the counter is cleared. The maximum applied frequency is fe/24 [Hz] in the NORMAL or IDLE mode. Two or more machine cycles are required for both the “H” and “L" levels of the pulse width. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to “1”. SCAP is automatically cleared after capturing. Example: Generates an interrupt every 0.5 s, inputing 50Hz pulses to the TC3 pin. LD — (TC3CR), 00001100 ; Sets TC3 mode, source clock LD (TREG3A), 19H ; 0.5s+1/50=25=194 LD (TC3CR) , 000111008 ; Start TC3 3-09-50 2002-01-08

(3) Capture Mode The pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals, etc. The counter is free running by the internal clock. On the rising (falling) edge of the TC3 pin input, the current contents of counter is loaded into TREG3A, then the up-counter is cleared and an INTTC3 interrupt is generated. On the falling (rising) edge of the TC3 pin input, the current contents of the counter is loaded into the TREG3B. In this case, counting continues. At the next rising (falling) edge of the TC3 pin input, the current contents of counter are loaded into TREG3A, then the counter is cleared again and an interrupt is generated. If the counter overflows before the edge is detected, FF} is set to the TREG3A and an overflow interrupt (INTTC3) is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the TREG3A value is FFy. Also, after an interrupt (capture to TREG3A, or overflow detection) is generated, capture and overflow detection are halted until TREG3A has been read out; however, the counter continues. Source clock TLL LLL LILI UL Up-counter 2 KKK KKK Ke KKK X 2X XX EKA LX 2X3) TC3 pin input i Hi pE—— ERY TREG3A CD aEcan a a a j Capture {Capture 1 Overflow INTTC3 interrupt a 9 A he » DO Reading TREG3A J I i. Figure 2-17. Timing chart for capture mode (INT3ES = 0) 3-09-51 2002-01-08

TOSHIBA , TMP87C409B/809B 2.7 8-bit Timer/Counter (TC4)

2.7.1 Configuration

TCAs [>< ue U . Clear TC4pin Ep>/D | Source lock Overflow

2 Timer F/F 4

Trea Tcas | Tcam Ra [) } >> toasle pin 2p 2. > set aHt>o—O > clear Y Timer/Counter 4 Control Register 8-bit Timer Register 4 TeaM=11 cf afi 2+ Note: MPX; Multiplexer CMP: Comparator INTTC4 TC4M, TFFA interrupt Figure 2-18. Timer/Counter 4

2.7.2 Control

The timer/counter 4 is controlled by a timer/counter 4 control register (TCACR) and an 8-bit timer register 4(TREG4). Reset does not affect TREG4. res. 7 6 5 4 3 2 «1 «0 (001839 Write-only 7 6 5 4 3 2 1 0 ToacR Tra | "0" [Teas] TC4CK TcaM Initial value: 00¢0 0000) (001C,,) is AC 4 (Initial value: 00s )) 00: Timer mode a 01: Reserved TCAM | TC4 operating mode select 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode 00: Internal clock fo/2" [Hz] 01: Internal clock fo/2” TC4CK | TC4 source clock select 10: Internal clockfe/2? Write- 11: External clack (TCA pin input) only 0: Stop & clear 00: Clear . 01: Toggle TRF Timer F/F 4 control 10: Set 11: - (Note 3) Note 1: fe: High-frequency clock [Hz]. *: Don’t care Note 2: Set the operating mode, the source clock selection, the timer FIF 4 control and the edge selection (INT4ES) when the TC4 stops (TC4S =0). Note 3: TFF4 must be set to “11” in the timer and event counter modes. Note 4: Values to be loaded to the timer register must satisfy the following condition. TREG4>0 Note 5: TC4CR and TREG4 are write-only registers and must not be used with any of read-modify-write instructions. Figure 2-19. Timer register 4 and TC4 control register 3-09-52 2002-01-08

2.7.3 Function

The timer/counter 4 has four operating modes: timer, event counter, programmable divider output, and PWM output mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of TREG4 are compared with the contents of up-counter. If a match is found, a timer/counter 4 interrupt (INTTC4) is generated and the up-counter is cleared to “0”. Counting up resumes after the up- counter is cleared. Table 2-5. Source clock (Internal clock) for timer/counter 4 [worwaLio.emede | fexawne | feaemne | fo2" [Hz] 256 ys 65.3 ms fod” 16 ys 4.1 ms fd2? 1s 255 us (2) Event Counter Mode In this mode, the TC4 pin input (external clock) pulse is used for counting up. The contents of TREG4 are compared with the contents of the up-counter. If a match is found, an INTTC4 interrupt is generated and the counter is cleared. The maximum applied frequency is fe/2* [Hz] in NORMAL or IDLE mode. Two or more machine cycles are required for both the high and low levels of the pulse width. (3) Programmable Divider Output (PDO) Mode The internal clock is used for counting up. The contents of TREG4 are compared with the contents of the up-counter. Timer F/F 4 output is toggled and the counter is cleared each time a match is found. Timer F/F 4 output is inverted and output to the PDO (P51) pin. This mode can be used for 50 % duty pulse output. Timer F/F 4 can be initialized by program, and it is initialized to “0” during reset. An INTTC4 interrupt is generated each time the PDO output is toggled. Example: Output a 1024 Hz pulse (at fc = 4.194304 MHz) SET (P5). 1 ; P51 output latch —1 LD (P5CR), 00000010 ; Sets P51 (output mode) LD (TREG4), 10H i (11024 = 27/fc) +2 = 104, LD (TCACR), 00010010B ; StartsTC4 Internal clock Wh l LAL TELS LILI Up-counter DOG OX X 2 Ke KKK XK 2 Xi KKK IX 2K KKK! TREGA Coop mated \\ Timer F/F 4 H i i i PDO pin output | | INTTC4 interrupt IL il il J Figure 2-20. Timing chart for PDO mode 3-09-53 2002-01-08

(4) Pulse Width Modulation (PWM) Output Mode PWM output with a resolution of 8 bits is possible. The internal clock is used for counting up. The contents of TREG4 are compared with the contents of up-counter. If a match is found, the timer F/F 4 output is toggled. The counter continues counting. And, when an overflow occurs, the timer F/F4 output is again toggled and the counter is cleared. Timer F/F 4 output is inverted and output to the PWM (P51) pin. An INTTC4 interrupt is generated when an overflow occurs. TREG4 is configured a 2-stage shift register and, during output, will not switch until one output cycle is completed even if TREG4 is overwritten; therefore, output can be altered continuously. Also, the first time, TREG4 is shifted by setting TC4S (bit 4 in TC4CR) to “1” after data are loaded to TREG4. Note: Do not overwrite TREG4 only when an INTTC4 interrupt is generated. Usually, TREG4 is overwritten in the routine of INTTC4 interrupt service. Internal clock | | J | J | l | l J | J | J Up-counter XOX XK XX OX XX XK XX OX EX XX oY aio A TREGA Ce SS DC, DC wd ovarton\\ \\ Timer F/F 4 H i H t H i i i i i PWM pin l | 1 INTTC4 interrupt Figure 2-21. Timing chart for PWM mode Table 2-6. PWM output mode [—soresnk | eotion [Non tn fy2" [Hz] 256 ys 65.5 ms fa? 16 ys 4.1 ms fo2 1s 256 ys 3-09-54 2002-01-08

2.8 Serial Bus Interface (SBI-ver. B) The TMP87C409B/809B each have a 1-channel serial bus interface which employs a clocked-synchronous 8-bit serial bus interface and an I?C bus. (a bus system by philips) The serial bus interface is connected to an external device through P42 (SDA) and P41 (SCL) in the I?¢ bus mode; and through P40 (SCK), P42 (SO), and P41 (SI) in the clocked-synchronous 8-bit SIO mode. The serial bus interface pins are also used as the P4 port. When used for serial bus interface pins, set the P4 output latches of these pins to “1”. When not used as serial bus interface pins, the P4 port is used as a normal I/O port.

2.8.1 Configuration

7 $C , —— SK SiO cieck Input’ HO] p40 input/ HO] P40 Control output (SCK) Control [pee slo so O) paz Tronafr f patacontrol|, dg 050) Control PC bus a Clock Syne. Greuit | : | “sc Control Canceller shift Pebus ea (Scusi) I — —: SBICR2/ SBI Control Register 2/12C bus SBI Data ‘SBI Control Register 1 SBI Status Register Address Register Buffer Register Figure 2-22. Serial bus interface (SBi-ver. B)

2.8.2 Serial bus interface (SBI-ver. B) control The following registers are used for control and operation status monitoring when using the serial bus interface (SBl-ver. B). © Serial bus interface control register 1 (SBICR1) © Serial bus interface control register 2 (SBICR2) © Serial bus interface data buffer register (SBIDBR) @ °C bus address register (I2CAR) © Serial bus interface status register (SBISR) The above registers differ depending on a mode to be used. Refer to Section “2.8.4 I2C bus Mode Control” and “2.8.6 Clocked-synchronous 8-bit SIO Mode Control”.

2.8.3 The data formats in the I2C bus mode

The data formats in the I?C bus mode are shown below. (a) Addressing format 8 bits 1 |<—1 to 8 bits —>] 1 |<—1 tos bits 1 A A Slave address ¢ ¢ K K 1 tormore (b) Addressing format (with restart) RIA A RIA Slave address | /|c c te K K Wik. (c) Free data format |<—s bits 1|<—1 to8 bits 1/<—1 to8 bits 1 lA A s c c K K, ~_—1 1ormore Note: _S: Start condition RAW: Direction bit ACK: Acknowledge bit P: Stop condition Figure 2-23. Data format at IC bus mode 3-09-56 2002-01-08

2.8.4 I2C bus Mode Control

The following registers are used for control the serial bus interface (SBI-ver. B) and monitor the operation status in the I?C bus mode. Serial Bus Interface Control Register 1 SBICRI 7 6 5S 4 3 2 1 0 (oo) [sc , [ack was scx, _] —_tinitiatvatue: 0000 000) [ _ack=0 ACK=1 b N b Be | Meaeec [eis | MGT T wits | 000 8 8 9 8 001 1 1 2 1 F Write BC | Number of transferred bits 010 2 2 3 2 ony on 3 3 4 3 y 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 11 7 7 8 7 0: Not generate clock pulse for acknowledge sianal (in master mode) / Not count clock pulse for an acknowledge signal (in slave mode) Read/ ACK | Acknowledge mode specification 1: Generate clock pulse for acknowledge signal (in Write master mode) / Count clock pulse for acknowledge signal (in slave mode) “tiate ai Oo: = Read/ SWRST | initiate a internal of SBI 1:_Initialized (Clearing “0” after initialized) 000: 200.0kHz 001: 111.1 kHz 010: 58.8kHz , . O11: 30.3kHz at fc= 8 MHz (Output on SCL pin) | Write- SCK | Serial clock selection 100: 188kHe only 101: 7.75kHz 110: 3.89kHz 111: _ reserved Note 1: fc; high-frequency clock [Hz], * ; Don’t care Note 2: Set the BC to “000” before switching to a clock-synchronous 8-bit SIO bus mode. Note 3: SBICR1 has write-only register bits, which cannot access any of in read-modify-write instructions such as bit operate, etc. Note4: +; Don’tcare Serial Bus Interface Data Buffer Register SBIDBR Fr ; 7 Note 1: When writing transmitted data, start from the MSB (bit7). Note 2: Cannot read the data which was written into SBIDBR, since a write data buffer and a read data buffer are independent in SBIDBR. Therefore, cannot access it any of in read-modify-write instructions such as bit operate, etc. Note 3: The data which was written into SBIDBR is cleared to “0” when INTSBI is generated. 12C bus Address Register 7 6 5 4 3 2 «1 ~O 12CAR Slave address Als (00224) | sas | sas | saa | sa3 | saz lsat Isao (initial value: 0000 0000) a_ | TMP87C4098/8098 slave address selection Write ‘ais | Address recognition mode (0: Slave address recognition only specification 1: Nonslave address recognition Note: I2CARisa write-only register, which cannot access any of in read-modify-write instructions such as bit operate, etc. Figure 2-24. Serial bus interface control register 1/serial bus interface data buffer register/ °C bus address register in the I?C bus mode 3-09-57 2002-01-08

Serial Bus Interface Control Register 2 ‘SBICR2 7 6 5 4 3 2 1 o) (00234) [st | Tax | 88 “or i “ont (initial value: 0001 00¢#) Or OS MsT | Master/slave selection 0: Slave 1: Master TRX | Transmitter/receiver selection lo: Receiver 1: Transmitter BB | Start/stop generation (0: Generate the stop condition when the MST, TRX, and PINare "1". Write- 1: Generate the start condition when the MST, TRX, and | “gniy PIN are “1". Cancel interrupt service request 0: - (cannot be cleared to “0") 1: Cancel interrupt service request (00: Port mode (serial bus interface output disable) Serial bus interface operating mode —_|01: SIO mode selection 10: PC bus mode 11; Reserved Note 1: *; Don’tcare Note 2: Switch a mode to port mode after confirming that the bus is free. Note 3: Switch a mode to !2Cbus mode after confirming that input signals via port are “H” level Note 4: SBICR2 has write-only register bits, which cannot access any of in read-modify-write instructions such as bit operate, etc. Note 5: Write “0” to bit 1, 0 in the SBICR2. Serial Bus Interface Status Register 7 6 5S 4 3 2 «1 +0 aaisn [mst [tex | ee [pin [ At [Aas [Avo] tre | (initiot vatue: 0001 0000) MST | Master/slave status monitor 0: Slave 1: Master TRX | Transmitter/receiver status monitor 0: Receiver 1: Transmitter BB | [2C bus status monitor 0: Bus free 4: Bus busy Interrupt service request status 0: INTSBI occurs monitor 1: INTSBI does not occur Read- ‘AL | Arbitration loss detection monitor _ | 0: Arbitration loss undetected only 1: Arbitration loss detected AAS | Slave address match detection monitor | 0: Slave address unmatch or “GENERAL CALL” undetected 1: Slave address match or “GENERAL CALL“ detected ADO | “GENERALCALL" detection monitor | 0: “GENERAL CALL” undetected 1: “GENERAL CALL" detected LRB | Last received bit monitor 0: Last received bit “0” 1: Last received bit “1” Figure 2-25. Serial bus interface control register 2/serial bus interface status register in the I? bus mode 3-09-58 2002-01-08

(1) Acknowledge mode specification Set the ACK (bit 4 in SBICR1) to “1” for operation in the acknowledge mode. The TMP87C409B/809B generate an additional clock pulse for an acknowledge signal when operating in the master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the “L” level in order to generate the acknowledge signal. Reset the ACK for operation in the non-acknowledge mode. The TMP87C409B/809B don’t generate a clock pulse for the acknowledge signal when operating in the master mode. In the acknowledge mode, the TMP87C409B/809B count a clock pulse for the acknowledge signal when operating in the slave mode. During the clock pulse, when the received slave address is the same as the value set at the I2CAR or when a GENERAL CALL is received, the SDA pin is set to the “L” level in order to generate the acknowledge signal. In the transmitter mode during the clock pulse cycle after matching the slave addresses or receiving a GENERAL CALL, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the “L” level in order to generate the acknowledge signal. In non-acknowledge mode, the TMP87C409B/809B don’t count a clock pulse for the acknowledge signal when operating in the slave mode. (2) Number of transfer bits The BC (bits 7 to 5 in the SBICR1) is used to select a number of bits for next transmitting and receiving data. Since the BC is cleared to “000” as a start condition, a slave address and direction bit transmissions are executed in 8 bits. Other than these, the BC retains a specified value. (3) Serial clock a. Clock source The SCK (bits 2 to 0 in the SBICR1) is used to select a maximum transfer frequency outputed on the SCL pin in the master mode. In both master mode and slave mode, a pulse width of at least 4 machine cycles is require for both “H" and “L" levels. SCK (bits2 to 0 in the SBICR1) trow=2"/fc 000 4 thigh = 2"/fe + Bifc oo é fel = tow +t on 7 (tLow + tHiGH) 100 8 101 9 Note: fc; high-frequency clock 110 10 Figure 2-26. Clock source 3-09-59 2002-01-08

b.Clock synchronization In the I2¢ bus mode, in order to drive a bus with a wired-AND, a master device which pulls down a clock line to “L” level, in the first place, invalidate a clock pulse of another master device which generates a “H“ level clock pulse. The master device with a “H” level clock pulse needs to detect the situation and implement the following procedure. The TMP87C409B/809B have a clock synchronization function for normal data transfer even when more than one master exists on a bus. The example explains clock synchronization procedures when two masters simultaneously exist on a bus. Wait counting “H” level width of a clock pulse . i i ! Start counting “H” level width of a clock pulse H i Hi SCL pin (Master 1) { A Counter start ! " {Reset a counter of “H* level | SCL pin (Master 2) ! width of a clock pulse } | Counter reset SCL (Bus) fi a b G Figure 2-27. Clock synchronization As Master 1 pulls down the SCL pin to the “L” level at point “a”, the SCL line of the bus becomes the “L" level. After detecting this situation, Master 2 resets counting a clock pulse in the “H” level and sets the SCL pin to the “L” level. Master 1 finishes counting a clock pulse in the “L” level at point “b” and sets the SCL pin to the “H” level. Since Master 2 holds the SCL line of the bus at the “L” level, Master 1 waits for counting a clock pulse in the “H” level. After Master 2 sets a clock pulse to the “H" level at point “c” and detects the SCL line of the bus at the “H” level, Master 1 starts counting a clock pulse in the “H™ level. The clock pulse on the bus is determined by the master device with the shortest “H™ level period and the master device with the longest “L” level period from among those master devices connected to the bus. (4) Slave address and Address recognition mode specification When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the ALS (bit 0 in 12CAR) to “0”, and set the SA (bits 7 to 1 in I2CAR) to the slave address. When the serial bus interface circuit is used with a free data format not to recognize the slave address, set the ALS to “1”. With a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (5) Master/slave selection Set the MST (bit 7 in the SBICR2) to “1” for operating the TMP87C409B/809B as a masterdevice. Reset the MST to “0” for operation as a slave device. The MST is cleared to “0” by the hardware after a stop condition on a bus is detected or arbitration lost is detected. 3-09-60 2002-01-08

Note: Whenastop condition is generated, a time to rise the SCL line should not exceed tr = 2n/fc - 3.5 x4/fc (s). (n depends on the SCK) If the rising time of the SCL line exceeds the above value, there is a probability that a stop condition is not started normally. [sce nT etttaxte=amrey | irittax,tenamray | [000 oss 050s | A E [ow as ed [ona a [tor ess Tas [toto 126.25 ys 252.5 ys | fc; High-frequency clock [Hz] The bus condition can be indicated by reading the contents of the BB (bit 5 in the SBISR). The BB is set to "1" when a start condition on a bus is detected,and is cleared to “0” when a stop condition is detected on a bus. (8) Interrupt service request cancel In the master mode, a serial bus interface interrupt request (INTSBI) occurs after the number of clocks which is specified by the BC and ACK has been transmitted. In the slave mode, when the received slave address is the same as the value set at the I2CAR, after outputting the acknowledge signal when a GENERAL CALL is received, or when data transfer is complete after matching the slave addresses or receiving a GENERAL CALL, an INTSBI interrupt request occurs. When a serial bus interface interrupt request occurs, the PIN (bit 4 in SBISR) is cleared to “0”. During the time that the PIN is “0”, the SCL pin is pulled down to the “L” level. Either writing / reading data to / from the SBIDBR sets the PIN to “1”. The time from the PIN being set to “1” until the SCL pin is released takes tow. Although the PIN (bit 4 in SBICR2) can be set to “1” by the program, the PIN is not set to “0” when “0” is written. (9) Serial bus interface operating mode The SBIM (bits 3 , 2 in SBICR2) is used to specify the serial bus interface operation mode. Set the SBIM to “10” after confirming that the serial bus interface pin is set to “H” level when used in the |2C bus mode. Switch a mode to port after making sure that a bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus in the I2C bus mode, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data. Data on the SDA line is used for bus arbitration of the I2C bus. The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus. Master 1 and Master 2 output the same data until point “a”. After Master 1 outputs “1” and Master 2, “0”, the SDA line of the bus is wired AND and the SDA line is pulled down to the “L” level by Master 2. When the SCL line of the bus is pulled up at point “b”, the slave device reads data on the SDA line, that is, data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is called “arbitration lost”. A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word. 3-09-62 2002-01-08

(12) GENERAL CALL detection monitor The ADO (bit 1 in SBISR) is set to “1” in the slave mode, when all 8-bit data received immediately after a start condition are “0”. The ADO is cleared to “0” when a start or stop condition is detected on the bus. (13) Last received bit monitor The SDA value stored at the rising edge of the SCL line is set to the LRB (bit 0 in SBISR). When the contents of the LRB are read immediately after an INTSBI interrupt request is generated in the acknowledge mode, and ACK signal is read. (14) Software reset function Software reset function is used to initialize SBI, when SBI is locked by external noise, etc. SWRST is set to “1”, internal reset signal pulse is generated and inputted into SBI circuit. All command registers and status registers are initialized to an initial value. SWRST is automatically cleared to “0” after initialize SBI circuit.

2.8.5 Data transfer in I7C bus mode

(1) Device Initialization First, set the ACK in the SBICR1 to “1”, the BC to “000”, and the data length to 8-bit to count a clock pulse for the acknowledge signal. In addition, set the transmit frequency to the SCK. Next, set the slave address to the SA in the I2CAR. Clear the ALS to “0” to set the addressing format. After confirming that the serial bus interface pin is “H” level, for specifying the default setting to a slave receiver mode, clear “0” to the MST, TRX, and BB in the SBICR2; “1” to the PIN; “10” to the SBIM; and “0” to bits 1 and 0. Note: To initialize the serial bus interface circuit, a constant period that the start conditions are not generated for any device is required after all devices which are connected to the bus are initialized. Then, the initialization must be completed during the period. If not, other devices may start transmitting data before the serial bus interface circuit has been initialized. Thus, data can not be normally received. (2) Start Condition and Slave Address Generation Confirm a bus free status (when BB = 0). Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to the SBIDBR. When the BB is “0”, the start condition are generated and the slave address and the direction bit which are set to the SBIDBR are output on a bus by writing “1” to the MST, TRX, BB, and PIN. An INTSBI interrupt request occurs at the 9th falling edge of the SCL clock cycle, and the PIN is cleared to “0”. The SCL pin is pulled down to the “L” level while the PIN is “0”. When an interrupt request occurs, the TRX changes by the hardware according to the direction bit only when an acknowledge signal is returned from the slave device. Note 1: The slave address to be output to the SBIDBR must be set after the bus free is detected by software. If setting of the slave address is executed before detection bus free, the current output data may be corrupted. Note 2: The bus free must be confirmed by software within 98.0 us (the shortest transmitting time according to the 12C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set “1” to the MST, TRX, BB, and PIN to generate the start conditions. If the start conditions are generated without writing “1” to them, transferring may be executed by other masters between the time when the slave address to be output to the SBIDBR is written and the time when “1” is written to the MST, TRX, BB, and PIN in the SBICR2. Thus, the slave address may be corrupted. 3-09-64 2002-01-08

b.When the MST is “0” (Slave mode) In the slave mode, the TMP87C409B/809B operate either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBI interrupt request occurs when the TMP87C409B/8096 receive a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete after matching a received slave address. In the master mode, the TMP87C409B/809B operate in a slave mode if it is losing arbitration. An INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. When an INTSBI interrupt request occurs, the PIN (bit 4 in the SBICR2) is reset, and the SCL pin is pulled down to the “L” level. Either reading/writing from/to the SBIDBR or setting the PIN to “1” releases the SCL pin after taking tow time. Check the AL (bit 3 in the SBISR), the TRX (bit 6 in the SBISR), the AAS (bit 2 in the SBISR), and the ADO (bit 1 in the SBISR) and implements processes according to conditions listed in the next table. Table 2-7. Operation in the slave mode [rex [ar [ass [aco] __conditions ___ | __itroces_ The TMP87C409B/809B loses arbitration when | Set the number ofbitsin 1wordtotheBC | transmitting a slave address and receives a slave | and write transmitted data to the SBIDBR. address of which the value of the direction bit sent from another master is “1”. T in the slave receiver mode, the TMP67C4098/8096 receives a slave address of which the value of the direction bit sent from the master is “1”. In the slave transmitter mode, 1-word data is | Check the LRB. If the LRB is set to “1”, set transmitted. the PIN to “1” since the receiver does not request next data. Then, clear the TRX to 0" release the bus. If the LRB is cleared to “Q", set the number of bits in a word to the BC and write transmitted data to the SBIDBR since the receiver requests next data. 1/0 |The TMP87C409B/809B lose arbitration when | Read the SBIDBR for setting the PIN to “1” transmitting a slave address and receives a slave | (reading dummy data) or write “1” to the address or GENERAL CALL of which the value of the | PIN. direction bit sent from another master is “0”. The TMP87C409B/809B loses arbitration when transmitting a slave address or data and terminates transferring word data. 1/0 [in the slave receiver mode, the TMP87C409B/8098 receives a slave address or GENERAL CALL of which the value of the direction bit sent from the master is “0”. 170 [in the slave receiver mode, the TMP87C409B/809B | Set the number of bits in a word to the BC terminates receiving of 1-word data. and read received data from the SBIDBR. 3-09-67 2002-01-08

(4) Stop Condition Generation When BB="1", writing “1” to the MST, TRX, and PIN and “0” to the BB starts a sequence for outputting a stop condition on the bus. Do not change the contents of the MST, TRX, BB, and PIN until a stop condition is generated on the bus. When a stop condition is generated and a bus SCL line is set to “L” level by the other devices, a stop condition is not started normally. Write “1” to the MST, TRX, and PIN, and “0” to the BB to generate a stop condition after releasing the SCLline. Note: When astop condition is generated. a time to rise the SCL line should not exceed tr =2n/fc - 3.5 x4/fc (2). (n depends on the SCK.) If the rising time of the SCL line exceeds the above value, there is a probability that a stop condition is not started normally. [scx nT ere, feces | trax, fem ania) a PC a [on ae _ | a a a fc; High-frequency clock [ Hz] “1" MST "1" 9 TRX So “0” BB LZ Stop condition "17 9PIN han an SCL pin +s a - i on -- SDApin re Ce oe H i beened PIN . ~~ BB (Read) Figure 2-36. Stop condition generation 3-09-68 2002-01-08

(5) Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart when the TMP87C409B/809B is in the master mode. Clear “0” to the MST, TRX, and BB and set “1” to the PIN and release the bus. The SDA pin retains the “H” level and the SCL pin is released. Since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from other devices. Check the BB until it becomes “0” to check that the SCL pin of the TMP87C409B/809B is released. Check the LRB until it becomes “1” to check that the SCL line of a bus is not pulled down to the “L” level by other devices. After confirming that a bus stays in a free state, generate a start condition with procedure 2.8.5. (2). In order to meet setup time when restarting, take at least 4.7 [1s] of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition. "0" MST “1 MST “0° > BB “1 BB “17 PIN “17 PIN |<47s1 (Min) Start condition SCL (Bus) oo SCL pin 9 a |(TMP87C409B/8098) ) i t SDA (pin) i e es LRB BB PIN l Figure 2-37. Timing diagram when restarting the TMP87C409B/809B 3-09-69 2002-01-08

AC Timing for SBI-Ver. B (I2C bus) [reamed tt [ee |e me | | Hold time (repeated) START condition. After this tyo;stA 2c period, the first clock pulse is generated. [omeroisimernowy | ovo | of | The period of generating a start condition when testa 3ite writing START command. The period of falling SCL clock when writing STOP tes 3ifc command. The period between falling edge of SDA and rising teoac 2"fe edge of SCL when generation a STOP condition. Note: Values those can be applied to “n” in the above table are 4 to 10, and setting values of SCK (bit 2 to 0 of SBICR1) for these values as follows. SCK(bit2toOinthesBicRt) | on | ee Start Command ‘Stop Command y v; tos, in two;o0ar " os fa i tact to, sr9 <x ‘HO:IOAT ‘tsuspaT ‘tsy;sTo. 3-09-70 2002-01-08

2.8.6 Clocked-synchronous 8-bit SIO mode control

The following registers are used for control and operation status monitoring when using the serial bus interface (SBI) in the clocked-synchronous 8-bit SIO mode. Serial Bus Interface Control Register 1 SBICRI 7 6 5S 4 3 2 1 0 (0020») [sios| #2 | siom [or], scK, | (initial value: 0000 +000) Indicate transfer start/stop 0: Stop 1: Start Continue/abort transfer 0: Continue transfer 1; Abort transfer (automatically cleared after abort) Transfer mode select 00: 8-bit transmit mode 01: reserved 10: 8-bit transmit / receive mode 5 11: Bbit receive mode ie 000: fc/25 (250 kHz) 001: f/26 ( 125kHz) 010: fo/27 ( 62.5kHz) ‘Output on i O11: f/28 (31.25kHz) patfc=B8MHz | SCK | Serial clock select 100: 729 (15.62 kHz) SCK pin 101: f2"9 (7.81 kHz) 110: fd211 ( 3.90kHz) __ 111: External clock (input from SCK pin) Note 1: +; Don’tcare Note 2: Set the SIOS to “0” when setting the transfer mode or serial clock. Note 3: SBICR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. Serial Bus Interface Data Buffer Register SBIDBR 7.6 5 4 =#3 2 1 0 Note: Cannot read the data which was written into SBIDBR, since a write data buffer and a read buffer are independent in SBIDBR. Therefore, cannot access it any of in read-modify-write instruction such as bit operate, etc. Serial Bus Interface Control Register 2 SBIR Oo Done hae SE dpe ene 00: Port mode (serial bus interface output disable) Serial bus interface operation mode | 01: SIO mode Write- selection 10: 2C bus mode only 11: reserved Note 1: +; Don’tcare Note 2: Switch a mode to port after data transfer is complete. Note 3: Switch a mode to SIO mode after confirming that input signal via port is “H” level. Note 4: SBICR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. Serial Bus Interface Status Register a re a a Serial transfer operating status 0: Transfer terminated monitor 1: Transfer in process - i , 0: Shift operation terminated Figure 2-38. Control register / data buffer register / status register in SIO mode 3-09-71 2002-01-08

b. Shift edge The leading edge is used to transmit data, and the trailing edge is used to receive data. @® Leading edge _ Data is shifted on the leading edge of the serial clock (at a falling edge of the SCK pin input/ output). @ Trailing edge __ Data is shifted on the trailing edge of the serial clock (at a rising edge of the SCK pin input/ output). SCK pin LIuLrvesrel y TIVITY $0 pin Xso_ XC air X_wita Xsies Xie Xwits Kaine X87 Shift ogister NEN GEE TEED RT) TID) OT) ORT), (a) Leading edge SCK pin KLE LS L& FLA LF LA Sipin (eo X~ier X_aiez X_sies X_sits X_sits X_sits X_aie7 Shiftregister sevswvse Yfesvreve{soreeee Kzidnnene K321Qeeee)K 320000 54321000 K65452102(78545210 (b) Trailing edge Note: + : Don’t care Figure 2-41. Shiftedge (2) Transfer mode The SIOM (bits 5 and 4 in SBICR) is used to select a transmit, receive, or transmit/receive mode. a.8-bit transmit mode Set a control register to a transmit mode and write data to the SBIDBR. After the data is written, set the SIOS to “1” to start data transfer. The transmitted data is transferred from the SBIDBR to the shift register and output to the SO pin in synchronous with the serial clock, starting from the least significant bit (LSB). When the data is transferred to the shift register, the SBIDBR becomes empty. The INTSBI (buffer empty) interrupt request is generated to request new data. When the internal clock is used, the serial clock will stop and automatic-wait function will be initiated if new data is not loaded to the data buffer register after the specified 8-bit data is transmitted. When new data is written, automatic wait function is canceled. When the external clock is used, data should be written to the SBIDBR before new data is shifted. The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the SBIDBR by the interrupt service program. When the transmit is started, after the SIOF goes “1” output from the SO pin holds final bit of the last data until falling edge of the SCK. Transmitting data is ended by cleaning SIO to “0” or setting SIOINH to “1” buffer empty interrupt service program. When the SIOS is cleared, the transmitted mode ends when all data is output. In order to confirm if data is surely transmitted by the program, set the SIOF (bit 3 in the SBISR) to be sensed. The SIOF is cleared to “0” when transmitting is complete. When SIOINH is set, the transmission is immediately ended and SIOF is cleared to “0”. 3-09-73 2002-01-08

b.8-bit receive mode Set a control register to a receive mode and the SIOS to “1” for switching to a receive mode. Data is received from the SI pin to the shift register in synchronous with the serial clock, starting from the least significant bit (LSB). When the 8-bit data is received, the data is transferred from the shift register to the SBIDBR. The INTSBI (buffer full) interrupt request is generated to request of reading the received data. The data is then read from the SBIDBR by the interrupt service program. When the internal clock is used, the serial clock will stop and automatic-wait function will be initiated until the received data is read from the SBIDBR. When the external clock is used, since shift operation is synchronized with the clock pulse provided externally, the received data should be read before new data is transferred to the SBIDBR. If the received data is not read, further data to be received is canceled. The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read. The receiving is ended by clearing SIOS to “0” or setting SIOINH to “1” in buffer full interrupt service program. When SIOINH is set, the receiving is immediately ended and SIOF is cleared to “0”. When the SIOS is cleared, received data is transferred to the SBIDBR in complete blocks. The received mode ends when the transfer is complete. In order to confirm if data is surely received by the program, set the SIOF (bit 3 in SBIDBR) to be sensed. The SIOF is cleared to “0” when receiving is complete. After confirming that receiving has ended, the last data is read. When the SIOINH is set, receiving data stops. The SIOF turns “0” (the received data becomes invalid, therefore no need to read it). Note: When the transfer mode is switched, the SBIDBR contents are lost. In case that the mode needs to be switched, conclude receiving data by clearing the SIOS to “0*, read the last data, and then switch the mode. slos i cb i SEF ' ' tot H Sipin CMR 22K 2 X 22X 23K 2X 25X a6X 27)K boX 2X 2X bsXbaX bsXbeX br] | INTSBI interrupt ft request seiner Ce cca Read received data Read received data Figure 2-44. Receive mode (Example: Internal clock) 3-09-75 2002-01-08

c. 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBIDBR. After the data is written, set the SIOS to “1” to start transmitting/receiving. When transmitting, the data is output from the SO pin on the leading edges in synchronous with the serial clock, starting from the least significant bit (LSB). When receiving, the data is input to the SI pin on the trailing edges of the serial clock. 8-bit data is transferred from the shift register to the SBIDBR, and the INTSBI interrupt request occurs. The interrupt service program reads the received data from the shift register to the SBIDBR, and the INTSBI interrupt request occurs. The interrupt service program reads the received data from the data buffer register and writes data to be transmitted. The SBIDBR is used for both transmitting and receiving. Transmitted data should always be written after received data is read. When the internal clock is used, automatic-wait function is initiated until received data is read and next data is written. When the transmit is started, after the SIOF goes “1” output from the SO pin holds final bit of the last data until falling edge of the SCK. When the external clock is used, since the shift operation is synchronized with the external clock, received data is read and transmitted data is written before new shift operation is executed. The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read and transmitted data is written. Transmitting/receiving data is ended by cleaning the SIOS to “0” or setting SIOINH to “1” in interrupt service program. When the SIOS is cleared, received data is transferred to the SBIDBR in complete blocks. The transmit/receive mode ends when the transfer is completed. In order to confirm if data is surely transmitted/received by the program, set the SIOF (bit 3 in SBISR) to be sensed. The SIOF becomes “0” after transmitting/receiving is complete. When SIOINH is set, the transmit/receive operation is immediately ended and SIOF is cleared to “0”. Note: When the transfer mode is switched, the SBIDBR contents are lost. In case that the mode needs to be switched, conclude transmitting/receiving data by clearing the SIOS to '0“, read the last data, and then switch the transfer mode. iOS te sior —_ SEF : ( ! SCKO pin i KA UU UUU UL 500 pin \\X aX aX aX aX aeX asX 26) Sf Fee XeXeXey 510 pin WMKoXXoX oXaXsXeXal XX aX aX aX daX d5X de X dr) INTSBI interrupt —_ ee | ee | request Wahranan nel dreecoun rite transmitted Read received Write transmitted Read received data (a) data (c) data (b) data (d) Figure 2-45. Transmit/receive mode (Example: Internal clock) 3-09-76 2002-01-08

tsopy =Min 4/fe [s] (In NORMAL mode, IDLE mode) Figure 2-46. Transmitted data hold time at end of transmit/receive 3-09-77 2002-01-08

2.9 Oscillation Stop Detector

The TMP87C409B/809B each have a Oscillation Stop Detector. If the oscillation stops for any cause, P51 (CLZ1) or P50 (CLZ0) becomes high-impedance. Note: On the emulator, when Oscillation Stop Detector is enabled, P50 or P51 may become high- impedance by break instruction or single step instruction. Release of break instruction or single step instruction returns the port in condition before high- impedance.

2.9.1 Configuration

noceeeee TENCLAEON cssey CLZ10UT. i j Oscillation P51 control Ose. enable — [>> i Stop i (om z Detector : : o1200uT. P50 control LJ LJ XIN XOUT Figure 2-47. Oscillation stop detector

2.9.2 Control

The Oscillation Stop Detector is controlled by register (CLZCR). Oscillation Stop Detector ee (00289) Lorvreivvverievvredeeshsrny [BTO*ER P51CR P50CR] (Initial value: see +000) Detection output control in | 0: Enable in STOP mode ji 0: P51 detection enable Write- . 0: P50 detection enable P50 detection output control | |: peg detection disable Note 1; *; Don’tcare Note 2: CLZCR is write-only register, therefore, it cannot be operated with read modify commands (SET, CLR and other bit operation commands: AND, OR and other multiplication commands). Figure 2-48. Oscillation stop detector control register 3-09-78 2002-01-08

2.9.3 Function

If the oscillation stops for any cause, P51 (CLZ1) or P50 (CLZ0) becomes high-impedance. When P51 or P50 used as a oscillation stop detector output, the output pins should be set to output mode beforehand the output latch should be set to “1” or “0”. P51/P50 output is selected by P51CR and P5OCR (bit 1 and 0 in CLZCR). In STOP mode, the oscillation stop detection can be disabled be setting STOPCR to “1” (bit 2 in CLZCR). Lo Teiz (Detection Time) cLZ10UT a PS10UT nr | Nie ee re eee eee H i Detection output Initial Output mode . (High-2) (High-2) ("17 or “0” output) Figure 2-49. Oscillation stop detector timing chart 3-09-79 2002-01-08

2.10 10-bit AD Converter (ADC) The TMP87C409B/809B have a 10-bit successive approximate type AD converter. Analog reference power supply (VAREF) is automatically cut off in stop mode or analog input disable.

2.10.1 Configuration

Wop) FAY} 0+ aanen nanan eeneneeneennn nnn c eens Ol vass P67 C}-4B 5 beni nz R RZ (vss) ‘STOP +>] AINDS Analog input Reference Multiplexer voltage AINO OF Ay aint O B 10 ain2 OF c ain3 D /Analog comparator aina O E ans O F Ain7 O HEN Shift clock 10 ENS SREF 8

8 ADS | | EOCF

P67 VAREF select register _P6 input/output control register. AD Converter control register AD Conversion result register Figure 2-51. AD Converter 3-09-80 2002-01-08

2.10.2 Control

The AD converter is controlled by an AD converter control register (ADCCR) and an analog reference power supply select register (SELREF). Reading EOCF of ADCCR recognizes AD converter operation state, and reading AD conversion result registers (ADCDRH, ADCDRL) recognize AD conversion result. AD Converter Control Register ADCCR 7 6 5 4 #3 2 +1 +0 (8096) [Eoce[ ADs [ACK [anos SAN] (nit vale: 00001000) EOCF |ADconversionend |Setto “1” at the end of AD conversion. Cleared when EOCF and ADCDRH flag are read successively. Read- 0: Under conversion or Before conversion only 1:_AD End of conversion ‘AD conversion start [Automatically cleared to "0" after AD conversion has started. Setting ADS to 1” during AD conversion initializes and newly starts AD conversion. lo: - 1: AD conversion start ACK | Conversion time 00: 216/fe: (27 ys at fc= 8 MHz) }01: 384/fc: (48 1 at f= 8 MHz) 10: 728/fc: (91 ps at f= 8 MHz) 11; Reserved AINDS | Analog input contro! |0: Enable 4: Disable 000: AINO 001: AIN1 010: AIN2 Analog input 011: AIN3. SAIN selection 100: AIN4 101: AINS 110: AING 111: AIN7 Note 1: Select analog input when AD converter stops. Note 2: The ADS is automatically cleared to “0” after starting conversion. Note 3: The EOCF is cleared to “0” when reading the ADCDRL. Note 4: The EOCFis read-only. The written data is ignored. VAREF Select Register A ee Se Se ee SELREF A : : : : (Initial value: O### +448) oor) asssssscsosseousssassondssosneedesssnssdsssenedonneend sreF | 0: Internal VDD Write- 1; External level (P67) only Note 1: * ; Don’tcare Note 2: When used as an analog reference power supply, P67 should be set to the input mode. Figure 2-51. AD Converter control register and analog reference select register AD Converter Result Register appr. 7 6 5 4 #3 2 #7 0 (00254) p06 |ap05[aD04[ap03 [A002] Read-only Figure 2-52. AD converter result register 3-09-81 2002-01-08

2.10.3 Operation

The high side of an analog reference voltage is applied to VAREF pin, and the low side is applied to VASS pin. VAREF can be selected either VDD or P67 by SREF (bit 7 in SELREF). The reference voltage between VAREF and VASS is divided into the voltage corresponding with bits by radar resistance. The reference voltage is compared with an analog input voltage and AD conversion is performed. Note 1; VASS is the same as VSS. Note 2: In the TMP87C409B/809B, the analog power supplies (VAREF, VASS) for the AD converter are shared with the digital power supplies (VDD, VSS). For applications that require high accuracy for the AD converter, consider noise reduction on the power supply lines by, for example, lowering the impedance of or inserting a noise filter capacitor into the power supply line. (1) Start of AD conversion First, selects one of analog input channels (AIN7 to AINO) by SAIN(bit 3 to 0 in ADCCR). Clear the AINDS (bit 4 in ADCCR) to “0”. The channel used as an analog input is cleared to “0” by P6 input control (P6CR). Note: The pin that is not used as an analog input can be used as regular input/output pins. During conversion, do not perform output instruction to maintain a precision for all of the pins. The AD conversion time is programmed into the ACK field (bits 5 and 4) in the ADCCR. AD conversion is started by setting the ADS (bit 6 in ADCCR) to “1”. AD conversion time is from AD conversion until setting the conversion result to ADCDR. When ACK = 00, conversion is accomplished in 216/fc [s] (54 machine cycles). For example, 27 ys in fc = 8 MHz. The EOCF (bit 7 in ADCCR) is set to “1” at end of conversion.When ADS is set to “1” during AD conversion, conversion is initialized and restarted.Sampling of an analog input voltage is performed in 4 machine cycles after AD conversion start is indicated. (2) Reading of AD conversion result After the end of conversion (EOCF = 1), read the conversion result from the ADCDR. The EOCF is automatically cleared to “0” when reading the ADCDR. When the conversion result is read out during AD conversion, the invalid value is read out. (3) AD conversion in STOP mode When the MCU places in the STOP mode during the AD conversion, the conversion is terminated and the AD conversion value become indefinite. Thus EOCF is maintained to “0” after returned from the STOP mode. However, if the STOP mode is started after the end of AD conversion (EOCF = 1"), the AD conversion value and EOCF state are held. ADS l ADCOR CD TD CT) 384/fc 384/fc EOCF l 728/fc J l Tele J Procession °° o—? ° as recession i) 44 4 Read Start Read Start Start Figure 2-53. AD Conversion Timing chart 3-09-82 2002-01-08

Example: After AIN pin 4 is selected as an analog input channel, and conversion time is selected 728/fc [s], AD conversion is started. EOCF is confirmed and the converted result is read out. It is saved to addresses 009Ey - 009FH in RAM.

7 AIN SELECT

LD (ADCCR) , 001001008 ; Selects AIN4, conversion time is 728/fc [s} ; AD CONVERT START SET (ADCCR). 6 7; ADS=1 SLOOP: TEST (ADCCR) . 7 ; EOCF=1? JRS T, SLOOP ; RESULT DATA READ LD (9EH), (ADCDRH) LD (9FH), (ADCDRL) Figure 2-54 shows the relationship between An analog input voltage and AD converted 10-bit digital value. 3FFy a 3FEy —— 3FDy ra AD ia conversion < result re 034 oe 024 — OMT TF “ < $+ t+ +> - o 4 2 3 1021 1022 1023 1024 x ARES Vass Analog input voltage Figure 2-54. Analog input voltage vs. AD conversion result (typ.) 3-09-83 2002-01-08

When ordering ES from Toshiba, always be sure to specify mask options using a request sheet for the production of Microcontroller Engineering Sample (ES). For details on how to write this specification, refer to Appendix, “Method for Specifying Mask Options in TLCS-870 Series.” (1) Control pins The input/output circuitries of the TMP87C409B/809B control pins are shown below. ee Osc. enable fe ina pi Resonator connecting pins VDD (high-frequency) XIN vod Re Ro Ry =1.2MQ — (typ,) XOUT Ro =1.5k (typ) XIN xOUT wer Rin Hysteresis input — R Pull-up resistor RESET Rin =220kQ = (typ.) Ro =1k2 (typ.) initial “High-2* ——po—] a R Hysteresis input INTS / STOP Input (p43) Pas Ro =1ka (typ.) INTSSTOP VDD R > Pull-down resistor TEST Input iN = Rw R =1k0 Note: The TMP87P809 does not have a pull-down resistor (Ry) and diode (Dj) for TEST pin. Be sure to fix the TEST pin to low in MCU mode. 3-09-84 2002-01-08

(2) Input/Output Ports The input/output circuitries of the TMP87C409B/809B input/output ports are shown below. Amask option code is only “A”. Initial “High-2" WDD Tri-state VO Hysteresis inut Disable Fe a R =1k9 (typ) Initial “High-2” Sink open drain output Hysteresis input vo —f>-—_f High current output R R stk — (typ) Initial “High-2” VDD Tri-state VO Hysteresis input High current output Disable R Ro =1kQ — (typ.) Initial “High-Z” VDD Tri-state VO R =1kQ (typ) Disable R 3-09-85 2002-01-08

Electrical Characteristics

Absolute Maximum Ratings (Vss = 0 V) [Moo [O06 TT Input Voltage [vw fT 032009403 Output Vor Ports P1, P5, P6, XOUT =03toVop+03 | | uiput Voltage | Vourr [ponpa toss Tv | Ports P1, P6 er Output Current tol fen . Ports PA, PS {30 (Per 1 pin) |iok ___| tours _| Ports Pt, P5.P6 [ -18 r Ports Pt, P6 Output Current OL oun ae PonsP Ps a rota [iow | Sloura | PonsP1. 5,6 3 | Power Dissipation Topr = 70°C] i. | ow | Soldering Temperature (time) Potid [2st Storage Temperature [stg f= 55 to 125 *c Operating Temperature [top f= 301070 Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Recommended Operating Conditions (Vss = OV, Topr= - 30 to 70°C) ee NORMAL mode fe=8MHz [iDLemode _—| Supply Voltage Voo fox NORMAL mode 2 v 42Mbe : wt et hyst P Vop 2 45V foo Input High Voltage Yoox0.75| Voo | v Vo 2 4.5V Input Low Voltage Hysteresis input Vopx0.25 | Vv VOD = 4.5to5.5V | ao | Clock Frequency XIN, XOUT MHz Yop =22Vt055 V [oa Note1; The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ACIDC values etc.), malfunction may occur, Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note2: Clock frequency fc: Supply voltage range is specified in NORMAL mode and IDLE mode. 3-09-86 2002-01-08

DC Characteristics (Vss = OV, Topr= - 30 to 70°C) fren] vm [moan [oon [ve J [om] Himteresivorage | vig [Ameresiinpe | | - oa} - |v tins _| TEST Vop=5.5V Input Current | tiv2 _| Tri-state ports Vin=5.5V/0V uA | ws _| RESET, STOP inp Resistance | Ra | RESET ans] Output Leakage Tri-state ports Vpp = 5-5 V, Vout =5-5V/0V. ho uA Current Output High Voltage Tri-state ports Voo=45Vilon=-0.7mA_ | 41 | - | - | V [vous [except xOuT, PaandPs |Voo=45Vilqu=16ma | ~~ | 0a | Supply Current in Voo =5.5V NORMAL mode fc=8 MHz Supply Current in Vin=5.3V/0.2V mA IDLE mode Supply Current in Vop=3.0V NORAML mode fe=4.2MHz Supply Current in Vin=2.8V/0.2V 1s mA IDLE mode : Supply Current in Vop=5.5V STOP mode Vw=5.3V/0.2V ws Note 1: Typical values show those at Topr =25°C, Vpp =5 V. Note 2: Input Current lIN1, IIN3,: The current through resistor is not included, when the input resistor (pull-up or pull-down) is contained. AD Conversion Characteristics (Vss = OV. Von = 2.2 to 5.5 V. Topr= - 30 to 70°C) Fame [| —_eoaow [vm [ow | wm [ome [veer [oe Analog Reference Voltage et | = | vo v J vass [os analog Reference curent | tner [Vaner= 55V.Vasal=oovp- [os | 10 | ma Nonlinearity Eror Voo=50¥ ee ee ere Vanes = 5.000V Vass(Vss) = 0.000 a ee ee or LsB Ful Scale Ervor Voos22¥ ee ee ee Varer= 2.200 V Vas Vas) = 0.000 ee oe eee Note: Quantizing error is not contained in those errors. 3-09-87 2002-01-08

Oscillation Stop Detector Characteristics (Vss = OV, Topr= - 30 to 70°C) frm] enews dn [oe [oe Jo] VDD =2.2V to 5.5 V (fe =2 MHz to 4.2 MHz) Detection time Taz s VDD =45V to 5.5 (fe=8MHz) AC Characteristics (Vss=0V, Vop =4.5to5.5V, Topr= - 30 to 70°C) [symbot | conaons | tin | ye. | an | uni] Machine Cycle Time tey as High Level Clock Pulse Width | twcn_| For external clock operation Low Level Clock Pulse Width fe=8MHz Recommended Oscillating Conditions (Vss=0V, Vop=2.2 to 5.5V, Topr= - 30 to 70°C) [ovata | cacy | “commended Osler requency MHz — | MURATA _CSTCC8M00G53-RO High-frequency (45Vt05.5%) | mupata — cSTLSBM00G53-B0 Ceramic Resonator Oscillation 4MHz — [MURATA _CSTCR4MO0G53-RO (22Vt055¥) | murata — csTLs4mooGs3-80 XIN xour (1) High-frequency Oscillation Note 1: When used in high electric field such as a picture tube, the package is recommended to be electrically shielded to maintain a regular operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL; http:!iwww.murata.co.jp/searchlindex.htm! 3-09-88 2002-01-08

CMOS 8-bit Microcontroller The TMP87P809 is a high-speed, high-performance 8-bit single chip microcomputer, which has 64-Kbits One- Time PROM. The TMP87P8039 is pin compatible with the TMP87C409B/809B. The operations possible with the TMP87C409B/8098 can be performed by writing programs to PROM. The TMP87P809 can write and verify in the same way as the TC57256AD using an adapter socket and a general-purpose PROM programmer. [_PoductNo. [Rom [RAM Package Adapter socket _] TMP87P809N P-SDIP28-400-1.78 BM11122 anenenmenrond 8 Kbytes 256 bytes frmennstetietnf centres TMP87P809M PSOP28-450-1.27 BM11116 Pin Assignments (Top View) P-spip28-400-1.78 SOP28/SDIP28 bios/xouT<—{ 1 28 [<— vob (VAREF) VCC cLocKxin—» 2 27 P<—RESET veprrest—> Cf 3 26 [<> P17/A7/07 OE (AINO) P60~<>C] 4 25 [<> PIG/A14/A6/D6 CE/(AIN1) P61<> Tf 5 24 [<> PIS/A13/A5/D5 TMP87P809N DO/AO/A8/ (AIN2) P62~<> Cj 6 23 D> PIMAI2/A4/D4 — P-SOP28-450-1.27 D1/A1/9/ (AIN3) P63<>C] 7 22 [<> P13 (DVO) /A11/A3/D3 (AINA) P64~<>C} 8 21 P<» P12 (TC1) /A10/A2/D2 —. (AINs) Pes~<>C] 9 20 <> P11 (INT) (aiNé) P66<>C] 10 19 [<> P10 (INTO) (AIN7/VAREF) P67<>C] 11 18 [<> P43 (STOP/INTS) (TC3/INT3/CLZ0) P50~<>L] 12 17 [<> P42 (SDA/SO) (TCa/PWM/PDO/CLZ1) PS1~<>L] 13 16 [<> P41 (ScL/s!) noe ‘TMP87P809M GND/(vASS) vss—>C] 14 15 [<> P40 (SCK) 0007076841 @ For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. @ TOSHIBA is “continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA. products, to comply with the standards of safety. in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or gomoge to property. In developing your designs, please ensure that, TOSHIBA (products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook" etc.. @The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc). These TOSHIBA products are neither intended ‘nor warranted for usage in equipment’ that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may ‘cause less of human life or. bodily’ injury (Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, ‘transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's ‘own risk. ihe products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is resented only as @ guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual Property or other rights of ‘the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual Property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 3-09-89 2002-01-08

The TMP87P809 has two modes: MCU and PROM. (1) MCU mode In this mode, the TMP87P809 is pin compatible with the TMP87C409B/8098 (fix the TEST pin at “L” level). (2) PROM mode Al4 to AS P17 to P12, P63, P62 ooscteertesenssscrvtevsasnnetnne Input Program memory address input A7 to AO P17 to P12, P63, P62 Joe 00 |v rogram memory dtsinguvon Lo fouputensesigntinnse ea vep +12.5V/5V (Program supply voltage) TEST vec Powersupply | +5V vob GND ov vss P11 to P10 P43 to P40 sestentnenat nunteneesneeeseee vo P51 to P50 PROM mode setting pins. Be fixed at “L” level. P67 to P64 cal XIN Input Inputs a clock externally. (CLOCK) | ox XOUT Input PROM mode contro! signal (DIDS) input a eeeeSSSSSSSSSSSSSSSSSSSSSSSSSFee 3-09-90 2002-01-08

The configuration and function of the TMP87P809 are the same as those of the TMP87C409B/809B, except in that a one-time PROM is used instead of an on-chip mask ROM. 1. Operating Mode The TMP87P809 has two modes: MCU and PROM.

1.1 MCU Mode

The MCU mode is activated by fixing the TEST/VPP pin at “L” level. In the MCU mode, operation is the same as with the TMP87C409B/809B (TEST/VPP pin cannot be used open because it has no built in pull-down resistance.)

1.1.1 Program memory

The TMP87P809 has a 8 Kbyte (addresses E000 to FFFF} in the MCU mode, addresses 6000 to 7FFFy in the PROM mode) one-time PROM. To use the TMP87P809 as the system evaluation for the TMP87C409B/809B, the program should be written to the program memory area as shown in Figure 1-1. 0000, 0000), £000 £000 6000 H Program i Program i Program : oe FFFF FFFF TRFF PROM mode TMP87CB09B McUmode —_mP87P809 (a) ROMsize=8 Kbytes 0000}, 0000), | EZ | a c a | MCU mode PROM mode TMP87C409B TMP87P809 (b) ROM size =4 Kbytes Figure 1-1. Program memory area Note: Either write the data FFH to the unused area or set the general-purpose PROM programmer to access only the program storage area

1.1.2 Data memory

The TMP87P809 has an 256 bytes data memory (static RAM). SSSSSSSSSSSSSSSSSSSSSSSSSssSeeeeeeee 3-09-91 2002-01-08

1.1.3 Input / Output circuits

(1) Control pins The control pins of the TMP87P809 are the same as those of the TMP8/C409B/809B except that the TEST pin has no built-in pull-down resistance. ue oO Note: TEST pin has no built-in pull-down resistance Figure 1-2. TEST Pin (2) W/O port The V/O circuits of TMP87P809 ports are the same as the TMP87C409B/809B.

1.2 PROM Mode

The PROM mode is used to write and verify programs with a general-purpose PROM programmer. Note: Please set the high-speed programming mode according to each manual of PROM programmer. VPP (12.5V/5V) voc

9 TIMP87P809 9

PROM programmer connection to adaptor socket: Piz BM11116 (TMP87P809M) P63 Adapter BM11122 (TMP87P809N) P62 Al4too P11, P10 J D7 tod ou P43 to P40 = Es! p60 P51, P50 = P61 P67 to PBA = D7t00 vss RESET Refer to Pin Function for the other pins. Figure 1-3. Setting for PROM mode SSeS 3-09-92 2002-01-08

1.2.1 Programming flowchart (High-speed Programming Mode-I)

The high-speed programming mode is achieved by applying the program voltage (+ 12.5 V) to the Vpp pin when Vcc =6 V. After the address and input data are stable, the data is programmed by applying a single 1ms program pulse to the CE input. The programmed data is verified. If incorrect, another 1ms program pulse is applied and then the programmed data is verified. This process should be repeated (up to 25 times) until the program operates correctly. Programming for one address is ended by applying additional program pulse with width 3 times that needed for initial programming (number of programmed times x 1 ms). After that, change the address and input data, and program as before. When programming has been completed, the data in all addresses should be verified with Vcc = Vpp = 5 Vv. << = No N=25? es No Error Verify OK 1 ms pulse 3N times of 3Nms pulse 1 time Verify Error NO_<Tast Address? Yes Veo =5V address OK Figure 1-4. Flowchart of high-speed programming mode - I 3-09-93 2002-01-08

1.2.2 Programming flowchart (High-speed Programming Mode-II)

The high-speed programming mode is achieved by applying the program voltage (+ 12.75 V) to the Vpp pin when Vcc = 6.25 V. After the address and input data are stable, the data is programmed by applying a single 0.1ms program pulse to the CE input. The programmed data is verified. If incorrect, another 0.1ms program pulse is applied and then the programmed data is verified. This process should be repeated (up to 25 times) until the program operates correctly. After that, change the address and input data, and program as before. When programming has been completed, the data in all addresses should be verified with Vec = Vpp =5 V. Ss No Error Verity No Yes Vpp=5V address ‘OK Figure 1-5. Flowchart of high-speed programming mode - II SSeS 3-09-94 2002-01-08

1.2.3 Writing method for general-purpose PROM program

(1) Adapters BM11116: TMP87P809M BM11122: TMP87P809N (2) Adapter setting Switch (SW1) is set to side N. (3), PROM programmer specifying i) PROM type is specified to TC57256AD. Writing voltage: 12.5 V (high-speed program | mode)

12.75 V (high-speed program II made)

ii) Data transfer (copy) (note 1) In TMP87P809, EPROM is within the addresses 6000 to 7FFFy. Data is required to be transferred (copied) to the addresses where it is possible to write. The program area in MCU mode and PROM mode is referred to “Program memory area” in Figure 1-1. Ex. In the block transfer (copy) mode, executed as below. ROM capacity of 4KB: transferred addresses F000 to FFF} to addresses 7000 to 7FFFH ROM capacity of 8KB: transferred addresses E000 to FFFF} to addresses 6000 to 7FFFy iii) Writing address is specified. (note 1) Start address: 7000} (ROM 8 KB: 6000}) End address: 7FFFH (4) Writing Writing/Verifying is required to be executed in accordance with PROM programmer operating procedure. Note 1: The specifying method is referred to the PROM programmer description. The data in addresses 0000 to 5FFF} must be specified to FFy. Note 2: When MCU is set to an adapter or the adapter is set to PROM programmer, a position of pin 1 must be adjusted. If the setting is reversed, MCU, the adapter and PROM program is damaged. Note 3: TMP87P809 does not support the electric signature mode (hereinafter referred to as “signature”). If the signature is used in PROM program, a device is damaged due to applying 12 V + 0.5 V to the address pin 9 (A9). The signature must not be used. SS

Absolute Maximum Ratings (ss = OV) [ vo [Oto | Program Voltage TEST/Vep pin = 0.3 to 13.0 Input Voltage | vw [= 03 t0Vo0 + 03 Output Volta: | Yours [PortsPt.ps.p6xouT | = 0.3t0V0p+03 | | mparvotese Port Pa = 031055 ity eon Ports PA, PS: a vere [oH tours _[Ports1,P5, P6 [ =e | r Ports Pt, P6 [30 Output Current ol ae (rota) Zlourz_| Ports P4, PS a | 10H Zlours_| Ports P1, P5, P6 a Soldering Temperature (time) posi fT 260¢089 se Storage Temperature | istg f= 5510125 Operating Temperature | too [= 302070 Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Recommended Operating Conditions (Vss=0V, Topr= - 30 to 70°C) eT NORMAL mode IDLE mode Supply Voltage Yoo f= NORMAL mode Vv 4.2MHz | IDLE mode [var [encept nysteessinput Yoo x070 Vpo 2 4.5V Input High Voltage Voo%0.75| Vop | v re Yoo <45V Voo x00 (3 yste Vop 2 4.5V (oo Input Low Voltage Voox0.25 |v ee Yoo <45V Voox0.10 VOD = 4.5to5.5V [eo | Clock Frequency fc XIN, XOUT Vop= 2.2V to5.5V. [a2 | Note1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note2: Clock frequency fc: Supply voltage range is specified in NORMAL mode and IDLE mode. See 3-09-96 2002-01-08

DC Characteristics (Vss=0V, Topr = - 30 to 70°C) [reonewr forma] rw «(woos [wn [ve [ome [om] Hysteresis Voltage [Vis [Hysteresisinput [= Po PT - ee a Input Current | tiy2 _| Tri-state ports Vin=5.5V/0V #2 | pA | liys_| RESET, STOP [inputResistance | Rive | RESET ee ee ‘Output Leakage Tri-state ports Vpp = 5-5 V, Vout = 5-5V/0V iA Current Output High Voltage Voo=45Vilow=-07ma [at | = | = |) | Vou [esceptxour,raandes [Vop=45Viin=tema [ - [ - | oa | [Output towcurrent [tos [paps Vo =45V,Vostov | - | 20 | - | ma | Supply Current in Vop=5.5V NORMAL modes fem 8MHz A m Supply Current in Vin=5.3V/0.2V IDLE modes Supply Current in Vpp = 3.0V NORAML mode fe=4.2MHz Supply Current in Vin=2.8V/0.2V 20 IDLE mode : Supply Current in Vop=5.5V STOP mode Viw=5.3V/0.2V Leal Note 1: Typical values show those at Topr =25°C, Vpp =5 V. Note 2: Input Current lIN1, IIN3,: The current through resistor is not included, when the input resistor (pull-up or pull-down) is contained. AD Conversion Characteristics (Vss=0V, Vp = 2.2 to 5.5V, Topr= ~ 30 to 70°C) [sme [| ewan [vm [ow [wm [om [| var | Te Analog Reference Voltage | = | v0 v [ves fo Pg Analog Reference current Vara 55vVasvg=00ov]- | os | 10 | ma Nonlinearity rror Voo=50V p= | or Full Scale Error Yoo=22¥ ee ee eee Varer= 2.200V Vass (Vs) = 0.000 V ee ee er Note: Quantizing error is not contained in those errors. SSeS 3-09-97 2002-01-08

Oscillation Stop Detector Characteristics (Vss=0V, Topr= - 30 to 70°C) a a VDD = 2.2 V to 5.5V (fc = 2 MHz to 4.2 MHz) Detection time Taz s VDD =4.5V to 5.5 (fe= 8 MHz) AC Characteristics (Vss=0V, Vop=4.5 to 5.5V, Topr= - 30 to 70°C) symbol | ___congtons in] ye, |e | ni | In NORMAL mode Machine Cycle Time tey ss In IDLE mode High Level Clock Pulse Width | twen_| For external clock operation Recommended Oscillating Conditions (Vss=0V, Vop=2.2to5.5V, Topr=-30 to 70°C) sai, Recommended Constant oxclaton stator | Recommended constant] _e~«NeEs [a Te] High-frequency (5Vt05.5¥) TmuRaTA _csAB.ooMTZ [sone | opr _| Ceramic Resonator Oscillation 4MHz MURATA —_ CST4.00MGWU [| - | Caves |wurara csasoowsu | 0m | 205" _| xIN xour (1) High-frequency Oscillation Note 1: When used in high electric field such as a picture tube, the package is recommended to be electrically shielded to maintain a regular operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL;http:/iwww.murata.co.jp/searchlindex.htm! eSSSSSSSSSSSSSSSeeeSSSSSSSSSSSMMMMssMFFFFFsSSS 3-09-98 2002-01-08

(1) READ OPERATION (Topr=0 to 70°C) DC Characteristics, AC Characteristics (Vss=0V) a ed [ve [OO vcexoe7 [= vee Tv | inputtowvoltage | ue [OP eco Tv | Supply Voltage [7% | so | sas | | Program Supply Voltage Address Set-up Time [ts fotos ‘Address Access Time: Vce=5.0#0.25V [=f stye Ps | XIN | u u u u u L Tomeemennenenen eens a i A High-Z Aoroars (aD-O [70 ) o J OE ta As (2) Program Operation (High speed write mode - I ) (Topr =25 +5°C) [ene [omen ewes | wn | me [om [om] Input High Voltage [vg [OO Veco? [= vee [ inputtow Voltage | vue [Sd (rex |v] Supply Voltage pve fo ss P60 as Tv | Program Supply voltage Vee [To Ps 0 Tv XOUT a a ee A0toA14 (a_| oui (AH {Au ) (01) {00 _) e J. tew Lf CIMA OE Program very} Note: DO; Data output (I0to17) AL ; Address input (A0 to A7) DI; Data input (10 to 17) AH ; Address input (A8 to A14) Note1: When Vcc power supply is turned on or after, Vpp must be increased. When V,- power supply is turned off or before, Vpp must be decreased. Note2: The device must not be set to the EPROM programmer or picked up from it under applying the program voltage (12.5 V +0.5 V) to the Vpp pin as the device is damaged. Note3: Be sure to execute the recommended programing mode with the recommended programing adaptor. If a mode or an adaptor except the above, the misoperation sometimes occurs. 3-09-99 2002-01-08

(3) Program Operation (High speed write mode -II) (Topr = 25 + 5°C) [raat | sot | conans | tn ftv |e || Povme fo ecexo? [vce TT Input Low Voltage PMs [oP ecco. Tv [-supplyVoltage + vee | nes | Program Supply Voltage a es =6.25V£0. XOUT i A0toA14 Cal} fotel7 CAH) At C01) {__90__) ae tow cE t Y LO WLM OE Program [___Verty | Note: DO, Data output (10 to17) AL; Address input (AO to A7) DI; Data input (10 to 17) AH ; Address input (A8 to A14) Note1: When Vcc power supply is turned on or after, Vpp must be increased. When V< power supply is turned off or before, Vpp must be decreased. Note2: The device must not be set to the EPROM programmer or picked up from it under applying the program voltage (12.5 V +0.5 V) to the Vpp pin as the device is damaged. Note3: Be sure to execute the recommended programing mode with the recommended programing adaptor. If a mode or an adaptor except the above, the misoperation sometimes occurs. 3-09-100 2002-01-08

P-SDIP28-400-1.78 Unit: mm A pooeoonnoons 5 ) 7] & Soa aos SSS Se 8 1 14 26.1MAX po pg og AAR AMTAMIAA AE 38] ry ry HH oe san mht I | \\) (commercial samples and products). PKG-1 2002-01-08

P-SOP28-450-1.27 Unit: mm 28 15 it 14 osebrve tl hese: goss e250 19.0MAX 18.540.2 er ee ne Fs] CIOs a = 3 g 1,020.2 q € TILL STINKS Note: Aceramic package (engineering samples) is different in dimensions from above plastic package (commercial samples and products). PKG-2 2002-01-08