87C754

83C754 PHILIPS

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/C0109 /C0110 /C0114 83C754/87C754 80C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference Preliminary specification Supersedes data of 1997 Dec 03 IC20 Data Handbook

1998 Apr 23

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

21998 Apr 23

DESCRIPTION

The Philips 83C754/87C754 offers many of the advantages of the 80C51 architecture in a small package and at low cost. The 8XC754 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up senitivity. The 8XC754 contains a 4k × 8 ROM (83C754) EPROM (87C754), a single module PCA, a 256 × 8 RAM, 11 I/O lines, two 16-bit counter/timers, a two-priority level interrupt structure, a full duplex serial channel, an on-chip oscillator, and an 8-bit D/A converter. The EPROM version of this device, the 87C754, is available in plastic one-time programmable (OTP) packages. Once the array has been programmed, it ifs functionally equivalent to the masked ROM 83C754. Thus, unless explicitly stated otherwise, all references made to the 87C754 apply equally to the 83C754. The 8XC754 supports two power reduction modes of operation referred to as the idle mode and the power-down mode.

FEATURES

• Available in erasable quartz lid or One-Time Programmable plastic packages
• 80C51-based architecture
• Small package sizes – 28-pin SSOP
• Wide oscillator frequency range
• Power control modes: – Idle mode – Power-down mode
• 4k × 8 ROM (83C754) EPROM (87C754)
• 256 × 8 RAM
• Two 16-bit auto reloadable counter/timers
• Single module PCA counter/timer
• Full duplex serial channel
• Boolean processor
• CMOS and TTL compatible PIN CONFIGURATION 12 17 28RxD/T0/P3.4/D4 TxD/T1/P3.5/D5 ECI/P3.6/D6 INT1/P3.7/D7 RST VSS ZIN/A2/A10 YIN/A3/A11 XIN/A4 P3.3/D3 P3.2/D2 P3.1/D1 P3.0/D0 INT0/P1.0/A0/A8 CEX/P1.1/A1/A9 VCC XYDAC/A7 VPP /P1.2 ZDAC/ASEL XYSOURCE/A6 XYDACBIAS/PGMXYZRAMP/A5 13 16 VREGAV SS 14 15 DECOUPLEAV CC SU00665D CERAMIC DUAL IN-LINE PACKAGE AND PLASTIC SHRINK SMALL OUTLINE PACKAGE PART NUMBER SELECTION ROM EPROM 1 TEMPERATURE RANGE °C AND PACKAGE FREQUENCY DRAWING NUMBER P83C754EBD DB P87C754EBD DB OTP 0 to +70, 28-pin Shrink Small Outline Package3.5 to 16MHz SOT341-1 NOTE: 1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM.

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 3

INTERRUPT, SERIAL PORT AND TIMER BLOCKS DACAV SS AV CC RAM ADDR REGISTER STACK POINTER PROGRAM ADDRESS REGISTER PC INCRE- MENTER PROGRAM COUNTER PORT 3 DRIVERS PORT 1 DRIVERS PORT 3 LATCH PORT 1 LATCH TIMING AND CONTROL B REGISTER SU00666D ANALOG XIN XYZRAMP DECOUPLE VREG XYDACBIAS XYSOURCE ZDAC XYDAC

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 4

PIN NO. TYPE NAME AND FUNCTION VSS 8 I Circuit Ground Potential. VCC 22 I Supply voltage during normal, idle, and power-down operation. have 1s written to them can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups (P1.0, P1.1). (See DC Electrical Characteristics: IIL). Port 1 also serves the special function features listed below (Note: P1.0 does not have the strong pullup that is on for 2 oscillator periods.): 24 I INT0 (P1.0): External interrupt 0. 23 O CEX (P1.1): PCA clock output. 21 I VPP (P1.2): Programming voltage input (open drain). P3.0–P3.7 1–4, 25–28 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also functions as the data input for the EPROM memory location to be programmed (or verified). (Note: P3.5 does not have the strong pullup that is on for 2 oscillator periods.) Port 3 also serves the special function as listed below: 3 I ECI (P3.6): External PCA clock input. 1 I RxD/T0 (P3.4):Serial port receiver data input. Timer 0 external clock input. 4 I INT1: External interrupt 1. 2 I TxD/T1 (P3.5):Serial port transmitter data. Timer 1 external clock input. RST 5 I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and VPP to be applied for programming or verification purposes. The RESET serial sequence must be synchronized with the X1 input. (Note: The 83/87C754 does not have an internal reset resistor.) X1 7 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state. X2 6 O Crystal 2: Output from the inverting oscillator amplifier. AV CC 1 14 I Analog supply voltage and reference input. AV SS 1 13 I Analog supply and reference ground. ZIN 9 I ZIN: Input to analog multiplexer. YIN 10 I YIN: Input to analog multiplexer. XIN 11 I XIN: Input to analog multiplexer. XYZRAMP 12 O XYZRAMP: Provides a low impedance pulldown to VSS under S/W control. DECOUPLE 15 O Decouple: Output from regulated supply for connection of decoupling capacitors. VREG 16 O VREG: Provides regulated analog supply output. XYDACBIAS 17 O XYDACBIAS: Provides source voltage for bias of external circuitry. – Input which specifies verify mode (output enable) or the program mode. /PGM = 1 output enabled (verify mode). /PGM = 0 program mode. XYSOURCE 18 O XYSOURCE: Provides source voltage from regulated analog supply. ZDAC 19 O ZDAC: Switchable outp from the internal DAC. ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3. ASEL = 0 low address byte available on port 3. ASEL = 1 high address byte available on port 3 (only the three least significant bits are used). XYDAC 20 O XYDAC: Non-switchable output from the internal DAC. NOTE: 1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be in the range 4.5V to 5.5V.

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amplifier which can be configured for use as an on-chip oscillator. voltages before a D/A conversion is started. independent 8-bit registers. instruction to invoke power-down is the last instruction executed. Table 1. External Pin Status During Idle and SBUF accesses a physically separate receive register. baud rate is fixed at 1/12 the oscillator frequency. Function Register SCON. The baud rate is variable. either 1/32 or 1/64 the oscillator frequency. rate. the baud rate in Mode 3 is variable. other modes by the incoming start bit if REN = 1.

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receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). the value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency.

32 Oscillator Frequency

received. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. modes, in any serial transmission. Must be cleared by software. modes, in any serial reception (except see SM2). Must be cleared by software. Figure 2. Timer 1 Generated Commonly Used Baud Rates

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 7

DIFFERENCES BETWEEN THE 8XC754 AND THE 80C51 Program Memory On the 8XC754, program memory is 4096 bytes long and is not externally expandable, so the 80C51 instructions MOVX, LJMP, and LCALL are not implemented. If these instructions are executed, the appropriate number of instruction cycles will take place along with external fetches; however, no operation will take place. The LJMP may not respond to all program address bits. The only fixed locations in program memory are the addresses at which execution is taken up in response to reset and interrupts, which are as follows: Program Memory Event Address Reset 000 External INT0 003 Timer 0 00B External INT1 013 PCA 01B SIO/TF1 023 Memory Organization The 8XC754 manipulates operands in three memory address spaces. The first is the program memory space which contains program instructions as well as constants such as look-up tables. The program memory space contains 4k bytes in the 8XC754. The second memory space is the data memory array which has a logical address space of 256 bytes. The third memory space is the special function register array having a 128-byte address space (80H to FFH). Only selected locations in this memory space are used (see Table 2). Note that the architecture of these memory spaces (internal program memory, internal data memory, and special function registers) is identical to the 80C51, and the 8XC754 varies only in the amount of memory physically implemented. The 8XC754 does not directly address any external data or program memory spaces. For this reason, the MOVX instructions in the 80C51 instruction set are not implemented in the 83C754, nor are the alternate I/O pin functions RD and WR. I/O Ports The I/O pins provided by the 8XC754 consist of port 1 and port 3. Port 1 Port 1 is a 3-bit bidirectional I/O port and includes alternate functions on some pins of this port. P1.1 is provided with internal pullups while the remaining pins (P1.0 and P1.2) are an open drain output structure. The alternate functions for port 1 are: INT0 – External interrupt 0. PCAOUT – PCA clock output V PP – External programming voltage. Port 3 Port 3 is an 8-bit bidirectional I/O port structure. P3.5 is open drain. The alternate functions for port 3 are: RxD – Serial port receiver data input. T1 – Timer 1 external clock input. INT1 – External interrupt 1. TxD – Serial port transmitter data. T0 – Timer 0 external clock input. ECI – PCA external clock input. Analog Section The analog section of the 8XC754, shown in Figure 3, consists of four major elements: a bandgap referenced voltage regulator, an 8-bit DAC, an input multiplexer and comparator, and a low impedance pulldown device. The bandgap voltage regulator uses the AV CC pin as its supply and produces a regulated output on the VREG pin. The bandgap reference is enabled/disabled by AC0. The regulator also supplies the analog supply voltage for the DAC. The regulator may be switched on/off by means of the AC1 bit in the analog control register (ACON0). The regulator output may also be supplied to the XYDACBIAS and XYSOURCE pins by means of bits AC3 and AC4, respectively. The DECOUPLE pin is provided for decoupling the regulator output. The DAC is an 8-bit device and its output appears on the XYDAC pin. In addition, the DAC output may also be routed to the ZDAC pin by means of bit AC6 in the ACON0 register. The DAC output is not buffered, so external load impedances should be taken into consideration when using either of these outputs. A 3-input multiplexer is provided, whose output is connected to the positive reference of a comparator. The multiplexer output is controlled by bits MUX2:0 of ACON1. A bandgap reference supplies the negative reference of the comparator. The output of the comparator may be used the trigger the capture input of PCA module. A low impedance pulldown is supplied at the XYZRAMP pin and is controlled by bit AC5 of ACON0. Interrupt Subsystem—Fixed Priority The interrupt structure is a seven-source, two-level interrupt system. Simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows: Highest priority:Pin INT0 Timer flag 0 Pin INT1 Lowest priority: Pin INT1 PCA Serial I/O – TF1 The vector addresses are as follows: Source Vector Address INT0 0003H TF0 000BH INT1 0013H PCA 001BH SIO/TF1 0023H Interrupt Enable Register MSB LSB EA – – ES/T1 EC EX1 ET0 EX0 Position Symbol Function IE.7 EA Global interrupt disable when EA = 0 IE.6 – IE.5 – IE.4 ES/T1 Serial port/Timer Flag 1 IE.3 EC PCA interrupt IE.2 EX1 External interrupt 1 IE.1 ET0 Timer 0 overflow IE.0 EX0 External interrupt 0

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Figure 3. Analog Section Figure 4. Typical Port Bit Latches and I/O Buffers

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Table 2. 8XC754 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

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modulator. The basic PCA configuration is shown in Figure 5. In the CMOD SFR are three additional bits associated with the PCA. functions are shown in Figure 6. ECOM (CCAPM.6) when set enables the comparator function. Figure 11 shows the CCAPM settings for the various PCA functions. There are two additional registers associated with the PCA module. the 16-bit count when a capture occurs or a compare should occur. used to control the duty cycle of the output. generated. Refer to Figure 12. independently variable using the module’s capture register CCAPL. module’s CCAPM register must be set to enable the PWM mode.

16 BITS

Figure 5. Programmable Counter Array (PCA)

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Figure 6. PCA Timer/Counter Figure 7. PCA Interrupt System

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it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module. WDTE = 1 enables it. CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 8. CMOD: PCA Counter Mode Register set. CF may be set by either hardware or software but can only be cleared by software. – Not implemented, reserved for future use*. CCF PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 9. CCON: PCA Counter Control Register

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– Not implemented, reserved for future use*. ECOM Enable Comparator. ECOM = 1 enables the comparator function. CAPP Capture Positive, CAPP = 1 enables positive edge capture. CAPN Capture Negative, CAPN = 1 enables negative edge capture. CCON to be set, flagging an interrupt. PWM Pulse Width Modulation Mode. PWM4 = 1 enables the CEX pin to be used as a pulse width modulated output. ECCF Enable CCF interrupt. Enables compare/capture flag CCF in the CCON register to generate an interrupt. bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 10. CCAPM: PCA Modules Compare/Capture Registers Figure 11. PCA Module Modes (CCAPM Register) Figure 12. PCA Capture Mode

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Figure 13. PCA Compare Mode Figure 14. PCA High Speed Output Mode

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Figure 15. PCA PWM Mode Figure 16. PCA Watchdog Timer

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 16

ABSOLUTE MAXIMUM RATINGS 1, 3, 4 PARAMETER RATING UNIT Storage temperature range –65 to +150 °C Voltage from VCC to VSS –0.5 to +6.5 V Voltage from any pin to VSS (except VPP ) –0.5 to VCC + 0.5 V Power dissipation 1.0 W Voltage from VPP pin to VSS –0.5 to + 13.0 V DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, AVCC = 5V ±5, AVSS = 0V4 VCC = 5V ± 10%, VSS = 0V SYMBOL PARAMETER TEST CONDITIONS LIMITS4 UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT ICC Supply current (see Figure 19) Inputs VIL Input low voltage, port 1, 3 –0.5 0.2VCC –0.1 V VIH Input high voltage, port 1, 3 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, X1, RST 0.7VCC VCC +0.5 V Outputs VOL Output low voltage, port 3 IOL = 1.6mA2 0.45 V VOH Output high voltage, ports 3, 1.0, 1.1 IOH = –60µA, 2.4 V ILI Input leakage current, port 1, 3, RST 0.45 < VIN < VCC +10 µA IIL Logical 0 input cirrent, ports 1 and 3 VIN = 0.45V –50 µA C IO Pin capacitance Test freq = 1MHz, Tamb = 25°C 10 pF IPD Power-down current5 VCC = 2 to 5.5V VCC = 2 to 6.0V (83C754) 50 µA VPP VPP program voltage (87C754 only) VSS = 0V VCC = 5V±10% Tamb = 21°C to 27°C 12.5 13.0 V IPP Program current (87C754 only) VPP = 13.0V 50 mA NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10mA Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 67mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 5. Power-down ICC is measured with all output pins disconnected; port 0 = VCC ; X2, X1 n.c.; RST = VSS . RST = port 0 = VCC . ICC will be slightly higher if a crystal oscillator is used. port 0 = VCC ; RST = VSS . 8. Load capacitance for ports = 80pF.

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 17

ANALOG SECTION ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, AVCC = 5V ±5, AVSS = 0V4 VCC = 5V ± 10%, VSS = 0V SYMBOL PARAMETER TEST CONDITIONS LIMITS4 UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Analog Inputs (D/A guaranteed only with quartz window covered.) AV CC Analog supply voltage 4.5 – 5.5 V Sensor resistor 330 – 3K Ω IAVCC AC0 = 0 IC only – 0.88 1.5 mA AC0 = 1 – – 10 µA Regulator VREG 3.6 3.8 4.0 V IVREG 13 – 55 mA CDECOUPLE Stability requirement 3 10 – µF RDSONQ1 – 7 – Ω ILEAKAGEQ1 – TBD – µA ILEAKAGEQ2 – TBD – µA PSRR 100Hz – –40 – dB VREGREJ VREG rejection of 1 Volt AVCC step change –100 – 100 mV TVREG VREG turn on time Q1 off, 330Ω sensor – 2 5 ms MUX and Comparator Comparator trip point 1.14 1.26 1.38 V Comparator delay input 0.04V/µs – 50 – ns Comparator delay change AV CC 4.5 to 5.5V –10 2 10 ns MUX impedance – 1 – kΩ ILEAKAGEMUX – TBD – µA Digital-to-Analog Conversion ZDAC, XYDAC monotonicity 0 – – bits ZDAC, XYDAC impedance – 10 – kΩ DAC selection switch impedance – 40 – Ω DAC settling – 1 – µs ZDAC switch impedance – 50 – Ω ZDAC switch impedance change AV CC 4.5 to 5.5V –20 – 20 Ω ZDAC switch leakage – TBD – µA Switches XYZRAMP impedance – 25 100 Ω XYZRAMP impedance change AV CC 4.5 to 5.5V –25 – 25 Ω XYZRAMP leakage – TBD – µA XYZRAMP discharge to 1LSB (1.6mV) – 1.5 10 µs XYZRAMP delay turn on time – 6 50 ns XYZRAMP start time change AV CC 4.5 to 5.5V –10 – 10 ns XYDACBIAS impedance – 7 13 Ω XYDACBIAS leakage – TBD – µA XYDACBIAS switching time – 130 1000 ns XYSOURCE impedance – 150 300 Ω XYSOURCE impedance change AV CC 4.5 to 5.5V –100 – 100 Ω XYSOURCE leakage – TBD – µA XYSOURCE switching time – 30 500 ns

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indicate the name of a signal or the logical status of that signal. Figure 17. External Clock Drive Figure 18. AC Testing Input/Output

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Figure 19. ICC vs. FREQ Maximum I CC values taken at VCC = 5.5V and worst case temperature. Typical ICC values taken at VCC = 5.0V and 25°C. Notes 6 and 7 refer to AC Electrical Characteristics.

1. 64 byte ROM encryption key
2. External MOVC is disabled, and

Security Bit 2: When programmed, this bit inhibits Verify User ROM. If the ROM Code file does not include the options, the following information must be included with the ROM code. Encryption: No Yes If Yes, must send key file.

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 20

PROGRAMMING CONSIDERATIONS EPROM Characteristics The 87C754 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices such as the 87C751 and 87C752. Figure 20 shows a block diagram of the programming configuration for the 87C754. Port pin P0.2 is used as the programming voltage supply input (V PP signal). Port pin P0.1 is used as the program (PGM/) signal. This pin is used for the 5 programming pulses. Port 3 is used as the address input for the byte to be programmed and accepts both the high and low components of the eleven bit address. Multiplexing of these address components is performed using the ASEL input. The user should drive the ASEL input high and then drive port 3 with the high order bits of the address. ASEL should remain high for at least 13 clock cycles. ASEL may then be driven low which latches the high order bits of the address internally. The high address should remain on port 3 for at least two clock cycles after ASEL is driven low. Port 3 may then be driven with the low byte of the address. The low address will be internally stable 13 clock cycles later. The address will remain stable provided that the low byte placed on port 3 is held stable and ASEL is kept low. Note: ASEL needs to be pulsed high only to change the high byte of the address. Port 1 is used as a bidirectional data bus during programming and verify operations. During programming mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the EPROM location specified by the address which has been supplied to Port 3. The XTAL1 pin is the oscillator input and receives the master system clock. This clock should be between 1.2 and 16MHz. The RESET pin is used to accept the serial data stream that places the 87C754 into various programming modes. This pattern consists of a 10-bit code with the LSB sent first. Each bit is synchronized to the clock input, X1. Programming Operation Figures 21 and 22 show the timing diagrams for the program/verify cycle. RESET should initially be held high for at least two machine cycles. P0.1 (PGM/) and P0.2 (V PP ) will be at VOH as a result of the RESET operation. At this point, these pins function as normal quasi-bidirectional I/O ports and the programming equipment may pull these lines low. However, prior to sending the 10-bit code on the RESET pin, the programming equipment should drive these pins high (V IH). The RESET pin may now be used as the serial data input for the data stream which places the 87C754 in the programming mode. Data bits are sampled during the clock high time and thus should only change during the time that the clock is low. Following transmission of the last data bit, the RESET pin should be held low. Next the address information for the location to be programmed is placed on port 3 and ASEL is used to perform the address multiplexing, as previously described. At this time, port 1 functions as an output. A high voltage V PP level is then applied to the VPP input (P0.2). (This sets Port 1 as an input port). The data to be programmed into the EPROM array is then placed on Port 1. This is followed by a series of programming pulses applied to the PGM/ pin (P0.1). These pulses are created by driving P0.1 low and then high. This pulse is repeated until a total of 5 programming pulses have occurred. At the conclusion of the last pulse, the PGM/ signal should remain high. The V PP signal may now be driven to the VOH level, placing the 87C754 in the verify mode. (Port 1 is now used as an output port). After four machine cycles (48 clock periods), the contents of the addressed location in the EPROM array will appear on Port 1. The next programming cycle may now be initiated by placing the address information at the inputs of the multiplexed buffers, driving the V PP pin to the VPP voltage level, providing the byte to be programmed to Port1 and issuing the 5 programming pulses on the PGM/ pin, bringing VPP back down to the VC level and verifying the byte. Programming Modes The 87C754 has four programming features incorporated within its EPROM array. These include the USER EPROM for storage of the application’s code, a 64-byte encryption key array and two security bits. Programming and verification of these four elements are selected by a combination of the serial data stream applied to the RESET pin and the voltage levels applied to port pins P0.1 and P0.2. The various combinations are shown in Table 3. Encryption Key Table The 87C754 includes a 64-byte EPROM array that is programmable by the end user. The contents of this array can then be used to encrypt the program memory contents during a program memory verify operation. When a program memory verify operation is performed, the contents of the program memory location is XNOR’ed with one of the bytes in the 64-byte encryption table. The resulting data pattern is then provided to port 1 as the verify data. The encryption mechanism can be disabled, in essence, by leaving the bytes in the encryption table in their erased state (FFH) since the XNOR product of a bit with a logical one will result in the original bit. The encryption bytes are mapped with the code memory in 64-byte groups. the first byte in code memory will be encrypted with the first byte in the encryption table; the second byte in code memory will be encrypted with the second byte in the encryption table and so forth up to and including the 64th byte. The encryption repeats in 64-byte groups; the 65th byte in the code memory will be encrypted with the first byte in the encryption table, and so forth. Security Bits Two security bits, security bit 1 and security bit 2, are provided to limit access to the USER EPROM and encryption key arrays. Security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. Additional programming of the USER EPROM is inhibited. 2. Additional programming of the encryption key is inhibited. 3. Verification of the encryption key is inhibited. 4. Verification of the USER EPROM and the security bit levels may still be performed. (If the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. Such programming would provide data during a verify cycle that is the logical complement of the USER EPROM contents). Security bit 2, the verify inhibit bit, prevents verification of both the USER EPROM array and the encryption key arrays. The security bit levels may still be verified.

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address or data information to the 87C754 on ports 1 and 3. results of the verify operation will appear on ports 1.6 and 1.7. light with wavelengths shorter than approximately 4,000 angstroms. Erasure leaves the array in an all 1s state. Table 3. Implementing Program/Verify Modes

• Pulsed from VIH to VIL and returned to VIH.

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1. Address should be valid at least 24tCLCL before the rising edge of VPP.
2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.

Figure 20. Programming Configuration

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Figure 21. Entry into Program/Verify Modes

5 PULSES

Figure 22. Program/Verify Cycle

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 24

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT341-1

Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

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Philips Semiconductors Preliminary specification 83C754/87C75480C51 8-bit microcontroller family 4K/256 OTP/ROM, DAC, comparator, UART, reference

1998 Apr 23 26

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 03892 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.