83C748 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 83C748/87C748 80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count Preliminary specification Supersedes data of 1998 Apr 23 IC20 Data Handbook
1999 Apr 15
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
21999 Apr 15
DESCRIPTION
The Philips 83C748/87C748 offers the advantages of the 80C51 architecture in a small package and at low cost. The 8XC748 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity. The 8XC748 contains a 2k × 8 ROM (83C748) EPROM (87C748), a 64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a four-source, fixed-priority level interrupt structure, and an on-chip oscillator.
FEATURES
- 80C51 based architecture
- Small package sizes – 24-pin DIP (300 mil “skinny DIP”) – 24-pin Shrink Small Outline Package (SSOP) – 28-pin PLCC
- 87C748 available in erasable quartz lid or one-time programmable plastic packages
- Wide oscillator frequency range: –3.5 to 16MHz
- Low power consumption: – Normal operation: less than 11mA @ 5V, 12MHz – Idle mode – Power-down mode
- 2k × 8 ROM (83C748) 2k × 8 EPROM (87C748)
- 64 × 8 RAM
- 16-bit auto reloadable counter/timer
- 10-bit fixed-rate timer
- Boolean processor
- CMOS and TTL compatible
- Well suited for logic replacement, consumer and industrial
applications
- LED drive outputs PIN CONFIGURATIONS 12 13 24P3.4/A4 P3.3/A3 P3.2/A2/A10 P3.1/A1/A9 P3.0/A0/A8 P0.2/VPP RST VSS P0.0/ASEL P1.0/D0 P1.1/D1 P1.2/D2 P1.3/D3 P1.4/D4 P1.5/INT0 /D5 P1.6/INT1/D6 P1.7/T0/D7 P3.7/A7 P3.6/A6 P3.5/A5 V CC PLASTIC DUAL IN-LINE AND SHRINK SMALL OUTLINE PACKAGE PLASTIC LEADED CHIP CARRIER 41 2 6 12 18 P0.1/OE–PGM Pin Function 1 P3.4/A4 2 P3.3/A3 3 P3.2/A2/A10 4 P3.1/A1/A9
5 NC*
6 P3.0/A0/A8 7 P0.2/V PP 8 P0.1/OE-PGM 9 P0.0/ASEL
10 NC*
11 RST
15 P1.0/D0 16 P1.1/D1 17 P1.2/D2 18 P1.3/D3 19 P1.4/D4 20 P1.5/INT0 /D5
21 NC*
22 NC*
23 P1.6/INT1 /D6 24 P1.7/T0/D7 25 P3.7/A7 26 P3.6/A6 27 P3.5/A5 28 V CC SU00295A* NO INTERNAL CONNECTION
ORDERING INFORMATION
ROM EPROM 1 TEMPERATURE RANGE °C AND PACKAGE FREQUENCY MHz DRAWING NUMBER P83C748EBP N P87C748EBP N OTP 0 to +70, Plastic Dual In-line Package 3.5 to 16 SOT222-1 P83C748EBA A P87C748EBA A OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16 SOT261-3 P83C748EBD DB P87C748EBD DB OTP 0 to +70, Shrink Small Outline Package 3.5 to 16 SOT340-1 NOTE: 1. OTP = One Time Programmable EPROM.
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
1999 Apr 15 3
P0.0–P0.2 PORT 0 DRIVERS RAM ADDR REGISTER PORT 0 LATCH STACK POINTER PROGRAM ADDRESS REGISTER PC INCRE- MENTER PROGRAM COUNTER PORT 3 DRIVERS PORT 1 DRIVERS PORT 3 LATCH PORT 1 LATCH TIMING AND CONTROL B REGISTER SU00296
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
1999 Apr 15 4
PIN NO. MNEMONIC DIP/ SSOP LCC TYPE NAME AND FUNCTION VSS 12 14 I Circuit Ground Potential VCC 24 28 I Supply voltage during normal, idle, and power-down operation. P0.0–P0.2 8–6 9–7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. These pins are driven low if the port register bit is written with a 0. The state of the pin can always be read from the port register by the program. P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from “standard TTL” characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0 also provides alternate functions for programming the EPROM memory as follows: 6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1). 7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode. OE/PGM = 1 output enabled (verify mode). OE/PGM = 0 program mode. 8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3. ASEL = 0 low address byte available on port 3. ASEL = 1 high address byte available on port 3 (only the three least significant bits are used). 23, 24 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the value to program into the selected address during the program mode. Port 1 also serves the special function features of the 80C51 family as listed below: 18 20 I INT0 (P1.5): External interrupt. 19 23 I INT1 (P1.6): External interrupt. 20 24 I T0 (P1.7): Timer 0 external input. P3.0–P3.7 5–1, 23–21 6, 4–1, 27–25 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also functions as the address input for the EPROM memory location to be programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL. RST 9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC . After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the programming state allowing programming address, data and VPP to be applied for programming or verification purposes. The RESET serial sequence must be synchronized with the X1 input. X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state. X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: 1. When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to VCC via a small pull-up (e.g. 2k). ABSOLUTE MAXIMUM RATINGS 1, 2 PARAMETER RATING UNIT Storage temperature range –65 to +150 °C Voltage from VCC to VSS –0.5 to +6.5 V Voltage from any pin to VSS (except VPP ) –0.5 to VCC + 0.5 V Power dissipation 1.0 W Voltage on VPP pin to VSS 0 to +13.0 V Maximum IOL per I/O pin 10 mA NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
1999 Apr 15 5
DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1 SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT VIL Input low voltage –0.5 0.2VDD –0.1 V VIH Input high voltage, except X1, RST 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, X1, RST 0.7VCC VCC +0.5 V P0.2 VIL1 Input low voltage –0.5 0.3VCC V VIH2 Input high voltage 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1 and 3 IOL = 1.6mA2 0.45 V VOL1 Output low voltage, port 0.2 IOL = 3.2mA2 0.45 V VOH Output high voltage, ports 1 and 3 IOH = –60µA 2.4 V IOH = –25µA 0.75VCC V IOH = –10µA 0.9VCC V Port 0.0 and 0.1 – Drivers VOL2 Output low voltage IOL = 3mA 0.4 V Driver, receiver combined: (over VCC range) C Capacitance 10 pF IIL Logical 0 input current, ports 1 and 3 VIN = 0.45V –50 µA ITL Logical 1 to 0 transition current, ports 1 and 33 VIN = 2V (0 to 70°C) –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC ±10 µA R RST Internal pull-down resistor 25 175 kΩ C IO Pin capacitance Test freq = 1MHz, Tamb = 25°C 10 pF IPD Power-down current4 VCC = 2 to VCC max 50 µA VPP VPP program voltage (for 87C748 only) VSS = 0V VCC = 5V±10% Tamb = 21°C to 27°C 12.5 13.0 V IPP Program current (for 87C748 only) VPP = 13.0V 50 mA ICC Supply current (see Figure 2) NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10mA Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 67mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 4. Power-down ICC is measured with all output pins disconnected; port 0 = VCC ; X2, X1 n.c.; RST = VSS . RST = port 0 = VCC . ICC will be slightly higher if a crystal oscillator is used. port 0 = VCC ; RST = VSS .
1999 Apr 15 6
- Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
- Load capacitance for ports = 80pF.
Figure 1. External Clock Drive
1999 Apr 15 7
Figure 2. ICC vs. FREQ Maximum I CC values taken at VCC max and worst case temperature. Typical ICC values taken at VCC = 5.0V and 25°C. Notes 5 and 6 refer to DC Electrical Characteristics. amplifier which can be configured for use as an on-chip oscillator. machine cycles (24 oscillator periods), while the oscillator is running. CC and RST must come up at the same time for a proper start-up. the same manner as a power-on reset. instruction to invoke power-down is the last instruction executed. Table 1. External Pin Status During Idle and
1999 Apr 15 8
RAM overlapped with the 128-byte special function register area. pre-incremented on a PUSH instruction). counter are centralized in a single register called TCON. locations, and reset values. is no need for the IP SFR, so it is not used. SBUF have also been removed. independent 8-bit registers. Figure 3. Memory Map
1999 Apr 15 9
Table 2. 8XC748 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs. 80C51 but does not include address/data input and output circuitry. bidirectional with no internal pullups. interrupt is enabled, will generate an interrupt.
1999 Apr 15 10
0 – Timer/counter is enabled when TR is 1. C/T 1 – Counter/timer operation from T0 pin. 0 – Timer operation from internal clock. TF 1 – Set on overflow of TH. TR 1 – Timer/counter enabled. IE0 1 – Edge detected in INT0 . IT0 1 – INT0 is edge triggered. 0 – INT0 is level sensitive. IE1 1 – Edge detected on INT1 . IT1 1 – INT1 is edge triggered. 0 – INT1 is level sensitive. flags are therefore combined into one register. from the positions used in the standard 80C51 TCON register. interrupt service routine and elsewhere must be explicitly saved). The interrupt structure is a four-source, one-level interrupt system. below in their order of polling sequence priority. are based on the 80C51 interrupt architecture. EX1 IE.2 Enables or disables external interrupt 1. If EX1 = 0, external interrupt 1 is disabled. EX0 IE.0 Enables or disables external interrupt 0. If EX0 = 0, external interrupt 0 is disabled. Figure 4. 83C748 Counter/Timer Block Diagram
1999 Apr 15 11
stream is used to place the 87C748 in the programming mode. (PGM/) signal. This pin is used for the 25 programming pulses. driven low which latches the high order bits of the address internally. clock. This clock should be between 1.2 and 6MHz. transmission of the last data bit, the RESET pin should be held low. PP level is then applied to the VPP input (P0.2). the conclusion of the last pulse, the PGM/ signal should remain high. 87C748 in the verify mode. (Port 1 is now used as an output port). addressed location in the EPROM array will appear on Port 1. P0.2. The various combinations are shown in Table 3. Table 3. Implementing Program/Verify Modes
- Pulsed from VIH to VIL and returned to VIH.
resulting data pattern is then provided to port 1 as the verify data. encrypted with the first byte in the encryption table, and so forth.
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
1999 Apr 15 12
Two security bits, security bit 1 and security bit 2, are provided to limit access to the USER EPROM and encryption key arrays. Security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. Additional programming of the USER EPROM is inhibited. 2. Additional programming of the encryption key is inhibited. 3. Verification of the encryption key is inhibited. 4. Verification of the USER EPROM and the security bit levels may still be performed. (If the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. Such programming would provide data during a verify cycle that is the logical complement of the USER EPROM contents). Security bit 2, the verify inhibit bit, prevents verification of both the USER EPROM array and the encryption key arrays. The security bit levels may still be verified. Programming and Verifying Security Bits Security bits are programmed employing the same techniques used to program the USER EPROM and KEY arrays using serial data streams and logic levels on port pins indicated in Table 3. When programming either security bit, it is not necessary to provide address or data information to the 87C748 on ports 1 and 3. Verification occurs in a similar manner using the RESET serial stream shown in Table 3. Port 3 is not required to be driven and the results of the verify operation will appear on ports 1.6 and 1.7. Ports 1.7 contains the security bit 1 data and is a logical one if programmed and a logical zero if not programmed. Likewise, P1.6 contains the security bit 2 data and is a logical one if programmed and a logical zero if not programmed. EPROM PROGRAMMING AND VERIFICATION Tamb = 21°C to +27°C, VCC = 5V ±10%, VSS = 0V SYMBOL PARAMETER MIN MAX UNIT 1/tCLCL Oscillator/clock frequency 1.2 6 MHz tAVGL 1 Address setup to P0.1 (PROG–) low 10µs + 24tCLCL tGHAX Address hold after P0.1 (PROG–) high 48tCLCL tDVGL Data setup to P0.1 (PROG–) low 38tCLCL tGHDX Data hold after P0.1 (PROG–) high 36tCLCL tSHGL VPP setup to P0.1 (PROG–) low 10 µs tGHSL VPP hold after P0.1 (PROG–) 10 µs tGLGH P0.1 (PROG–) width 90 110 µs tAVQV 2 VPP low (VCC ) to data valid 48tCLCL tGHGL P0.1 (PROG–) high to P0.1 (PROG–) low 10 µs tMASEL ASEL high time 13tCLCL tHAHLD Address hold time 2tCLCL tHASET Address setup to ASEL 13tCLCL tADSTA Low address to valid data 48tCLCL NOTES: 1. Address should be valid at least 24tCLCL before the rising edge of P0.2 (VPP ). 2. For a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.
1999 Apr 15 13
Figure 5. Programming Configuration Figure 6. Entry into Program/Verify Modes
25 PULSES
Figure 7. Program/Verify Cycle
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count
1999 Apr 15 14
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count
1999 Apr 15 15
PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count
1999 Apr 15 16
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count
1999 Apr 15 17
Philips Semiconductors Preliminary specification 83C748/87C74880C51 8-bit microcontroller family, 2K/64 OTP/ROM, low pin count
1999 Apr 15 18
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 04-99 Document order number: 9397 750 05736 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.