87C652

87C652 PHILIPS | Alldatasheet

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Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 87C652/87C654 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C Product specification Replaces data sheets 87C652 of 1998 May 01 and 87C654 of 1998 May 01 IC20 Data Handbook

1999 Jul 23

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

21999 Jul 23 853-1689 22042

DESCRIPTION

The 87C652/87C654 single-chip 8-Bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C652/87C654 has the same instruction set as the 80C51. Three versions of the derivative exist: 80C652—ROMless 83C652/83C654—8 Kbyte, 16 Kbyte ROM 87C652/87C654—8 Kbyte, 16 Kbyte OTP The ROMless and ROM are in separate datasheets. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 87C654 contains a non-volatile 16k × 8 EPROM and the 87C652 contains an 8k x 8 EPROM. Both have a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, an I 2C interface, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C652/87C654 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs. Multiply and divide instructions require 3 µs.

FEATURES

• 80C51 central processing unit
• 16k × 8 EPROM or 8k x 8 EPROM expandable externally to 64k bytes
• 256 × 8 RAM, expandable externally to 64k bytes
• Two standard 16-bit timer/counters
• Four 8-bit I/O ports
• I2C-bus serial I/O port with byte oriented master and slave functions
• Full-duplex UART facilities
• Power control modes – Idle mode – Power-down mode
• Extended temperature range
• OTP package available
• Two speed ranges – 16 MHz – 20 MHz PIN CONFIGURATIONS 20 21 40P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 SDA/P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC PLASTIC DUAL IN-LINE PACKAGE SU00259

ORDERING INFORMATION

EPROM TEMPERATURE RANGE °C AND PACKAGE FREQ DrawingEPROM TEMPERATURE RANGE C AND PACKAGE MHz g Number S87C654-4N40 0 to +70, Plastic Dual In-line Package 16 SOT129-1 S87C654-4A44 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2 S87C654–4B44 0 to +70, Plastic Quad Flat Pack 16 SOT307-2 S87C654-5N40 –40 to +85, Plastic Dual In-line Package 16 SOT129-1 S87C654-5A44 –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2 S87C654-5B44 –40 to +85, Plastic Quad Flat Pack 16 SOT307-2 S87C654–7N40 0 to +70, Plastic Dual In-line Package 20 SOT129-1 S87C654–7A44 0 to +70, Plastic Leaded Chip Carrier 20 SOT187-2 S87C652-4N40 0 to +70, Plastic Dual In-line Package 16 SOT129-1 S87C652-4A44 0 to +70, Plastic Leaded Chip Carrier 16 SOT187-2 S87C652-4B44 0 to +70, Plastic Quad Flat Pack 16 SOT307-2 S87C652-5A44 –40 to +85, Plastic Leaded Chip Carrier 16 SOT187-2 NOTES: 1. For ROM see 83C654 data sheet and 83C652/80C652 data sheet

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 3

(256 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS I2C SERIAL I/O SDA SCL SHARED WITH PORT 1 T0 T1 COUNTERS XTAL2 XTAL1 FREQUENCY REFERENCE INTERNAL INTERRUPTS INT0 INT1 EXTERNAL INTERRUPTS CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL IN SERIAL OUT SHARED WITH PORT 3 (16K x 8 EPROM) SU00271 LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS VSSVCC ALTERNATE FUNCTIONS RST XTAL1 XTAL2 VPP /EA PROG /ALE PSEN RxD TxD INT0 INT1 WR RD SCL SDA SU00262

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 4

1 NC*

2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6/SCL 9 P1.7/SDA

10 RST

11 P3.0/RxD

12 NC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

23 NC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NC*

/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00260* NO INTERNAL CONNECTION PLASTIC QUAD FLAT PACK PIN FUNCTIONS Pin Function 1 P1.5 2 P1.6/SCL 3 P1.7/SDA

4 RST

5 P3.0/RxD

6 NC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 Pin Function 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NC*

29 EA /VPP

30 P0.7/AD7 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC

39 NC*

40 P1.0 41 P1.1 42 P1.2 43 P.13 44 P1.4 PQFP 44 34 12 22 SU00261* NO INTERNAL CONNECTION

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 5

MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C654. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: P1.6 7 8 2 I/O SCL: I2C-bus serial port clock line. P1.7 8 9 3 I/O SDA: I2C-bus serial port data line. P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EPROM programming. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 87C654 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 1FFFH for 87C652 and 3FFFH for 87C654. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH. This pin also receives the 12.75 V programming supply voltage (VPP ) during EPROM programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.

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Table 1. 8XC652/654 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

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oscillator, as shown in the Logic Symbol. the data sheet must be observed. power-down is the last instruction executed. 8XC552 section of this manual. pull-up structure as found on the 80C51. Table 2. External Pin Status During Idle and Power-Down Mode Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 3. Serial Clock Rates

1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 8

ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Storage temperature range –65 to +150 °C Voltage on EA/VPP to VSS –0.5 to + 13 V Voltage on any other pin to VSS –0.5 to + 6.5 V Input, output current on any single pin ±5 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V SS unless otherwise noted. DEVICE SPECIFICATIONS SUPPLY VOLTAGE (V) FREQUENCY (MHz) TEMPERATURE RANGE TYPE MIN. MAX. MIN. MAX. (°C) S87C652-4 and S87C654-4 4.5 5.5 3.5 16 0 to +70 S87C652-5 and S87C654-5 4.5 5.5 3.5 16 –40 to +85 S87C654–7 4.5 5.5 3.5 20 0 to +70

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 9

DC ELECTRICAL CHARACTERISTICS VSS = 0 V TEST LIMITS SYMBOL PARAMETER PART TYPE CONDITIONS MIN. MAX. UNIT VIL Input low voltage, except EA, P1.6/SCL, P1.7/SDA 0 to +70°C –40 to +85°C –0.5 –0.5 0.2VCC –0.1 0.2VCC –0.15 V V VIL1 Input low voltage to EA 0 to +70°C –40 to +85°C –0.5 –0.5 0.2VCC –0.3 0.2VCC –0.35 V V VIL2 Input low voltage to P1.6/SCL, P1.7/SDA1 –0.5 0.3VCC V VIH Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0 to +70°C –40 to +85°C 0.2VCC +0.9 0.2VCC +1.0 VCC +0.5 VCC +0.5 V V VIH1 Input high voltage, XTAL1, RST 0 to +70°C –40 to +85°C 0.7VCC 0.7VCC +0.1 VCC +0.5 VCC +0.5 V V VIH2 Input high voltage, P1.6/SCL, P1.7/SDA1 0.7VCC 6.0 V VOL Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA IOL = 1.6mA2, 3 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN IOL = 3.2mA2, 3 0.45 V VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA 0.4 V VOH Output high voltage, ports 1, 2, 3 0 to +70°C –40 to +85°C IOH = –60µA IOH = –25µA 2.4 0.75VCC V V VOH1 Output high voltage; port 0 in external bus mode, ALE, PSEN , RST4 0 to +70°C –40 to +85°C IOH = –400µA IOH = –150µA 2.4 0.75VCC V V IIL Logical 0 input current, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA 0 to +70°C –40 to +85°C VIN = 0.45V –50 –75 µA µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA 0 to +70°C –40 to +85°C See note 5 –650 –750 µA µA IL1 Input leakage current, port 0 0.45V < VI < VCC ±10 µA IL2 Input leakage current, P1.6/SCL, P1.7/SDA 0V < VI < 6.0V 0V < VCC < 6.0V ±10 µA µA ICC Power supply current: See note 6 VCC =6.0V Active mode @ 16 MHz7 25 mA Idle mode @ 16 MHz8 6 mA Power down mode9, 10 0 to +70°C 50 µA Power down mode9, 10 –40 to +85°C 135 µA R RST Internal reset pull-down resistor 50 150 kΩ C IO Pin capacitance Freq.=1 MHz 10 pF NOTES: 1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 0.3VCC will be recognized as a logic 0 while an input voltage above 0.7VCC will be recognized as a logic 1. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10 mA per port pin; Maximum IOL = 26 mA total for Port 0; Maximum IOL = 15 mA total for Ports 1, 2, and 3; Maximum IOL = 71 mA total for all output pins. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 4. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 6. See Figures 9 through 11 for ICC test conditions. 7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; 8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; 9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC ; EA = RST = VSS . See Figure 11. 10. 2V ≤ VPD ≤ VCC max.

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 10

AC ELECTRICAL CHARACTERISTICS 1, 2

16 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency Speed Versions 87C654 –4, –5 3.5 16 MHz tLHLL 2 ALE pulse width 85 2tCLCL –40 ns tAVLL 2 Address valid to ALE low 8 tCLCL –55 ns tLLAX 2 Address hold after ALE low 28 tCLCL –35 ns tLLIV 2 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 2 ALE low to PSEN low 23 tCLCL –40 ns tPLPH 2 PSEN pulse width 143 3tCLCL –45 ns tPLIV 2 PSEN low to valid instruction in 83 3tCLCL –105 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 38 tCLCL –25 ns tAVIV 2 Address to valid instruction in 208 5tCLCL –105 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tAVLL 3, 4 Address valid to ALE low 28 tCLCL –35 ns tRLRH 3, 4 RD pulse width 275 6tCLCL –100 ns tWLWH 3, 4 WR pulse width 275 6tCLCL –100 ns tRLDV 3, 4 RD low to valid data in 148 5tCLCL –165 ns tRHDX 3, 4 Data hold after RD 0 0 ns tRHDZ 3, 4 Data float after RD 55 2tCLCL –70 ns tLLDV 3, 4 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 3, 4 Address to valid data in 398 9tCLCL –165 ns tLLWL 3, 4 ALE low to RD or WR low 138 238 3tCLCL –50 3tCLCL +50 ns tAVWL 3, 4 Address valid to WR low or RD low 120 4tCLCL –130 ns tQVWX 3, 4 Data valid to WR transition 3 tCLCL –60 ns tDW 3, 4 Data setup time before WR 288 7tCLCL –150 ns tWHQX 3, 4 Data hold after WR 13 tCLCL –50 ns tRLAZ 3, 4 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns Shift Register tXLXL 5 Serial port clock cycle time3 0.75 12tCLCL µs tQVXH 5 Output data setup to clock rising edge3 492 10tCLCL –133 ns tXHQX 5 Output data hold after clock rising edge3 80 2tCLCL –117 ns tXHDX 5 Input data hold after clock rising edge3 0 0 ns tXHDV 5 Clock rising edge to input data valid3 492 10tCLCL –133 ns External Clock tCHCX 6 High time3 20 20 tCLCL – tLOW ns tCLCX 6 Low time3 20 20 tCLCL – tHIGH ns tCLCH 6 Rise time3 20 20 ns tCHCL 6 Fall time3 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested.

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 11

AC ELECTRICAL CHARACTERISTICS 1, 2

20 MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency: Speed Versions 87C654 –7, –8 3.5 20 MHz tLHLL 2 ALE pulse width 60 2tCLCL –40 ns tAVLL 2 Address valid to ALE low 25 tCLCL –25 ns tLLAX 2 Address hold after ALE low 25 tCLCL –25 ns tLLIV 2 ALE low to valid instruction in 135 4tCLCL –65 ns tLLPL 2 ALE low to PSEN low 25 tCLCL –25 ns tPLPH 2 PSEN pulse width 105 3tCLCL –45 ns tPLIV 2 PSEN low to valid instruction in 90 3tCLCL –60 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 25 tCLCL –25 ns tAVIV 2 Address to valid instruction in 170 5tCLCL –80 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tAVLL 3, 4 Address valid to ALE low 25 tCLCL –25 ns tRLRH 3, 4 RD pulse width 200 6tCLCL –100 ns tWLWH 3, 4 WR pulse width 200 6tCLCL –100 ns tRLDV 3, 4 RD low to valid data in 160 5tCLCL –90 ns tRHDX 3, 4 Data hold after RD 0 0 ns tRHDZ 3, 4 Data float after RD 72 2tCLCL –28 ns tLLDV 3, 4 ALE low to valid data in 250 8tCLCL –150 ns tAVDV 3, 4 Address to valid data in 285 9tCLCL –165 ns tLLWL 3, 4 ALE low to RD or WR low 100 200 3tCLCL –50 3tCLCL +50 ns tAVWL 3, 4 Address valid to WR low or RD low 125 4tCLCL –75 ns tQVWX 3, 4 Data valid to WR transition 20 tCLCL –30 ns tDW 3, 4 Data setup time before WR 220 7tCLCL –130 ns tWHQX 3, 4 Data hold after WR 25 tCLCL –25 ns tRLAZ 3, 4 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 25 75 tCLCL –25 tCLCL +25 ns Shift Register tXLXL 5 Serial port clock cycle time3 0.6 12tCLCL µs tQVXH 5 Output data setup to clock rising edge3 367 10tCLCL –133 ns tXHQX 5 Output data hold after clock rising edge3 40 2tCLCL –60 ns tXHDX 5 Input data hold after clock rising edge3 0 0 ns tXHDV 5 Clock rising edge to input data valid3 367 10tCLCL –133 ns External Clock tCHCX 6 High time3 17 17 tCLCL – tLOW ns tCLCX 6 Low time3 17 17 tCLCL – tHIGH ns tCLCH 6 Rise time3 20 20 ns tCHCL 6 Fall time3 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested.

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 12

AC ELECTRICAL CHARACTERISTICS – I 2C INTERFACE SYMBOL PARAMETER INPUT OUTPUT SCL TIMING CHARACTERISTICS tHD ; STA START condition hold time ≥ 14 tCLCL > 4.0 µs1 tLOW SCL LOW time ≥ 16 tCLCL > 4.7 µs1 tHIGH SCL HIGH time ≥ 14 tCLCL > 4.0 µs1 tRC SCL rise time ≤ 1 µs – 2 tFC SCL fall time ≤ 0.3 µs < 0.3 µs3 SDA TIMING CHARACTERISTICS tSU ; DAT1 Data set-up time ≥ 250 ns > 20 tCLCL – tRD tSU ; DAT2 SDA set-up time (before rep. START cond.) ≥ 250 ns > 1 µs1 tSU ; DAT3 SDA set-up time (before STOP cond.) ≥ 250 ns > 8 tCLCL tHD ; DAT Data hold time ≥ 0 ns > 8 tCLCL – tFC tSU ; STA Repeated START set-up time ≥ 14 tCLCL > 4.7 µs1 tSU ; STO STOP condition set-up time ≥ 14 tCLCL > 4.0 µs1 tBUF Bus free time ≥ 14 tCLCL > 4.7 µs1 tRD SDA rise time ≤ 1µs – 2 tFD SDA fall time ≤ 0.3µs < 0.3 µs3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 t CLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62 ns < tCLCL < 285 ns (16 MHz) > fOSC > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. TIMING SIO1 (I2C) INTERFACE tRD tSU;STA tBUF tSU;STO

0.7 VCC

0.3 VCC

tHIGHtLOWtHD;STA tSU;DAT1 tHD;DAT tSU;DAT2 tSU;DAT3 START condition repeated START condition SDA (INPUT/OUTPUT) SCL (INPUT/OUTPUT) STOP condition START or repeated START condition SU00107A

1999 Jul 23 13

Figure 1. External Program Memory Read Cycle Figure 2. External Data Memory Read Cycle

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Figure 3. External Data Memory Write Cycle Figure 4. Shift Register Mode Timing Figure 5. External Clock Drive

1999 Jul 23 15

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 6. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 7. Float Waveform Figure 8. ICC Test Condition, Active Mode exceed the IOL1 specification.

1999 Jul 23 16

Figure 9. ICC Test Condition, Idle Mode Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 11. ICC Test Condition, Power Down Mode exceed the IOL1 specification.

1999 Jul 23 17

produce only encrypted data. other lock bit can still be programmed. Figure 14. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 4. required on port 0 for this operation. encryption table itself cannot be read out. satisfies the timing specifications, is suitable. Table 4. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5 V±10% during programming and verification.

 Trademark phrase of Intel Corporation.

1999 Jul 23 18

Figure 12. Programming Configuration

25 PULSES

Figure 13. PROG Waveform

0 ENABLE

Figure 14. Program Verification

1999 Jul 23 19

• FOR PROGRAMMING VERIFICATION SEE FIGURE 12.

FOR VERIFICATION CONDITIONS SEE FIGURE 14. Figure 15. EPROM Programming and Verification

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 20

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 21

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 22

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 23

Philips Semiconductors Product specification 87C652/87C65480C51 8-bit microcontroller 8K/16K, 256 OTP, I2C

1999 Jul 23 24

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 07-99 Document order number: 9397-750-06607 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.