87C54 PHILIPS
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Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers 3-2151996 Aug 16
DESCRIPTION
The 87C54/87C58 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C54/87C58 has the same instruction set as the 80C51. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 87C58 contains 32k × 8 EPROM memory, and the 87C54 contains 16k × 8 EPROM memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, two-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C54/87C58 can be expanded using standard TTL compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications. See 80C52/54/58 datasheet for ROM device specification.
FEATURES
- 80C51 central processing unit
- 16k × 8 EPROM expandable externally to 64k bytes (87C54)
- 16k × 8 EPROM (87C54) and 32k × 8 EPROM expandable externally to 64k bytes (87C58) – Improved Quick Pulse programming algorithm – Two level program security system – 32 byte encryption array
- 256 × 8 RAM, expandable externally to 64k bytes
- Three 16-bit timer/counters – T2 is an up/down counter
- Four 8-bit I/O ports
- Full-duplex enhanced UART – Framing error detection – Automatic address recognition
- Power control modes – Idle mode – Power-down mode
- Once (On Circuit Emulation) Mode
- Five package styles
- OTP package available
- Programmable clock out
- 6 interrupt sources
- 2 level priority PIN CONFIGURATIONS 20 21 40T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC DUAL IN-LINE PACKAGE SU00748
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-216
ORDERING INFORMATION
16k × 8 EPROM 1 32k × 8 EPROM 1 TEMPERATURE RANGE °C AND PACKAGE FREQUENCY DRAWING NUMBER P87C54EBP N P87C58EBP N OTP 0 to +70, 40-Pin Plastic Dual In-line Package 16MHz SOT129-1 P87C54EBF FA P87C58EBF FA UV 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window16MHz 0590B P87C54EBA A P87C58EBA A OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 16MHz SOT187-2 P87C54EBL KA P87C58EBL KA UV 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window16MHz 1472A P87C54EBB B P87C58EBB B OTP 0 to +70, 44-Pin Plastic Quad Flat Pack 16MHz SOT307-2 P87C54EFP N P87C58EFP N OTP –40 to +85, 40-Pin Plastic Dual In-line Package 16MHz SOT129-1 P87C54EFF FA P87C58EFF FA UV –40 to +85, 40-Pin Ceramic Dual In-line Package w/Window16MHz 0590B P87C54EFA A P87C58EFA A OTP –40 to +85, 44-Pin Plastic Leaded Chip Carrier 16MHz SOT187-2 P87C54EFB B P87C58EFB B OTP –40 to +85, 44-Pin Plastic Quad Flat Pack 16MHz SOT307-2 P87C54IBP N P87C58IBP N OTP 0 to +70, 40-Pin Plastic Dual In-line Package 24MHz SOT129-1 P87C54IBF FA P87C58IBF FA UV 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window24MHz 0590B P87C54IBA A P87C58IBA A OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 24MHz SOT187-2 P87C54IBL KA P87C58IBL KA UV 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window24MHz 1472A P87C54IBB B P87C58IBB B OTP 0 to +70, 44-Pin Plastic Quad Flat Pack 24MHz SOT307-2 P87C54IFP N P87C58IFP N OTP –40 to +85, 40-Pin Plastic Dual In-line Package 24MHz SOT129-1 P87C54IFF FA P87C58IFF FA UV –40 to +85, 40-Pin Ceramic Dual In-line Package w/Window24MHz 0590B P87C54IFA A P87C58IFA A OTP –40 to +85, 44-Pin Plastic Leaded Chip Carrier 24MHz SOT187-2 P87C54IFB B P87C58IFB B OTP –40 to +85, 44-Pin Plastic Quad Flat Pack 24MHz SOT307-2 NOTE: 1. OTP = One Time Programmable EPROM. UV = Erasable EPROM. LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS T2EX RxD TxD INT0 INT1 WR RD SECONDARY FUNCTIONS RST EA PSEN ALE VSSVCC XTAL1 XTAL2 SU00732
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-217
1996 Aug 16 3-218
Table 1. 87C54/87C58 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.
- Reset value depends on reset source.
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-219
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS LCC 614 0 18 28 Pin Function
1 NC*
2 T2/P1.0 3 T2EX/P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7
10 RST
11 RxD/P3.0
12 NC*
13 TxD/P3.1
14 INT0
/P3.2 15 INT1 /P3.3 Pin Function 16 T0/P3.4 17 T1/P3.5 18 WR /P3.6 19 RD /P3.7
20 XTAL2
21 XTAL1
23 NC*
24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15
32 PSEN
33 ALE/PROG
34 NC*
/VPP 36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 44 V CC SU00061* DO NOT CONNECT PLASTIC QUAD FLAT PACK PIN FUNCTIONS PQFP 44 34 12 22 Pin Function 1 P1.5 2 P1.6 3 P1.7
4 RST
5 RxD/P3.0
6 NC*
7 TxD/P3.1
8 INT0
/P3.2 9 INT1 /P3.3 10 T0/P3.4 11 T1/P3.5 12 WR /P3.6 13 RD /P3.7
14 XTAL2
15 XTAL1
17 NC*
18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15
26 PSEN
27 ALE/PROG
28 NC*
/VPP 30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0 38 V CC
39 NC*
40 T2/P1.0 41 T2EX/P1.1 42 P1.2 43 P1.3 44 P1.4 SU00062* DO NOT CONNECT
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-220
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and receives code bytes during EPROM programming. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: 1 2 40 I T2 (P1.0): Timer/Counter 2 external count input/Clockout 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I IL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: I IL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG ) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 8XC58 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 7FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. This pin also receives the 12.75V programming supply voltage (VPP ) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.
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Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1). 1/2 the oscillator frequency. machine cycles (24 oscillator periods), while the oscillator is running. CC and RST must come up at the same time for a proper start-up. condition when a voltage above VIH1 is applied to RESET. the same manner as a power-on reset. the Power Down mode is terminated. and the on-chip RAM to retain their values. oscillator to restart and stabilize (normally less than 10ms).
- When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
- The windowed parts must be covered with an opaque label to assure proper chip operation. ONCE Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems using the 8XC58 without the 8XC58 having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC58 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Table 2. External Pin Status During Idle and Power-Down Mode
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-222
The 87C54/87C58 has a new feature. A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed (1) to input the external clock for Timer/Counter 2 or (2) to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: OscillatorFrequency 4 (65536RCAP2H, RCAP2L) In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. Enhanced UART The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 87C54/87C58 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 1). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 2. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 3. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “|Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. Reduced EMI Mode The AO bit (AUXR.0) in the AUXR register, when set, disables the ALE output. 8XC58 Reduced EMI Mode AUXR (0X8E) 76543210 AO: Turns off ALE output.
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The 87C54/87C58 has a 6-source two-level interrupt structure. and IP which are identical in function to those on the 80C51. priority level interrupt that was stopped will be completed. Table 3. Interrupt Table frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. other modes, in any serial transmission. Must be cleared by software. the other modes, in any serial reception (except see SM2). Must be cleared by software. Figure 1. SCON: Serial Port Control Register
1996 Aug 16 3-224
Figure 2. UART Framing Error Detection – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 3. UART Multiprocessor Communication, Automatic Address Recognition
- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
of this specification is not implied.
- This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
- Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-225
DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP 1 MAX UNIT VIL Input low voltage, except EA –0.5 0.2VCC –0.1 V VIL1 Input low voltage to EA 0 0.2VCC –0.3 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 37 IOL = 1.6mA2 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN7 IOL = 3.2mA2 0.45 V VOH Output high voltage, ports 1, 2, 33 IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 8, PSEN3 IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 35 See note 4 –650 µA ILI Input leakage current, port 0 0.45 VIN < VCC – 0.3 ±10 µA ICC Power supply current (See Figure 11): Active mode @ 16MHz See note 10 15 32 mA Idle mode @ 16MHz 3 5 mA Power-down mode T amb = 0 to +70°C 10 75 µA Tamb = –40 to +85°C 100 µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance9 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I OL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to 85°C, ITL = –750µA. 6. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 7. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 8. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 9. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF). 10. See Figures 12 through 15 for ICC test condition.
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
1996 Aug 16 3-226
AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 4 Oscillator frequency Speed versions : E 3.5 16 MHz tLHLL 4 ALE pulse width 85 2tCLCL –40 ns tAVLL 4 Address valid to ALE low 22 tCLCL –40 ns tLLAX 4 Address hold after ALE low 32 tCLCL –30 ns tLLIV 4 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 4 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 4 PSEN pulse width 142 3tCLCL –45 ns tPLIV 4 PSEN low to valid instruction in 82 3tCLCL –105 ns tPXIX 4 Input instruction hold after PSEN 0 0 ns tPXIZ 4 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 4 Address to valid instruction in 207 5tCLCL –105 ns tPLAZ 4 PSEN low to address float 10 10 ns Data Memory tRLRH 5, 6 RD pulse width 275 6tCLCL –100 ns tWLWH 5, 6 WR pulse width 275 6tCLCL –100 ns tRLDV 5, 6 RD low to valid data in 147 5tCLCL –165 ns tRHDX 5, 6 Data hold after RD 0 0 ns tRHDZ 5, 6 Data float after RD 65 2tCLCL –60 ns tLLDV 5, 6 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 5, 6 Address to valid data in 397 9tCLCL –165 ns tLLWL 5, 6 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 5, 6 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 5, 6 Data valid to WR transition 13 tCLCL –50 ns tWHQX 5, 6 Data hold after WR 13 tCLCL –50 ns tQVWH 6 Data valid to WR high 287 7tCLCL –150 ns tRLAZ 5, 6 RD low to address float 0 0 ns tWHLH 5, 6 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 8 High time 20 20 tCLCL +tCLCX ns tCLCX 8 Low time 20 20 tCLCL +tCHCX ns tCLCH 8 Rise time 20 20 ns tCHCL 8 Fall time 20 20 ns Shift Register tXLXL 7 Serial port clock cycle time 750 12tCLCL ns tQVXH 7 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 7 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 7 Input data hold after clock rising edge 0 0 ns tXHDV 7 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
Philips Semiconductors Preliminary specification 87C54/87C58CMOS single-chip 8-bit microcontrollers
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AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK 4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 4 Oscillator frequency Speed versions : I 3.5 24 MHz tLHLL 4 ALE pulse width 43 2tCLCL –40 ns tAVLL 4 Address valid to ALE low 17 tCLCL –25 ns tLLAX 4 Address hold after ALE low 17 tCLCL –25 ns tLLIV 4 ALE low to valid instruction in 102 4tCLCL –65 ns tLLPL 4 ALE low to PSEN low 17 tCLCL –25 ns tPLPH 4 PSEN pulse width 80 3tCLCL –45 ns tPLIV 4 PSEN low to valid instruction in 65 3tCLCL –60 ns tPXIX 4 Input instruction hold after PSEN 0 0 ns tPXIZ 4 Input instruction float after PSEN 17 tCLCL –25 ns tAVIV 4 Address to valid instruction in 128 5tCLCL –80 ns tPLAZ 4 PSEN low to address float 10 10 ns Data Memory tRLRH 5, 6 RD pulse width 150 6tCLCL –100 ns tWLWH 5, 6 WR pulse width 150 6tCLCL –100 ns tRLDV 5, 6 RD low to valid data in 118 5tCLCL –90 ns tRHDX 5, 6 Data hold after RD 0 0 ns tRHDZ 5, 6 Data float after RD 55 2tCLCL –28 ns tLLDV 5, 6 ALE low to valid data in 183 8tCLCL –150 ns tAVDV 5, 6 Address to valid data in 210 9tCLCL –165 ns tLLWL 5, 6 ALE low to RD or WR low 75 175 3tCLCL –50 3tCLCL +50 ns tAVWL 5, 6 Address valid to WR low or RD low 92 4tCLCL –75 ns tQVWX 5, 6 Data valid to WR transition 12 tCLCL –30 ns tWHQX 5, 6 Data hold after WR 17 tCLCL –25 ns tQVWH 6 Data valid to WR high 162 7tCLCL –130 ns tRLAZ 5, 6 RD low to address float 0 0 ns tWHLH 5, 6 RD or WR high to ALE high 17 67 tCLCL –25 tCLCL +25 ns External Clock tCHCX 8 High time 17 17 tCLCL –tCLCX ns tCLCX 8 Low time 17 17 tCLCL –tCHCX ns tCLCH 8 Rise time 5 5 ns tCHCL 8 Fall time 5 5 ns Shift Register tXLXL 7 Serial port clock cycle time 505 12tCLCL ns tQVXH 7 Output data setup to clock rising edge 283 10tCLCL –133 ns tXHQX 7 Output data hold after clock rising edge 3 2tCLCL –80 ns tXHDX 7 Input data hold after clock rising edge 0 0 ns tXHDV 7 Clock rising edge to input data valid 283 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 87C58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 24MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 3-226.
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AVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Figure 4. External Program Memory Read Cycle Figure 5. External Data Memory Read Cycle
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Figure 6. External Data Memory Write Cycle Figure 7. Shift Register Mode Timing Figure 8. External Clock Drive
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AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 9. AC Testing Input/Output OH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 10. Float Waveform Figure 11. ICC vs. Frequency
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Figure 12. ICC Test Condition, Active Mode Figure 13. ICC Test Condition, Idle Mode Figure 14. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 15. ICC Test Condition, Power Down Mode
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width and number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 16. Note that the 87C58 is running with a 4 to 6MHz device is executing internal address and program data transfers. low 5 times as shown in Figure 17. programmed, verification cycles will produce only encrypted data. data. The encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. light with wavelengths shorter than approximately 4,000 angstroms. Erasure leaves the array in an all 1s state. programmed, in addition to the above, verify mode is disabled. above apply and all external program memory execution is disabled. 32 bytes of encryption array are initially unprogrammed (all 1s). Trademark phrase of Intel Corporation.
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Table 4. EPROM Programming Modes
- ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
- VCC = 5V±10% during programming and verification.
programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs. Table 5. Program Security Bits is sampled and latched on Reset, and further programming of the EPROM is disabled. 3 P P Same as 2, also verify is disabled.
- P – programmed. U – unprogrammed.
- Any other combination of the security bits is not defined.
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Figure 16. Programming Configuration
5 PULSES
Figure 17. PROG Waveform Figure 18. Program Verification
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- FOR PROGRAMMING VERIFICATION SEE FIGURE 16.
FOR VERIFICATION CONDITIONS SEE FIGURE 18. Figure 19. EPROM Programming and Verification